{"id":"f1cae444-ce90-4b93-a831-a591cd5ced9f","arxiv_id":"2607.15830","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":5,"one_line_summary":"Linearizing RTL logic cones into breadth-first sequences and processing them with Mamba-2 sequence models yields better arrival-time, WNS, and TNS predictions than graph-based baselines on 21 open-source designs.","lead":"RTL-Sequencer replaces graph neural networks with sequence models (Mamba-2) for chip timing prediction at the register-transfer level, turning each logic cone into a breadth-first ordered list. A generalist might read it because cheaper, earlier timing estimates could shorten chip design loops and the sequence-based approach scales better than graph transformers.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Table 3's performance margins lack error bars and significance tests; 'consistent surpasses' is not yet established.","rationale":"The reader's weakest assumption targets the BFT linearization's information loss, which is a plausible theoretical weakness. However, the paper's central claim is fundamentally empirical: it reports quantitative improvements over state-of-the-art baselines. The most direct threat to that claim is that the reported margins are not shown to be statistically reliable. With no error bars, no seeds, no per-design results, and no released code/data, a reader cannot distinguish a genuine algorithmic advantage from favorable noise or implementation choices. The BFT concern is real but would only matter if the empirical results hold; if the results are not robust, the entire contribution is undermined regardless of representational theory. The ablation study and consistent trends partially mitigate this, but they too lack variance information. Therefore the verdict should remain CONDITIONAL, with the condition being the addition of statistical validation and reproducible artifacts. I only partially agree with the reader because the reader focused on theoretical information loss rather than the statistical validity of the empirical evidence, though both are legitimate concerns.","tokens_in":11920,"tokens_out":6376,"duration_ms":65216,"concrete_test":"Release code and dataset; run the full Table 3 comparison 10 times with different random seeds, compute mean±std AT MAPE per fold, and apply a paired test (e.g., Wilcoxon signed-rank over the 21 designs) between RTL-Sequencer and CircuitFusion for AT. If the 95% confidence intervals overlap or p>0.05, the phrase 'consistently surpasses' is not justified.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim in Sec. 5.2 is that RTL-Sequencer 'consistently surpasses prior approaches across all evaluated timing metrics,' with AT MAPE 17.24% vs 20.29% for the next-best CircuitFusion. This is a 3-percentage-point gap, but the paper reports no variance across seeds, no per-fold/per-design breakdown, and no statistical test. With only 21 designs in 5-fold cross-validation, each test fold has only ~4 designs; a single large design can dominate the aggregate MAPE. Moreover, all baselines are reimplemented by the authors, and no code or dataset is released, so there is no independent verification that the hyperparameters and training setups are comparable. The same issue applies to Fig. 4's claim that all sequence models surpass graph-based solutions. If the gap between RTL-Sequencer and CircuitFusion falls within run-to-run variability or depends on one or two favorable designs, the paper's central empirical claim would not be supported. Thus the load-bearing condition—that the reported improvements are real and reproducible—is currently unverified.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes RTL-Sequencer, a sequence-based framework for RTL timing prediction. Logic cones are linearized by inverse breadth-first traversal and processed with Mamba-2 linear sequence models, augmented by four techniques: stochastic shuffling, bidirectional sequence modeling, a differential (global-minus-depth-local) operation, and a hybrid GNN-sequence architecture. Experiments on 21 open-source RTL designs with 5-fold cross-validation report AT MAPE 17.24%, WNS MAPE 17.66%, and TNS MAPE 23.92%, outperforming the evaluated graph-based and transformer baselines. The authors argue this establishes a scalable sequence-based paradigm with global receptive fields and linear complexity.","tokens_in":1366,"tokens_out":1559,"duration_ms":48090,"significance":"If the reported gains are reproducible and general, the paper makes a useful contribution: it challenges the graph-centric default in RTL timing prediction and shows that modern linear sequence models can be competitive or better with better scalability. The architecture is clearly described, the ablation study isolates each proposed component, and the comparison includes several strong recent baselines. The design-partitioned 5-fold protocol is appropriate for generalization claims. However, the central empirical claim is currently under-supported because no variance or significance information is reported, and the theoretical 'lossless encoding' statement in Section 3 is incorrect as written. The lack of released code/data also prevents independent verification of the baseline reimplementations.","major_comments":[{"comment":"The central claim 'consistently surpasses prior approaches' rests on aggregate MAPE/R/R² values from 5-fold cross-validation over only 21 designs, so each test fold contains roughly 4 designs. No per-design or per-fold results, standard deviations across seeds, confidence intervals, or significance tests are reported. The AT MAPE improvement over CircuitFusion is 17.24% vs. 20.29%; without variance estimates this margin could lie within run-to-run variability or be dominated by one or two large designs. Please report per-design and per-fold errors, seed variance, and a paired significance test (e.g., Wilcoxon or bootstrap) on design-level errors. The same issue applies to Figure 4's claim that all sequence models surpass graph-based solutions. This is load-bearing because the paper's contribution is empirical.","section":"Sec. 5.2, Table 3"},{"comment":"The breadth-first linearization is the core enabler of the method, but the paper provides neither a formal guarantee nor a quantitative analysis that the linearization preserves enough directed timing information. Section 4.1 asserts BFT 'preserves the hierarchical progression of signal propagation,' while Section 4.4 concedes that BFT 'frequently places unrelated nodes at the same BFT depth,' making them adjacent in the sequence. Since a fixed BFT sequence with intra-level shuffling does not encode the DAG exactly, the model must recover timing-critical paths from an approximate linearization. The hybrid GNN module mitigates this, but the paper should evaluate sensitivity to the linearization (e.g., alternative traversals, different shuffling policies, or random permutations at inference) or provide an information-theoretic bound for the cone sizes considered. Without this, the general","section":"Sec. 4.1, Sec. 4.4"},{"comment":"The statement that historical context is 'losslessly encoded by preceding nodes while maintaining linear computational complexity' is false for finite-dimensional hidden states: any fixed-size state is a lossy compression of an arbitrarily long prefix. This is not merely a wording issue, because the paper uses the lossless claim to motivate the entire sequence-based paradigm. Please replace it with a bounded-error or approximation statement, or show that for the finite logic-cone setting the state dimension is sufficient to represent the relevant timing information. The empirical results may still hold, but the theoretical motivation must be corrected.","section":"Sec. 3, Eq. (2)-(3)"}],"minor_comments":[{"comment":"The definition of E is garbled: 'E denotes the set of nodes corresponding to registers and combinational logic elements' repeats the definition of V; E should be the set of edges.","section":"Sec. 2"},{"comment":"The TNS row for RTL-Sequencer reports R²=0.76 in Table 4 but R²=0.77 in Table 3. Please reconcile.","section":"Table 4 vs. Table 3"},{"comment":"The mechanism is 'differential' (global minus depth-local), not merely 'differentiable.' The paper uses both terms interchangeably; recommend renaming to 'Differential Sequence Modeling' to match the cited Differential Transformer and to avoid confusion with differentiability.","section":"Sec. 4.4 and title"},{"comment":"References [3] and [4] appear to be the same TF-Predictor paper listed twice with different years and venues. Please merge or disambiguate.","section":"References [3] and [4]"},{"comment":"The shuffling rule is ambiguous: 'randomized within each BFT depth level with 50% probability' could mean per-cone, per-level, or per-node. Please specify the exact stochastic procedure and how permutations are synchronized across child nodes.","section":"Sec. 4.2"}],"recommendation":"major_revision","confidential_remarks":"The paper is within scope and the architectural idea is worth pursuing. The main barrier is empirical verification: the headline numbers need variance/significance analysis and preferably a reproducibility release. If the authors can provide design-level error distributions and confidence intervals, the central claim may become solid. The false lossless-encoding statement should be corrected regardless."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nThe paper is worth a look if you care about ML-based RTL timing. The core move—linearize each logic cone by reversed BFT and feed it to a Mamba-style sequence model—is new in this space, and it is a clean way to get global receptive fields at linear complexity. The four customizations (shuffling, bidirectional, differential/depth-local subtraction, and a hybrid GNN wrapper) are reasonable engineering, and the ablations suggest each earns its keep. The comparison set is broad: GCN, GAT, SG-Former, RTL-Timer, RTLDistill, NUA-Timer, CircuitFusion, TF-Predictor. I believe the results are genuinely better, not just cherry-picked; the gains are consistent across AT, WNS, and TNS, and the basic-sequence baseline already beats graph models, which validates the paradigm.\n\nThe soft spots are mostly about evidence reporting. No error bars, no per-seed variance, no significance tests. With 21 designs split 5-fold, each test fold has only ~4 designs, so a single large cone can move aggregate MAPE by several points. All baselines were reimplemented by the authors, and no code or data is released, so nothing is independently reproducible yet. That makes the 'consistently surpasses' claim (Sec. 5.2) stronger than the evidence currently supports.\n\nThere are also a few smaller issues. Sec. 3's claim that the sequence model 'losslessly encodes' history is false for a finite state space; it's a useful approximation, not exact. The reference list has a duplicate (TF-Predictor appears as [3] and [4]). And calling the differential mechanism 'differentiable sequence modeling' is confusing—it is just global-minus-depth-local subtraction with a learned gate; the name overpromises. None of these is fatal.\n\nThe BFT linearization does place unrelated same-depth nodes adjacently, and shuffling is a patch around that. The authors don't offer a formal argument that the linearization preserves timing-critical path information, but the empirical results on these 21 designs suggest it is adequate in practice. I'm not going to call that a load-bearing flaw; it's a limitation to probe in follow-up work.\n\nOverall: the paper is a solid empirical contribution, clearly written, and the central idea is worth pursuing. It deserves a serious referee. For acceptance, I'd want error bars or significance tests, a per-design breakdown, and ideally code/data release. If you rely on its numbers, treat them as promising but not final.\n\nRecommendation: send to peer review; ask for statistical rigor and artifacts before publication.","headline":"A sensible sequence-based alternative to graph timing models with promising results, but the claimed 'consistent' superiority lacks variance reporting and public artifacts.","tokens_in":12629,"tokens_out":2317,"would_cite":true,"duration_ms":20645,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"RTL timing prediction improves when logic cones are read as linear sequences instead of graphs.","keywords":["RTL timing prediction","logic cone","sequence model","breadth-first traversal","linear complexity","state space model","timing analysis","design automation"],"falsifier":"If, on a synthetic logic cone where two nodes at the same BFT depth feed paths with very different delays, the predictor cannot separate their contributions – MAPE worsens as such same-depth collisions are introduced – the claimed information-preservation would fail. Concretely: generate cones with controlled same-depth sibling structure and compare RTL-Sequencer against a depth-first linearization baseline; if BFT no longer helps, the central mechanism is suspect.","tokens_in":11862,"feed_emoji":"⏱️","tokens_out":3019,"duration_ms":27642,"temperature":0.7,"pith_summary":"This paper argues that RTL timing prediction should be treated as a sequence-learning problem rather than a graph-learning problem. It shows that a logic cone – the directed circuit subgraph feeding an output register – can be flattened by breadth-first traversal into a node sequence, and that modern linear sequence models trained on such sequences predict arrival time, worst negative slack, and total negative slack more accurately than graph neural networks or graph transformers. On 21 open-source RTL designs with 5-fold cross-validation, it reports AT MAPE 17.24%, WNS MAPE 17.66%, and TNS MAPE 23.92%, all better than the baselines, while maintaining linear computational complexity and a global receptive field. If this holds, designers could get accurate timing feedback before synthesis and layout, shortening the design loop.","feed_headline":"Logic cones as sequences beat graph nets for chip timing","feed_subtitle":"Flattening each cone by breadth-first traversal lets a linear-time model reach 17% arrival-time error on 21 RTL designs.","key_machinery":"The key object is the BFT-linearized logic cone sequence. Each cone is traversed backward from the endpoint register, visiting nodes level by level; the resulting sequence carries a directional ordering that mirrors signal propagation. A linear sequence model (Mamba-2 in the implementation) updates a hidden state per node in linear time, giving each node implicit access to all predecessors. The four customizations – shuffling within BFT levels, bidirectional passes, differential depth-subtraction with a learned gate, and a GNN front-end – compensate for the topological information lost when a DAG is flattened into a fixed order.","core_discovery":"The central claim is that flattening each logic cone into an ordered sequence by inverse breadth-first traversal, then applying a linear sequence model, recovers enough of the cone's directed timing structure to outperform graph-based predictors. To make this work, the authors add four mechanisms: random shuffling of nodes within each BFT level as data augmentation, bidirectional sequence passes so later nodes influence earlier ones, a differentiable 'global minus depth-local' embedding subtraction that suppresses same-depth neighbors' spurious influence, and a hybrid pipeline that first runs a GNN for local structure then the sequence model for long-range depth. The result is a timing predi","pith_inferences":["The same BFT-linearization approach could extend to other cone-level prediction tasks in chip design, such as power or routability, where directed signal flow also matters and graph models face the same receptive-field limits.","The shuffling result suggests the model learns timing structure rather than a fixed node order; a stronger generalization test would measure performance on cones whose depth distribution lies far outside the training set.","One could probe the differential module by constructing synthetic cones where two same-depth nodes feed paths with very different delays; if the model still separates them, the depth-subtraction is doing the intended work."],"forward_implications":["Early RTL timing feedback could become accurate enough to guide design changes before synthesis, shortening design iterations.","Timing prediction no longer needs to trade off receptive field against computational cost: the sequence model provides both global reach and linear scaling.","Training on very large cones – tens of thousands of nodes – becomes practical on modest hardware because memory and time grow linearly with cone size.","The hybrid graph–sequence design indicates that local structure and global depth are complementary signals, and both can be captured end-to-end."],"fun_headline_variants":["Flatten cones, sequence them: new RTL timing method","Cone-to-sequence beats graph nets for chip timing","RTL timing with sequence models: 17% error on 21 designs","Breadth-first cone flattening enables scalable RTL timing","Sequence paradigm for RTL timing: faster and more accurate"],"cache_read_input_tokens":2304,"weakest_assumption_plain":"The whole approach rests on the assumption that flattening a logic cone into a breadth-first node sequence preserves enough of its directed timing-critical structure for a sequence model to recover it, even though BFT places unrelated same-depth nodes side by side.","fun_headline_variants_meta":{"raw":{"variants":["Flatten cones, sequence them: new RTL timing method","Cone-to-sequence beats graph nets for chip timing","RTL timing with sequence models: 17% error on 21 designs","Breadth-first cone flattening enables scalable RTL timing","Sequence paradigm for RTL timing: faster and more accurate"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000218,"raw_usage":{"total_tokens":1218,"prompt_tokens":627,"completion_tokens":591,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":371,"completion_tokens_details":{"reasoning_tokens":515}},"tokens_in":371,"tokens_out":591,"duration_ms":5930,"temperature":1.0,"reasoning_tokens":515,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-01T22:11:07.862808+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"If, on a synthetic logic cone where two nodes at the same BFT depth feed paths with very different delays, the predictor cannot separate their contributions – MAPE worsens as such same-depth collisions are introduced – the claimed information-preservation would fail. Concretely: generate cones with controlled same-depth sibling structure and compare RTL-Sequencer against a depth-first linearization baseline; if BFT no longer helps, the central mechanism is suspect.","supporting_citations":[],"review_version":1}