{"id":"b11158ff-5c44-4960-a4c1-f44be1d4f41c","arxiv_id":"2607.22498","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":7.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"An ILP over circuit gauge operators automates flag-based fault-tolerant state preparation, meeting or beating gate-count state of the art on 12 CSS codes and yielding a [[24,10,4]] Steane gadget with ~1.4e-4 block error on H2.","lead":"This paper casts fault-tolerant quantum state preparation as an integer linear program, producing circuits with equal or fewer gates than prior automated methods and demonstrating one on a trapped-ion quantum computer. This matters because smaller error-correction circuits directly reduce the overhead and noise of future quantum computation.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Fault-tolerance guarantee for ILP-generated circuits is not rigorously established: Sec. III's flag analysis omits measurement/preparation faults and Algorithm 1 is heuristic; a fault-injection check is needed.","rationale":"The reader's conditional verdict is appropriate. The central claim is plausible, but the FT guarantee has a concrete gap: the proof of the flag subcircuit in Section III only treats faults after two-qubit gates (Table I), not measurement or preparation faults, and Algorithm 1 is heuristic. This is a correctness risk, not an internal inconsistency, and it can be resolved by exhaustive fault-path verification. The hardware result is a single event, but that is secondary to the algorithmic claim. The gate-count comparisons are likely reproducible once code is released, and the paper itself acknowledges the heuristic nature of gauge generation, so the concern is addressable. No reason to move beyond CONDITIONAL; the reader's verdict stands.","tokens_in":12264,"tokens_out":4895,"duration_ms":56590,"concrete_test":"For each generated circuit (at minimum the [[24,10,4]] gadget), use a stabilizer simulator such as Stim to exhaustively inject all fault sets of size up to t (the claimed tolerance, e.g., 2 for distance-4 codes and 3 for distance-6/7 claims) at every operation, including ancilla preparation, two-qubit gates, and measurements. Check whether any undetected fault set produces a logical error of weight greater than t. Separately, run a brute-force enumeration of all gauge operators of weight ≤3 (instead of the heuristic Algorithm 1) and recompute the ILP cover; if the brute-force cover is strictly smaller or the fault injection finds an undetected error, the completeness gap is real and the FT claim needs correction.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim—that ILP produces fault-tolerant state preparation circuits with gate counts at or below SOTA—depends on the FT property of every generated circuit. Section III's proof that final-stage weight-3 flags add no new first-order errors (Table I) only analyzes Pauli faults occurring after each two-qubit gate. It does not model faults in the ancilla preparation (|+>) or the subsequent X-basis measurement. A measurement error can convert a real error into a false negative, and a preparation error can alter the flag syndrome; whether these can combine with data faults to produce an undetected logical error of weight > t is not shown. In addition, Algorithm 1 that generates the candidate gauge operators is explicitly heuristic and 'not guaranteed to be as large as possible' (Section II.A). If a dangerous spackle is not covered by any generated gauge, the ILP may return a circuit that satisfies the set-cover constraints but still admits an undetected logical error. Since the paper's headline is a universal claim over all 12 tested codes, this gap is load-bearing: it applies to every circuit, not just the hardware demo. The hardware result, while a single event without error bars, is secondary; the primary risk is that the FT certification itself is incomplete.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes an automated method for constructing flag-based fault-tolerant stabilizer state preparation circuits. The construction is framed as a weighted set-cover problem over circuit gauge operators, solved with integer linear programming (ILP). The authors describe a heuristic algorithm (Algorithm 1) that generates low-weight gauge operators, then select a set of gauge measurements whose detection syndromes cover all dangerous fault combinations. They apply the method to 12 CSS codes and report gate counts that match or beat prior state-of-the-art circuits, with improvements most pronounced for high-rate codes. They also implement a Steane error-correction gadget for the [[24,10,4]] two-block group algebra code and run it on Quantinuum H2, reporting a logical block error rate of about 1.4e-4 based on one logical error in 7117 accepted shots.","tokens_in":12601,"tokens_out":10466,"duration_ms":115573,"significance":"If the fault-tolerance guarantees can be rigorously established, this would be a solid and useful contribution. The ILP/gauge-operator formulation is a natural extension of earlier SAT-based and flag-at-origin methods, and the reported constant-factor gate-count improvements are valuable for near-term QEC subroutines. The paper also contains a rare hardware demonstration of an optimized logical gadget. The explicit circuits in the appendices and reproducible gate-count comparisons are assets. However, the central correctness claim depends on a fault-tolerance proof that is not yet complete, and on a heuristic gauge-generation step whose completeness is not certified. The contribution is conditionally significant pending those points.","major_comments":[{"comment":"The proof that a bare-ancilla weight-3 gauge measurement 'does not produce high-weight faults not seen in the original circuit C' examines only Pauli generators occurring after each two-qubit gate (Table I). It does not analyze faults in the |+> ancilla preparation or in the final X-basis measurement. A Z fault on the ancilla immediately after preparation propagates through the controlled gates into the data as PQR (the measured gauge operator), and a measurement fault can convert a legitimate non-trivial flag syndrome into a false negative. Neither of these single-fault channels is covered by Table I or the surrounding argument. Since this proof is the only formal justification that the promotion procedure preserves fault tolerance, the FT claim for all 12 circuits in Table II is not established. Please either extend the proof/table to all fault locations or provide exhaustive fault-inj","section":"Section III, Table I"},{"comment":"The ILP set-cover constraints in Eq. (5) are only over the gauge set G produced by Algorithm 1, which the paper states is 'not guaranteed to be as large as possible.' If a dangerous spackle is not covered by any generated gauge, the ILP is infeasible; but if the dangerous-spackle set S itself is under-generated, or the reduction by 'equivalent to an operator of weight ≤ t' is done incorrectly, the ILP can return a circuit that satisfies the constraints yet is not fault-tolerant. No certificate or exhaustive simulation is provided for the distance-5, -6, and -7 circuits in Table II. The completeness of S and of the generated gauge set is a load-bearing assumption for the paper's headline claim. Please add an explicit verification step or a proof of completeness for the generated gauge set.","section":"Section II.A; Eq. (5)"}],"minor_comments":[{"comment":"The hardware estimate 'one logical error in 7117 accepted shots implies a logical error rate of 1/7117 ~ 1.4e-4' is a point estimate from a single Bernoulli observation. With one event, the 95% confidence interval spans roughly an order of magnitude. Please report an interval (e.g., Wilson) and the calibration conditions, since the hardware claim is presented without uncertainty.","section":"Section IV A / Table III"},{"comment":"There are several typographical and formatting issues: '104 shots' should be '10^4 shots'; 'theJ7,1,3KSteane code' is missing bracket delimiters; and some exponent notation is garbled. The manuscript would benefit from a careful proofreading pass.","section":"Abstract / throughout"},{"comment":"The notation in Table I (e.g., 'IP', 'IP⊥', 'Q1R5', syndrome columns) is not explained in sufficient detail. Without a definition of the location labels and the convention for propagating generators, the reader cannot independently verify the table. An explicit derivation for one row would greatly improve accessibility.","section":"Table I / Section III"},{"comment":"The comparison to state-of-the-art gate counts relies on several external sources, including one private communication [19]. For reproducibility, please state the precise version and settings of the prior methods, and clarify whether all SOTA values use the same fault-tolerance definition (number of detected faults, post-selection criteria, and error model).","section":"Table II"}],"recommendation":"major_revision","confidential_remarks":"The core idea is promising and the gate-count results are interesting, but the paper in its current form does not rigorously establish the fault tolerance of the generated circuits. The two main gaps—the incomplete proof of the bare-ancilla weight-3 measurement and the heuristic completeness of Algorithm 1—are fixable within the scope of the manuscript by adding exhaustive fault-injection verification or completing the proof. If the authors provide that, I would be willing to reconsider favorably. The hardware result is a nice demonstration but should be presented with confidence intervals."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Let me give you the short version first. This paper does something real: it turns the flag-based promotion problem into a weighted set-cover ILP over circuit gauge operators, and it reports gate counts that meet or beat the previous SOTA on all 12 codes they test. The [[24,10,4]] Steane gadget with 89 FT gates vs 170 for flag-at-origin is a concrete win, and the H2 demo with sub-physical logical error rate is a nice pragmatic signal. I think the ILP formulation (Eq. 4, mapping flag detection to anticommutation with the spackle) is genuinely new and worth engaging with seriously.\n\nWhat the paper does well: the connection between flag circuits and circuit gauge operators is explained carefully, the promotion problem is cleanly reduced to an ILP, and the comparison against external SOTA gate counts is reasonable. They also don't overclaim in the discussion — they flag that their cost function is imperfect and that larger improvements might be possible.\n\nThe soft spots are real but not fatal. The main one is the fault-tolerance proof in Section III. The analysis of the weight-3 bare-ancilla flag gadget in Table I only considers Pauli faults after each two-qubit gate. It does not explicitly analyze faults in the |+> preparation or in the final X measurement. A measurement fault could, in principle, turn a detected fault into an undetected one, and the paper's claim that all first-order errors are equivalent to those in the original circuit is not supported for those locations. That is a gap in the proof of the headline guarantee, not a demonstrated counterexample. The reader's worry about Algorithm 1 being heuristic is less convincing: if the generator set is missing a gauge, the ILP just becomes infeasible for the spackles that need that gauge; it doesn't make an output circuit unsound. The real gap is the missing prep/measurement analysis.\n\nThe hardware result is one event in 7117 accepted shots, no error bars; that's a demonstration, not a rigorous validation. And there's no code or data released, which makes it harder to check the gate count claims. Those are addressable.\n\nBottom line: this is a solid paper with a real contribution, but the fault-tolerance guarantee is not fully established as written. It deserves a serious referee, not a desk reject. I'd ask the authors to supply either a complete proof that includes preparation and measurement faults, or exhaustive fault-injection simulation for each generated circuit, and ideally release the artifacts. If that comes through, the paper would be a strong contribution to the QEC toolkit.","headline":"Genuine ILP-based advance in flag circuit synthesis with SOTA-beating gate counts, but the FT guarantee is not fully proven — needs a rigorous fault-injection check.","tokens_in":13059,"tokens_out":6811,"would_cite":true,"duration_ms":67451,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":["03.67.Pp","03.67.Lx"],"model":"deepseek-v4-flash","headline":"ILP over circuit gauge operators produces fault-tolerant state-prep circuits at or below prior gate counts for all 12 codes tested, and a [[24,10,4]] Steane gadget with ~1.4e-5 per-qubit logical error rate on H2.","keywords":["fault-tolerant state preparation","integer linear programming","circuit gauge operators","flag-based error detection","Steane error correction","post-selection","quantum error correction","trapped-ion quantum computer"],"falsifier":"Run full state-vector simulation with a depolarizing noise model on one ILP-derived circuit (e.g., [[24,10,4]] or [[7,1,3]]) and enumerate all single-fault and pair-fault sets; if any fault set produces an output error of weight greater than t without triggering a flag, the fault-tolerance claim is falsified. Alternatively, exhaustively enumerate all gauge operators for a small code and check whether Algorithm 1 misses a gauge that is required to cover a dangerous spackle, which would falsify the completeness of the heuristic.","tokens_in":12163,"feed_emoji":"⚛️","tokens_out":6555,"duration_ms":65285,"temperature":0.7,"pith_summary":"This paper aims to show that fault-tolerant state-preparation circuits, essential for initializing logical qubits and for Steane/Knill error-correction gadgets, can be constructed automatically by solving an integer linear program over circuit gauge operators. The ILP selects a set of low-weight gauge operators whose measurement, implemented as flag subcircuits, detects every dangerous combination of up to t faults. Comparisons across 12 codes show the resulting circuits match or beat the gate counts of the two leading automated methods. A hardware demonstration on Quantinuum's H2 machine with a Steane gadget for the [[24,10,4]] code yields a block logical error rate of about 1.4e-4, about 1.4e-5 per logical qubit. If correct, this makes automated design of fault-tolerant state preparation practical for medium-size codes and points towards a general optimization-based approach to fault-tolerant circuit design.","feed_headline":"ILP beats prior state-prep circuits on all 12 codes tested","feed_subtitle":"A Steane gadget it found for the [[24,10,4]] code hit ~1.4e-5 logical errors per qubit on H2.","key_machinery":"The central object is the circuit gauge operator: a Pauli operator supported on spacetime locations of a circuit that is equivalent to the identity when inserted into the circuit. Flag subcircuits are shown to measure such operators, detecting exactly those fault sets whose spackle (the spacetime support of the propagated faults) anticommutes with the gauge operator. The task of promoting a circuit to tolerate t faults becomes weighted set cover: choose low-weight gauge operators (cost = weight + 1, corresponding to controlled-Pauli gates plus one measurement) whose anticommuting spackle sets cover all dangerous fault sets. The set-cover instance is solved by an integer linear program, with","core_discovery":"The paper's central claim is that flag-based fault-tolerant state preparation reduces to weighted set cover over circuit gauge operators: each flag subcircuit measures a gauge operator, and the set of faults it detects is exactly those whose 'spackle' (spacetime support) anticommutes with that operator. Choosing which gauge operators to measure so that all dangerous fault sets are covered is a weighted set cover problem, solved here with integer linear programming. The authors show that this ILP construction produces circuits with gate counts equal to or lower than the state of the art for all 12 codes considered, detecting up to three faults, and that a Steane error-correction gadget for th","pith_inferences":["The cost function used in the ILP (weight + 1) ignores the fact that each added flag subcircuit introduces new fault locations; a more accurate cost would likely lead to even smaller circuits, as the authors themselves suggest.","The same gauge-operator covering approach could be extended to promote non-fault-tolerant circuits for logical operations (e.g., fold-transversal gates), although this requires embedding a decoder in the exit criterion.","The hardware result is a single code and a single device; the claim that gate-count reduction translates into lower logical error rates would be strengthened by applying the ILP pipeline to several codes and comparing on multiple machines."],"forward_implications":["For every one of the 12 codes tested, the ILP-derived circuits match or beat the gate counts of the two prior automated methods, with the largest reductions on high-rate codes (e.g., 89 vs 170 operations for the [[24,10,4]] 2BGA code).","The method automates construction of flag circuits that detect up to three faults, scaling to codes of distance up to 7 with block sizes up to 42 qubits.","The [[24,10,4]] Steane gadget produced one logical error in 7,117 accepted shots (block error ~1.4e-4, per-qubit ~1.4e-5), with only ~1.6% of shots post-selected, demonstrating fault-tolerant preparation below typical physical two-qubit gate error rates.","Because the ILP formulation is based on the circuit gauge operator formalism, it provides a unified explanation of flag circuits and can be applied to other fault-tolerant subroutines beyond state preparation."],"fun_headline_variants":["ILP-based flag circuits match or beat prior art on 12 codes","ILP automates fault-tolerant state prep, cutting gates on 12 codes","Flag prep via ILP: equal or fewer gates, up to 3 errors","ILP optimizes flag circuits for 12 quantum codes","Automated flag prep with ILP: equal or fewer gates than prior"],"cache_read_input_tokens":2304,"weakest_assumption_plain":"The paper's fault-tolerance guarantee assumes Algorithm 1 finds every gauge operator needed to cover dangerous spackle sets, and that the final-stage proof, which analyzes faults after two-qubit gates, also covers ancilla preparation and measurement faults; neither is proven.","fun_headline_variants_meta":{"raw":{"variants":["ILP-based flag circuits match or beat prior art on 12 codes","ILP automates fault-tolerant state prep, cutting gates on 12 codes","Flag prep via ILP: equal or fewer gates, up to 3 errors","ILP optimizes flag circuits for 12 quantum codes","Automated flag prep with ILP: equal or fewer gates than prior"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.00089,"raw_usage":{"total_tokens":3700,"prompt_tokens":795,"completion_tokens":2905,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":539,"completion_tokens_details":{"reasoning_tokens":2809}},"tokens_in":539,"tokens_out":2905,"duration_ms":19714,"temperature":1.0,"reasoning_tokens":2809,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-01T04:32:52.996930+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run full state-vector simulation with a depolarizing noise model on one ILP-derived circuit (e.g., [[24,10,4]] or [[7,1,3]]) and enumerate all single-fault and pair-fault sets; if any fault set produces an output error of weight greater than t without triggering a flag, the fault-tolerance claim is falsified. Alternatively, exhaustively enumerate all gauge operators for a small code and check whether Algorithm 1 misses a gauge that is required to cover a dangerous spackle, which would falsify the completeness of the heuristic.","supporting_citations":[],"review_version":1}