{"id":"0992b1e4-aea6-4b2b-8bea-cf5f3142d010","arxiv_id":"2607.23225","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":4,"one_line_summary":"ParasGB releases the first public graph benchmark for predicting post-layout parasitic capacitance and resistance from pre-layout analog/SRAM circuit schematics.","lead":"ParasGB is a new public benchmark that gives AI models circuit graphs with real measured wire resistances and capacitances from analog and memory chip designs. It lets researchers train and compare machine-learning models that predict parasitic effects before the physical layout is finished.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Analog split is internally inconsistent: IDs 5 and 7 are exact duplicates, and Appendix D.1's training list omits three circuit IDs, so the held-out ID 5 may have its identical twin in training.","rationale":"The reader's weakest assumption points to a duplicate of ID 5 (as ID 7) contaminating the held-out test. I agree this is the most load-bearing concern because it directly threatens the paper's cross-design generalization results. However, the reader's specific claim that 'ID 7 is in the training split (Appendix D.1)' is not fully supported by the text: the printed D.1 training list explicitly omits ID 7 along with IDs 13 and 19. The list is internally inconsistent with the 20-circuit dataset, so the correct interpretation is ambiguous. If the true training split includes ID 7 (as a likely typo in the range), the contamination is real; if not, the paper still has a serious data-curation and documentation flaw. Either way, the evaluation protocol cannot be trusted without repository verification. The concrete test of inspecting the actual split files and data hashes will settle which scenario holds. The verdict remains CONDITIONAL: the dataset contribution can be salvaged by clarifying/fixing the split, but the experimental claims should not be taken at face value until then.","tokens_in":24901,"tokens_out":6503,"duration_ms":72492,"concrete_test":"Inspect the ParasGB repository's split configuration and raw data: (1) Parse the analog train/valid/test split files and list which circuit IDs are in each; check specifically whether ID 7 is in the training set. (2) Compare the netlist or processed graph files for IDs 5 and 7, e.g., by computing hashes of the raw extracted parasitics or the graph statistics in Table 2. If ID 5 and ID 7 share identical underlying data and ID 7 is in training, the held-out evaluation on ID 5 is invalid. (3) Verify whether IDs 13 and 19 appear in any split; if they are absent, confirm with the authors whether they were discarded or omitted by typo.","verdict_should_be":"CONDITIONAL","load_bearing_attack":"The paper's central claim of cross-design generalization on analog circuits depends on the held-out test IDs (5, 14, 20) being genuinely unseen. Table 2 lists IDs 5 and 7 with identical node/edge counts, identical Cg and Reff statistics, and the same reference [19]; Appendix A.2 describes them with identical text. This strongly suggests the same physical design appears twice. Appendix D.1 says circuits 1–4, 6, 8–12, and 15–18 are used for training/validation, while 5, 14, 20 are held out. But this training list excludes IDs 7, 13, and 19, so either (a) ID 7 is actually in training (if the intended range was 6–13 or similar), making the held-out ID 5 a duplicate of a training circuit and contaminating the reported held-out results; or (b) ID 7 (and 13, 19) are unused, in which case the paper misleadingly lists 20 analog circuits and fails to explain why three are absent from experiments. In either case, the analog evaluation protocol is not well-defined and the central claim of a clean held-out evaluation is unsupported as written.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents ParasGB, a benchmark suite for pre-layout parasitic prediction on analog/mixed-signal and SRAM circuit graphs. It provides node-level ground-capacitance, edge-level effective-resistance, and edge-level coupling-capacitance labels extracted with commercial EDA tools from tape-out-proven designs, and defines unified regression and classification tasks. The paper benchmarks several general-purpose GNNs and two circuit-specific baselines on these tasks, reporting mixed results that highlight label imbalance and cross-design generalization challenges.","tokens_in":25222,"tokens_out":4994,"duration_ms":51968,"significance":"If the data-integrity issues are resolved, ParasGB would be a valuable contribution: it is the first open-source benchmark suite of its kind with post-layout RC labels, it is built from industrial designs using commercial extraction tools, and it ships a public repository, an OGB-style API, and unusually detailed preprocessing and normalization equations. The SRAM subset is particularly notable for its scale (up to 11.7M nodes) and dense coupling-capacitance labels. The benchmark also exposes realistic challenges (long-tail distributions, structural heterogeneity) that are likely to be useful to the graph-learning and EDA communities. However, the analog subset contains an apparent duplicate design and the split description omits three listed circuits, so the benchmark's core claim of 20 distinct analog designs and a clean cross-design evaluation is not currently supported as written.","major_comments":[{"comment":"IDs 5 and 7 in Table 2 are identical in every reported statistic (nodes, edges, C_g, R_eff, citation [19]), and Appendix A.2 gives them the same verbatim description. This strongly indicates the same physical design is listed twice. Since ID 5 is held out for cross-design evaluation and ID 7 is not listed in the training set of Appendix D.1, the duplicate does not necessarily contaminate training under the stated split, but it invalidates the claim of 20 distinct analog circuits and makes the held-out evaluation ambiguous. The authors must either confirm that IDs 5 and 7 are distinct and explain the identical entries, or deduplicate the dataset and re-run the affected experiments.","section":"Table 2 / Appendix A.2"},{"comment":"The analog split is not well-defined as written. Appendix D.1 states that circuits 1–4, 6, 8–12, and 15–18 are used for training/validation while 5, 14, and 20 are held out, but this accounts for only 17 of the 20 circuits listed in Table 2. IDs 7, 13, and 19 are omitted from the split and from all reported experiments. If the intended training range included ID 7, then the held-out ID 5 is a duplicate of a training circuit and the analog cross-design results are contaminated. If IDs 7, 13, and 19 are intentionally unused, the manuscript must say so and remove them from the claimed dataset inventory. As written, the evaluation protocol is not reproducible from the information given.","section":"Appendix D.1 / Tables 8, 9, 13, 14"},{"comment":"The manuscript repeatedly emphasizes '20 analog circuits' and uses this count to support the benchmark's breadth. The duplicate ID 5/7 and the absence of IDs 13 and 19 from experiments mean the actual number of distinct, used analog designs is at most 17. All statistics in Table 2, the histograms in Appendix A.3, and the scale groupings in Table 4 should be reconciled with the split description. This is load-bearing for the central claim of a comprehensive analog benchmark.","section":"Section 3.1 / Table 2"}],"minor_comments":[{"comment":"References [19] and [20] are the same paper: K. N. Leung and P. K. T. Mok, 'A CMOS voltage reference based on weighted Delta-V_GS for CMOS low-dropout linear regulators,' JSSC 38(1), 2003. They should be merged and cited consistently.","section":"References"},{"comment":"The set notation 'circuits 1–4, 6, 8–12, and 15–18' is ambiguous regarding whether ID 7 is included. Please use an explicit enumeration or set-builder notation.","section":"Appendix D.1"},{"comment":"The SRAM capacitance validity window in Eq. (3), 1e-21 < C < 1e-15, is introduced without physical justification. The replacement of invalid ground-capacitance labels with 1e-30 in Eq. (5) also deserves a comment on how such measurements arise and whether they could bias the normalized distribution.","section":"Appendix C.2"},{"comment":"The row label 'sram' appears to be an abbreviation of 'ssram' used elsewhere (e.g., Table 6 and Appendix A.2). Please use consistent dataset names.","section":"Table 3"}],"recommendation":"major_revision","confidential_remarks":"The duplicate ID 5/7 and the unexplained omission of IDs 7, 13, and 19 are likely copy-paste or listing errors rather than intentional design, but they are exactly the kind of issue that must be fixed before this benchmark can be trusted. If the authors confirm ID 7 is not in training, the impact is reduced but the dataset inventory still needs correction. I would like to see a clear data-integrity statement in the revision."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Reading ParasGB, the dataset is real and the release is careful: commercial EDA extraction, an OGB-style API, tasks for Cg, Reff, and Cc, and baseline results across eight models. This is the first public benchmark with RC labels for pre-layout AMS/SRAM circuits, and the documentation of the preprocessing pipeline is unusually thorough. Credit is due for shipping code, data, and configs so others can actually run it.\n\nThe problem is the analog evaluation. Table 2 lists IDs 5 and 7 with identical node/edge counts, identical Cg and Reff statistics, and the same citation [19]; Appendix A.2 gives them the same description word for word. That is not a coincidence. And the training list in Appendix D.1 (“1–4, 6, 8–12, 15–18”) does not include ID 7, or IDs 13 and 19 for that matter. So either ID 7 is actually in training and the held-out ID 5 is a duplicate of something the models saw, or IDs 7, 13, and 19 are unused and the paper claims a 20-circuit benchmark while silently dropping three circuits. Either way the clean cross-design generalization claim on the analog subset is not supported as written.\n\nThe fix is straightforward: re-split, acknowledge the duplicate, and re-report the analog numbers. Until then the analog held-out tables should be read with suspicion. The SRAM part is a separate contribution and looks fine on its own, modulo the usual single-seed caveat (random seed 42 only, no repeated runs).\n\nI would not desk-reject this. The dataset is a real service to the EDA-ML community, and the issue is localized and fixable. But a referee should demand the corrected analog split and repeated runs before accepting the headline claims. My recommendation: send to review, with the expectation of major revision on the analog evaluation.","headline":"A genuinely useful RC benchmark for AMS parasitic prediction, but the analog held-out split looks contaminated by an apparent duplicate (IDs 5 and 7) and needs correction before the cross-design claims can be trusted.","tokens_in":25724,"tokens_out":1526,"would_cite":true,"duration_ms":15911,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"ParasGB is the first open benchmark that supplies graph-learning models with large-scale, physically grounded parasitic RC labels for analog and SRAM circuits.","keywords":["parasitic estimation","circuit graphs","benchmark suite","graph neural networks","analog/mixed-signal","SRAM","effective resistance","coupling capacitance"],"falsifier":"Compare the released netlists or graph files for analog circuit IDs 5 and 7; if they are identical (same node and edge counts, same Cg and Reff statistics, same layout files), the held-out test set is not truly unseen, and that would settle whether the claimed cross-design generalization for analog circuits holds.","tokens_in":24823,"feed_emoji":"⚡","tokens_out":5399,"duration_ms":52756,"temperature":0.7,"pith_summary":"ParasGB is a benchmark suite that supplies what parasitic-aware circuit learning has lacked: large-scale, physically grounded circuit graphs with ground-truth parasitic labels extracted by commercial EDA tools from real, tape-out-proven analog and SRAM designs. The paper's central claim is that this fills the gap left by earlier schematic-level analog benchmarks, which provide topology but no RC supervision. It defines node-level ground capacitance and edge-level effective resistance and coupling capacitance as learning tasks, in both regression and classification forms, with a unified evaluation protocol. The paper benchmarks common GNNs and circuit-specific models, and reports that parasitic labels are extremely imbalanced and long-tailed, making accurate prediction—especially of effective resistance on unseen analog topologies—genuinely hard. A sympathetic reader would care because a reliable public benchmark is the precondition for measurable progress on early-stage parasitic estimation, which in turn could cut costly layout iterations in deep-submicron AMS design.","feed_headline":"Open benchmark brings real chip parasitics to graph learning","feed_subtitle":"Tape-out-proven analog and SRAM circuits with commercial EDA labels give GNN researchers a standard testbed—and show the task is still hard.","key_machinery":"The central object is the benchmark suite itself: a conversion pipeline that reduces post-layout RC networks to lumped heterogeneous circuit graphs—device/net/pin nodes with topology edges as input, and ground capacitance (node), effective resistance (edge), and coupling capacitance (edge) as prediction targets. Effective resistance is computed efficiently by building the node admittance matrix and taking the inverse of its Cholesky factor, so port-to-port resistances can be queried without expensive path searches. A unified evaluation module standardizes metrics across models, making results comparable across methods.","core_discovery":"On its own terms, the paper establishes ParasGB as the first open-source benchmark for pre-layout parasitic parameter prediction on circuit graphs. The dataset is built from commercial EDA extraction on silicon-proven designs, converted into heterogeneous graphs with device, net, and pin nodes. The labels are lumped ground capacitance on net nodes, effective resistance on pin-to-pin edges computed via a Cholesky-factor-based method, and coupling capacitance on net-pair edges for SRAM. The benchmark provides a standardized API and train/validation/test splits, including held-out analog circuits and much larger unseen SRAM arrays. Across eight baseline models, the paper shows that current GNNs","pith_inferences":["Editorial inference: the benchmark's fixed five-bin classification boundaries give a consistent physical scale across designs, so the dataset could also serve as a testbed for ordinal regression and label-noise studies, not just standard classification.","Editorial inference: because the lumped-model labels abstract away detailed routing geometry, a natural follow-up is to quantify the gap between GNN predictions trained on ParasGB and full post-layout extraction; that gap would reveal the ceiling imposed by the lumped approximation itself.","Editorial inference: the cross-scale SRAM split (train on small digital/memory blocks, test on whole arrays) invites a study of how far inductive graph models can extrapolate in graph size and topology—a question that extends beyond EDA to graph learning generally.","Editorial inference: the authors stop at benchmarking; one could use ParasGB to train a single multi-task model that predicts all three parasitic targets jointly, testing whether shared representations across node- and edge-level tasks improve accuracy on the hard effective-resistance task."],"forward_implications":["GNN research on parasitic estimation can move from private, inconsistent datasets to a single public testbed where any proposed model can be compared on identical splits and metrics.","The held-out analog circuits and much larger unseen SRAM arrays make cross-design generalization a measurable property, not an assumption.","The documented extreme label imbalance and long-tail distributions imply that imbalance-aware losses and robust regression methods are core requirements for useful parasitic prediction, not optional extras.","The SRAM subset, with graphs up to tens of millions of nodes, gives graph learning researchers a concrete scalability challenge at industrial scale.","If pre-layout GNN predictions become reliable on this benchmark, front-end designers could act on estimated parasitics for sizing, buffering, and floorplanning decisions before layout, shortening design convergence."],"fun_headline_variants":["First open benchmark for pre-layout parasitic prediction","Real chip parasitics now a public graph benchmark for GNNs","ParasGB benchmark: real RC data from silicon-proven designs","Graph benchmark for parasitic estimation exposes GNN limits","Open RC benchmark from tape-out-proven circuits for GNN research"],"cache_read_input_tokens":2304,"weakest_assumption_plain":"The 20 analog circuits in Table 2 are 20 distinct physical designs, so the held-out test IDs 5, 14, and 20 were never seen during training; if two listed circuits are actually the same design, the claimed cross-design generalization results for analog tasks are invalid.","fun_headline_variants_meta":{"raw":{"variants":["First open benchmark for pre-layout parasitic prediction","Real chip parasitics now a public graph benchmark for GNNs","ParasGB benchmark: real RC data from silicon-proven designs","Graph benchmark for parasitic estimation exposes GNN limits","Open RC benchmark from tape-out-proven circuits for GNN research"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000196,"raw_usage":{"total_tokens":1204,"prompt_tokens":757,"completion_tokens":447,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":501,"completion_tokens_details":{"reasoning_tokens":364}},"tokens_in":501,"tokens_out":447,"duration_ms":4611,"temperature":1.0,"reasoning_tokens":364,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-01T00:00:35.142556+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Compare the released netlists or graph files for analog circuit IDs 5 and 7; if they are identical (same node and edge counts, same Cg and Reff statistics, same layout files), the held-out test set is not truly unseen, and that would settle whether the claimed cross-design generalization for analog circuits holds.","supporting_citations":[],"review_version":1}