{"id":"1fe25925-6a7e-4a9f-84c2-2f91afde8664","arxiv_id":"2607.23709","paper_version":1,"verdict":"CONDITIONAL","confidence":"HIGH","novelty_score":7.5,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"Elemental Ge is demonstrated as a CMOS-native phase-change memory with ≤240 ps crystallization, extrapolated >110 °C 10-year retention, and ~60% lower HRS drift than GST.","lead":"Elemental germanium works as a phase-change memory material in vertical W/Ge/W cells, with 240 ps crystallization, multi-day retention at 150 °C, and lower resistance drift than GST. If scalable, pure Ge would let PCM be built in ordinary CMOS fabs without Sb/Te contamination controls.","discovery_kind":"new_application","skeptic_critique":{"model":"moonshotai/kimi-k3","headline":"The >110 °C/10-year retention claim hangs on an Arrhenius extrapolation built from one temperature, one HRS device, no observed failure, and a literature Ea≈3 eV never measured in this device geometry — and the paper's own 4D-STEM data give a concrete reason the device-relevant Ea could be lower.","rationale":"The reader identified exactly this as the weakest assumption, and my independent pass lands in the same place, so I agree and see no reason to move the verdict off CONDITIONAL — the reader's conditions (multi-temperature retention before accepting the 'superior alternative' framing) are the right ones. I add two sharpenings beyond the reader's statement. First, the concern is not merely that Ea was imported; the paper's own structural evidence (residual crystalline fraction in the HRS, Fig. 3e) plus the W/Ge interfaces provide a specific physical mechanism by which the device-relevant Ea could be lower than the nucleation-limited thin-film literature value, making this a correctness risk rather than a generic extrapolation worry. Second, the single-temperature, single-device, no-failure anchor means the Arrhenius form itself is untested in this system; the τ0 back-solve (~10^-31 s, far from physical attempt frequencies) is a symptom that the construction is a parameterization, not a measurement. That said, I want to be fair about what survives even if this concern lands: the core materials demonstration — reversible melt-quench/recrystallization of elemental Ge in a vertical cell with direct STEM/4D-STEM confirmation, 240 ps instrument-limited SET, ν≈0.045 drift, and the CMOS-compatibility argument — does not depend on the retention extrapolation at all. The 150 °C bake is genuine evidence of stability exceeding GST under identical conditions. So the correct disposition is exactly what the reader gave: accept the demonstration, withhold the quantitative retention figure pending the multi-temperature measurement. Endurance (~5×10^3 cycles) and reset energy are real gaps too, but the authors disclose them plainly and they do not undercut the central claim the way the retention number does.","tokens_in":18197,"tokens_out":2405,"duration_ms":96827,"concrete_test":"Run isothermal retention bakes on multiple (≥5) HRS devices at four temperatures spanning the accessible range, e.g., 150/175/200/225 °C, until actual HRS failure (resistance drop defining t_fail) is observed at least at the two highest temperatures. Fit t_fail(T) to Eq. 1 to extract the device-relevant Ea and τ0 independently rather than back-solving τ0 from a non-failure. If the extracted device Ea comes out below ~2.6 eV, or if the Arrhenius fit shows curvature (growth-dominated regime), the >110 °C/10-year headline figure does not hold and must be revised downward; if Ea ≈ 3 eV is confirmed in the encapsulated W/Ge/W geometry, the retention claim is substantially de-risked. A complementary Kissinger analysis (multiple ramp rates) on the actual encapsulated device stack would cross-check the same quantity cheaply.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The retention leg of the strongest claim rests entirely on Methods §4.3: a single 10^5 s bake at 150 °C of one HRS device, no failure observed, then τ0 back-solved by setting t_fail = 10^5 s in Eq. 1 with Ea≈3 eV imported from 1970s-era resistance measurements on uncapped evaporated/sputtered Ge thin films (refs 42, 43). Three compounding weaknesses: (1) One temperature cannot constrain an Arrhenius temperature dependence — the extrapolation to 10 years spans ~3 orders of magnitude in time and is pure model assumption, not measurement. (2) The literature Ea values come from free-standing thin films whose crystallization is nucleation-limited; the actual device is an encapsulated W/Ge/W stack with SiNx, and the authors' own 4D-STEM (Fig. 3e) shows a residual crystalline fraction persisting in the HRS. A residual seed plus W/Ge interfaces shifts the device toward growth-dominated crystallization, which typically carries a lower effective activation energy than nucleation-limited thin-film values — precisely the direction that breaks the projection. (3) Sensitivity is real: with the same τ0 back-solving construction, Ea = 2 eV instead of 3 eV drops the 10-year temperature to roughly 95 °C, erasing the claimed margin over GST (~87 °C) and the 85 °C benchmark. The paper even notes Ea falls to ~1.4 eV above ~360 °C, underscoring that Ea is regime-dependent and must be measured, not imported. The 150 °C hold itself is real evidence of good stability, but the quantitative '>110 °C for 10 years' figure is the weakest-supported number in the headline. Note also n=1 HRS device for the retention anchor.","agreement_with_reader":"agree"},"referee_report":{"model":"moonshotai/kimi-k3","summary":"The manuscript introduces elemental germanium as a single-element, CMOS-compatible phase-change memory material, demonstrated in a vertical W/Ge/W cell (30/20/30 nm). The authors show threshold switching with snapback at ~2.2 V, a pristine HRS/LRS contrast exceeding four orders of magnitude, reversible unipolar switching over 1,500 cycles with a well-defined amorphization window, and instrument-limited crystallization in 240 ps. Phase change as the switching mechanism is supported by convergent structural evidence: cross-sectional STEM lattice fringes in the LRS versus a disordered HRS, 4D-STEM sharp spots versus diffuse rings, EDX showing no W–Ge interdiffusion (ruling out metallization-based switching), thin-film R–T crystallization near 490 °C corroborated by Raman and XRD, plus quantum-transport self-heating simulations showing Ge melting under RESET bias and melt-quench MD simulations showing the amorphous phase can be stabilized at device-relevant quench rates. The headline quantitative claims are 240 ps SET speed, a resistance drift coefficient ν≈0.045 (~60% below GST), and a projected 10-year retention temperature above 110 °C.","tokens_in":18514,"tokens_out":2579,"duration_ms":72583,"significance":"If the results hold, this is a genuinely significant contribution: the first demonstration of a CMOS-native elemental phase-change material, eliminating Sb/Te contamination concerns and elemental redistribution under cycling, and apparently breaking the speed–stability tradeoff that governs the Ge–Sb–Te system. The paper ships several notable strengths: (i) the phase-change mechanism is established by multiple independent structural probes rather than inferred from electrical data alone; (ii) the 240 ps figure is honestly reported as instrument-limited, with the true speed likely lower; (iii) the benchmarking in Fig. 4b/d/e is unusually careful about restricting comparisons to matched device sizes and measurement techniques; (iv) the MD melt-quench result is validated against two independent interatomic potentials (SW and GAP); and (v) limitations (endurance of ~5×10³ cycles versus 10⁶–10⁹ for optimized GST) are disclosed rather than buried. The principal risk attaches to one of the three headline numbers: the >110 °C/10-year retention projection.","major_comments":[{"comment":"The >110 °C/10-year retention figure rests on a single bake temperature (150 °C, the setup maximum), a single HRS device, no observed failure within 10^5 s, and a literature activation energy Ea≈3 eV imported from 1970s resistance measurements on uncapped evaporated/sputtered Ge thin films (refs 42, 43). τ0 is then back-solved by setting t_fail = 10^5 s in Eq. (1). One temperature cannot constrain an Arrhenius temperature dependence, so the ~3-decade extrapolation in time is entirely model assumption. The τ0 construction is conservative only conditional on Ea being correct: with the identical back-solving procedure, Ea = 2 eV instead of 3 eV lowers the 10-year temperature to roughly 95 °C, erasing the claimed margin over GST (~87 °C) and the 85 °C benchmark. The paper itself supplies two reasons to doubt that the thin-film nucleation-limited Ea transfers to this device: (a) the authors' ","section":null},{"comment":"Fig. 3e shows a residual crystalline spot persisting in the HRS diffraction pattern, and the MD protocol of §4.8/Fig. 3g explicitly models recrystallization proceeding by growth from a crystalline seed. A seeded, growth-dominated device crystallization process generically carries a lower effective activation energy than the nucleation-limited kinetics of the uncapped films from which Ea≈3 eV was taken — i.e., the error direction is the one that degrades retention. Further, the text (§2.4) notes Ea falls to ~1.4 eV above ~360 °C, demonstrating that Ge's crystallization energetics are regime- and geometry-dependent and must be measured, not imported. This is fixable within the manuscript's scope: either (i) measure the device-relevant Ea directly (accelerated bakes at two or more temperatures, e.g., 150/175/200 °C, on multiple HRS devices, or a Kissinger/Arrhenius analysis on the capped W/","section":null},{"comment":"Given that the abstract and conclusion both carry '>110 °C for 10 years' as a headline result, the retention claim should either be supported by a device-measured Ea with a stated uncertainty and sensitivity analysis, or the claim should be softened to what the data directly show: HRS stability at 150 °C over 10^5 s (itself a strong result that already exceeds GST, which fully crystallizes under these conditions) with the Arrhenius projection presented as conditional on the literature Ea. At minimum, report the implied 10-year temperature for a plausible Ea range (e.g., 2–3 eV) and state n (number of devices baked) in §4.3 — currently only one HRS and one LRS device are described.","section":null}],"minor_comments":[{"comment":"Fig. 2d: the cycled on/off ratio is ~100, versus the >4×10⁴ pristine contrast of Fig. 2b. A brief discussion of the origin of this contrast loss after the first SET (partial crystallization, filamentary volume, series resistance of the W/Ge contacts) would help readers judge multi-level prospects.","section":"§2.2"},{"comment":"Fig. 4c: drift is measured only at room temperature over 10³ s. Since GST's ν is known to increase strongly with temperature (Fig. 4d, refs 59, 60), at least one elevated-temperature drift measurement would strengthen the '~60% lower than GST' claim; otherwise note that the comparison is strictly valid at RT only.","section":"§2.4"},{"comment":"Fig. 4b mixes bottom-electrode diameter (mushroom cells) with the lateral Ge width (this work) as 'device size'. The justification given (both define the thermally active volume) is reasonable, but the equivalence is approximate; a caveat sentence would be appropriate, particularly since the record 242 ps Sb point is at 60 nm.","section":"§2.4, Fig. 4b"},{"comment":"The residual crystalline fraction in the HRS (Fig. 3e) should be quantified if possible (e.g., azimuthally integrated spot-to-ring intensity or crystallinity mapping from the 4D-STEM dataset), since it bears on both the retention mechanism and the MD seed model.","section":"§2.3, Fig. 3e"},{"comment":"Typographical: 'A WG' appears with a space throughout (§2.4, Methods §4.2). Fig. 2c reports n=5 devices per configuration; state this in the caption. The endurance data in Supplementary Fig. S4 (failure at up to 5,000 cycles, 10 devices) are important enough that the failure mode (stuck-LRS vs stuck-HRS) deserves one sentence in the main text.","section":"various"},{"comment":"Methods §4.7: the QT simulation uses a crystalline 20 nm Ge region at 3 V to show melting during RESET. Since the HRS that must be RESET is amorphous with much higher resistance, clarify why crystalline-Ge self-heating is the relevant configuration (presumably the post-threshold-switching state); a sentence on the assumed conduction state during the pulse would close this gap.","section":"§4.7, Fig. 3f"}],"recommendation":"major_revision","confidential_remarks":"The device physics, structural characterization, and benchmarking are solid and the writing is unusually candid about limitations (instrument-limited speed, modest endurance). My only load-bearing concern is the retention extrapolation in §4.3, which is the weakest link precisely because it supports one of the three abstract-level numbers. A multi-temperature bake or an honest reframing of the claim would resolve it; I do not see this as a reason to doubt the rest of the manuscript."},"author_rebuttal":null,"desk_editor":{"model":"grok-4.5","letter":"The real news is simple: pure Ge in a vertical W/Ge/W cell does reversible melt-quench PCM, with direct structural confirmation that LRS/HRS track crystalline/amorphous Ge. That corner of the triangle had been left alone for good historical reasons (covalent bonding, high Tm, Ge-rich GST trends). They showed it works.\n\nWhat they did well is multi-modal and not circular. Threshold snapback, a clean amorphization window, thin-film R–T near 490 °C plus Raman/XRD, cross-section STEM lattice fringes vs disorder, 4D-STEM spots vs diffuse rings, EDX with no W–Ge interdiffusion, plus QT self-heating past melting and MD melt-quench that can freeze amorphous Ge. Drift ν≈0.045 is a clean measurement and genuinely lower than typical GST. 240 ps SET is instrument-limited and size-independent in their range; they are careful enough to flag that. The CMOS-native argument is practical, not hype—no Sb/Te contamination segregation.\n\nSoft spots in proportion. Endurance tops out around a few thousand cycles and on/off collapses to ~100× under cycling; they own this and point to heater/confinement scaling. Reset energy is not yet competitive. The retention claim is the weakest number in the abstract: one 10^5 s bake at 150 °C on one HRS device, no failure, then τ0 back-solved with literature Ea≈3 eV from old uncapped films. Their own 4D-STEM shows residual crystallinity in the HRS, so device-relevant kinetics may be more growth-dominated and lower-Ea than the imported value. The 150 °C hold itself is real evidence of good stability; the quantitative >110 °C/10 yr figure is model, not measurement. Speed language that says “40× faster than GST” and “matches the record” should be read against the instrument floor and the larger device sizes.\n\nThis is for people who care about embedded NVM materials choices and monatomic PCM. The core demonstration deserves a serious referee. I would engage, cite the mechanism and drift results, and discount the extrapolated retention until multi-temperature data exist.","headline":"Working monatomic Ge PCM with solid STEM/4D-STEM mechanism proof and real CMOS-compatibility upside; the >110 °C/10-year number is the softest claim and should be read as a lower-bound projection, not a measured figure.","tokens_in":19637,"tokens_out":564,"would_cite":true,"duration_ms":10781,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"grok-4.5","headline":"Elemental germanium is a working CMOS-native phase-change memory that crystallizes in 240 ps, keeps data above 110 °C for a projected decade, and drifts less than GST.","keywords":["phase-change memory","elemental germanium","non-volatile memory","single-element PCM","CMOS compatibility","resistance drift","melt-quench crystallization"],"falsifier":"Measure the crystallization activation energy on the same W/Ge/W devices or films used for retention, then bake programmed high-resistance cells long enough to observe actual failure times at several temperatures; if the device Ea is substantially below ~3 eV, the projected >110 °C decade retention fails.","tokens_in":19182,"feed_emoji":"💾","tokens_out":994,"duration_ms":23033,"temperature":0.7,"pith_summary":"Standard phase-change memory relies on chalcogenide alloys such as GST. Those alloys segregate their atoms under cycling, drift in resistance, and bring Sb and Te that contaminate ordinary CMOS fabs. This paper shows that pure germanium, already used in mainstream semiconductor lines, can itself serve as the active phase-change layer in a simple vertical tungsten–germanium–tungsten cell. The cells crystallize in an instrument-limited 240 picoseconds, remain non-volatile with thermal stability projecting past 110 °C for ten years, and show a high-resistance drift coefficient about 60 percent lower than typical GST—while containing neither antimony nor tellurium. If the result holds under industrial scaling, phase-change memory can be built inside ordinary semiconductor facilities instead of dedicated chalcogenide fabs.","feed_headline":"Pure germanium stores bits in 240 picoseconds","feed_subtitle":"A standard semiconductor beats GST on speed, heat retention, drift, and fab compatibility","key_machinery":"A vertical self-heating W/Ge/W cell: a thin sputtered Ge film between tungsten electrodes is Joule-heated by unipolar pulses so that melt-quench amorphization and recrystallization switch resistance by orders of magnitude; STEM, 4D-STEM, quantum-transport heating maps, and melt-quench molecular dynamics confirm the phase-change mechanism.","core_discovery":"The authors establish that elemental germanium functions as a non-volatile phase-change material: short electrical pulses melt-quench a nanometric Ge volume into a stable amorphous high-resistance state and recrystallize it into a low-resistance state, with direct STEM and diffraction evidence that the two resistance states are crystalline and amorphous Ge. In their vertical self-heating W/Ge/W cells this yields sub-nanosecond crystallization (240 ps), projected 10-year retention above 110 °C, and a resistance-drift coefficient ν≈0.045, all without Sb or Te.","pith_inferences":["If explosive crystallization plus temperature-dependent Ea truly decouples high-T kinetics from low-T stability, other covalently bonded elemental semiconductors may be worth screening as PCM candidates.","CMOS-native Ge PCM could be co-integrated with Ge photodetectors or strained-Ge channels on the same wafer, collapsing optical, logic, and non-volatile memory process flows.","Because the active volume is monatomic, aggressive lateral scaling below stoichiometry-limited alloy cells may be limited mainly by thermal confinement rather than composition control.","Independent multi-temperature failure statistics on sub-50 nm Ge cells would be the decisive industrial gate for the retention and endurance claims."],"forward_implications":["Phase-change memory arrays could be fabricated inside standard CMOS lines without Sb/Te contamination controls or dedicated fabs.","Single-element Ge cells remove stoichiometry constraints and elemental segregation that limit cycling of multi-component alloys.","The combination of ≤240 ps write speed and high thermal stability opens high-temperature embedded and automotive non-volatile memory uses where GST is marginal.","A lower resistance-drift coefficient without doping or confinement improves analog multi-level and in-memory computing accuracy.","Adding a dedicated nanoheater and tighter thermal confinement is expected to raise endurance toward the 10^6–10^9 cycle range of optimized GST cells."],"fun_headline_variants":["Elemental Ge flips bits in 240 ps without Sb or Te","Pure germanium PCM: 240 ps set, 110 °C retention","CMOS-native Ge outpaces GST on speed and drift","Vertical Ge cells store data with 60% less resistance drift","Standard semiconductor Ge enables sub-ns phase-change memory"],"cache_read_input_tokens":128,"weakest_assumption_plain":"The claim of more than 110 °C ten-year retention rests on importing a literature crystallization activation energy of about 3 eV for germanium and back-solving an Arrhenius model from a single 150 °C bake in which no failure was seen.","fun_headline_variants_meta":{"raw":{"variants":["Elemental Ge flips bits in 240 ps without Sb or Te","Pure germanium PCM: 240 ps set, 110 °C retention","CMOS-native Ge outpaces GST on speed and drift","Vertical Ge cells store data with 60% less resistance drift","Standard semiconductor Ge enables sub-ns phase-change memory"]},"model":"grok-4.5","effort":"low","cost_usd":0.003665,"raw_usage":{"total_tokens":1256,"prompt_tokens":859,"num_sources_used":0,"completion_tokens":91,"cost_in_usd_ticks":36648000,"prompt_tokens_details":{"text_tokens":859,"audio_tokens":0,"image_tokens":0,"cached_tokens":256},"completion_tokens_details":{"audio_tokens":0,"reasoning_tokens":306,"accepted_prediction_tokens":0,"rejected_prediction_tokens":0}},"tokens_in":859,"tokens_out":91,"duration_ms":6353,"temperature":1.0,"reasoning_tokens":306,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-07-30T15:11:18.822787+00:00","model_set":{"reader":"grok-4.5"},"falsifier":"Measure the crystallization activation energy on the same W/Ge/W devices or films used for retention, then bake programmed high-resistance cells long enough to observe actual failure times at several temperatures; if the device Ea is substantially below ~3 eV, the projected >110 °C decade retention fails.","supporting_citations":[],"review_version":1}