{"id":"047ef738-e430-4cfd-a2ac-f97b02d1d155","arxiv_id":"2607.27204","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"Noisy modular interfaces tolerate ~10× higher error than local gates for lattice-surgery CNOTs, and distributed logical GHZ ancilla cost reduces to a spanning-tree vertex cover.","lead":"Circuit-level simulations show modular surface-code processors can run fault-tolerant nonlocal CNOTs even when inter-QPU links are roughly 20× noisier than local gates, with only a small threshold drop. The same work gives a graph-theoretic way to cut ancilla cost when building distributed logical GHZ states.","discovery_kind":"extension","skeptic_critique":{"model":"moonshotai/kimi-k3","headline":"The \"order-of-magnitude tolerance\" headline rests on a single hand-set operating point (α=20, with α_Bell≃10ε chosen arbitrarily), not on a measured sensitivity of the threshold to interface noise.","rationale":"The reader's weakest_assumption correctly identifies the load-bearing soft spot: the α≃20 interface model is a first-order fault count with an arbitrarily set Bell-pair contribution, no hardware-specific entanglement model, and no distillation/latency simulation. My stress test confirms this is the right target and sharpens it in one respect the reader did not emphasize: the claim is evaluated at a single α value, so the paper never measures threshold sensitivity to α — the \"order of magnitude\" language implies a robustness range that the data do not directly establish. This is a quantitative-conditioning issue, not an internal inconsistency: the simulations that were run appear competently executed (STIM/LOOM, PyMatching, 50k runs; the 2–3×10⁻³ gap is above binomial noise), and the graph-theoretic GHZ results (Theorem 1 via König, the DP in App. F, the edge-coloring depth argument) are elementary and sound. Nothing here rises to reject level: the paper's own wording (\"in the absence of a hardware-specific entanglement-generation model\") partially concedes the limitation, and the mechanism (small N_nl/N_l) is independently plausible. The reader's CONDITIONAL verdict with MODERATE confidence is calibrated; the α-sweep test would either firm up the headline or force a narrower statement, but the contribution stands either way. Hence UNCHANGED.","tokens_in":14302,"tokens_out":2211,"duration_ms":90241,"concrete_test":"Re-run the case-(a) single-interface CNOT simulation sweeping α ∈ {2, 5, 10, 20, 50, 100} at fixed code distances (e.g., d=3,5,7), same STIM/LOOM circuits and PyMatching decoder, and extract threshold vs α. If the threshold remains within ~3×10⁻³ of the monolithic value out to α≳50, the claim is robust as stated; if it degrades faster than linearly or the gap exceeds ~5×10⁻³ by α=50, the \"order-of-magnitude tolerance\" headline only holds for the stipulated α_Bell and must be conditioned on distillation achieving ~1% effective Bell infidelity. As a secondary check, recompute with a distillation-informed α_Bell (e.g., raw fidelity 0.90, one distillation round) to test whether α=20 is representative of any actual interconnect.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The strongest claim is that inter-QPU noise can be ~an order of magnitude above intra-QPU noise with only a 2–3×10⁻³ threshold reduction, explained by the small nonlocality ratio N_nl/N_l. The weak point is how this is established. Appendix C derives α = α_Bell + α_TeleGate ≃ 20ε from a first-order fault-location count, but the two pieces are asymmetric in justification: α_TeleGate≃10ε comes from an explicit 14-location count in the teleportation circuit (Supp. Fig. 3), while α_Bell≃10ε is, by the authors' own words, set \"in the absence of a hardware-specific entanglement-generation model.\" So the headline number is half-derived, half-stipulated. More importantly, the simulations compare only α=1 vs α=20. The derivative d(threshold)/dα is never measured, so the paper cannot distinguish \"threshold is insensitive to α over a wide range\" from \"α=20 happens to sit before a knee.\" This matters because raw photonic/interconnect Bell pairs routinely have infidelities of 5–10% against intra-QPU gate errors of ~10⁻³, i.e., effective α_Bell of 50–100 before distillation; distillation can recover this but adds latency and memory errors that the depolarizing-after-gates model (Eq. 1) does not include. If the threshold degrades superlinearly in α, the \"order of magnitude\" claim understates the interface requirement for real hardware. The N_nl/N_l argument (App. B) is a gate-count ratio and does not by itself bound how boundary-crossing syndrome errors propagate into logical failures, so it is supporting intuition rather than a guarantee.","agreement_with_reader":"agree"},"referee_report":null,"author_rebuttal":null,"desk_editor":{"model":"grok-4.5","letter":"The useful core is two things. First, they run actual circuit-level STIM/LOOM simulations of rotated-surface-code lattice-surgery CNOTs across noisy inter-QPU links (α=1 vs α=20) for three layouts, not just memory experiments, and the threshold only drops by ~2–3×10⁻³. Second, they cast distributed logical-GHZ ancilla placement under their fusion protocol as min spanning-tree vertex cover, prove the elementary tree identities, and give a polynomial Star-Search heuristic that beats BFS/DFS on ER graphs.\n\nThat is real incremental work. Prior distributed surface-code papers mostly stayed at memory or abstract resource counts; monolithic lattice surgery is already standard. The nonlocality-ratio bound in App. B is a clean explanation for why local noise dominates when N_nl/N_l stays small. The graph reduction is standard combinatorics applied correctly—not deep, but usable for architecture layout. Citations look appropriate; no circularity in the Monte Carlo thresholds.\n\nSoft spots, in proportion. Appendix C sets α_Bell≃10ε by fiat “in the absence of a hardware-specific model,” then only compares α=1 and α=20. So the “order-of-magnitude tolerance” line is an operating-point claim, not a measured d(threshold)/dα curve. Real photonic Bell pairs often sit at much higher effective α before distillation, and the depolarizing-after-gates model omits latency and correlated memory errors. That weakens the engineering headline without killing the simulation result under the stated noise model. No shipped code or data. The multi-CNOT and GHZ depth trade-offs are sketched rather than exhaustively optimized.\n\nWho it is for: people designing modular FT architectures who need quantitative interface budgets and ancilla/time trade-offs. Worth a serious referee. I would engage—cite the threshold comparison and the vertex-cover framing with the α caveat stated—and I would send it to peer review rather than desk-reject.","headline":"Solid systems-QEC paper: circuit-level distributed lattice-surgery CNOT thresholds hold up under a simple interface model, plus a clean vertex-cover reduction for GHZ ancillas; the α≃20 headline is only half-derived.","tokens_in":15699,"tokens_out":530,"would_cite":true,"duration_ms":17475,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"grok-4.5","headline":"Modular quantum processors can run fault-tolerant logical CNOTs across links an order of magnitude noisier than local gates, with only a small drop in the error threshold.","keywords":["modular quantum computing","rotated surface code","lattice surgery","fault-tolerant CNOT","noisy interconnects","distributed GHZ states","vertex cover","Bell pairs"],"falsifier":"Repeat the same circuit-level surface-code CNOT simulations (or a hardware experiment) with a realistic Bell-pair generation channel whose effective error is far above 20× local depolarizing noise or is strongly correlated; if the distributed–monolithic threshold gap then grows large or the threshold disappears, the resilience claim fails.","tokens_in":15498,"feed_emoji":"🔗","tokens_out":1003,"duration_ms":25541,"temperature":0.7,"pith_summary":"This paper asks whether fault-tolerant quantum computing still works when logical qubits live on separate modules linked by noisy entanglement, not on one monolithic chip. Using the rotated surface code and lattice surgery, the authors simulate nonlocal logical CNOT gates fed by imperfect Bell pairs and find that interface two-qubit noise can be roughly ten times worse than local noise while the fault-tolerance threshold falls only by a few parts in a thousand. The reason is architectural: only a small fraction of the two-qubit gates cross the interface, so local gate noise still dominates the logical error budget. Building on that CNOT primitive, they give a protocol for assembling distributed logical GHZ states across a network of modules, and show that minimizing the number of modules that need extra ancilla patches is equivalent to a vertex-cover problem on a spanning tree of the network. A simple greedy heuristic finds low-ancilla trees in polynomial time. Together the results argue that distributed error correction can scale modular hardware without demanding near-perfect interconnects.","feed_headline":"Noisy module links still allow fault-tolerant logical CNOTs","feed_subtitle":"Surface-code thresholds barely drop when inter-QPU noise is ten times local noise","key_machinery":"Nonlocal lattice-surgery CNOT mediated by noisy Bell pairs (interface noise parameter α), together with the nonlocality ratio N_nl/N_l that explains why local noise still sets the threshold; ancilla minimization cast as minimum vertex cover on a spanning tree, solved by a greedy Star-Search heuristic.","core_discovery":"Circuit-level simulations of lattice-surgery CNOTs between rotated surface-code patches on different QPUs show that raising the inter-QPU two-qubit error rate to about twenty times the local rate (α ≈ 20) lowers the fault-tolerance threshold by only about 2–3 × 10⁻³ relative to the fully local case. Threshold behavior is dominated by local gates because the nonlocality ratio stays small. The same nonlocal CNOT is then used to fuse local logical GHZ states into a global one, with ancilla placement reduced to a minimum vertex cover on a spanning tree of the QPU graph.","pith_inferences":["If the nonlocality-ratio argument generalizes, other lattice-surgery primitives (multi-target CNOTs, magic-state injection across modules) may inherit similar interface tolerance without new threshold analyses for every gate.","The vertex-cover framing suggests network topology itself becomes a first-class design knob: choosing QPU connectivity to admit low-cover spanning trees could cut physical ancilla overhead more than improving Bell-pair fidelity alone.","Latency and classical communication rounds from gate teleportation are left outside the noise model; including them could reintroduce a time–error trade-off that the static α model hides."],"forward_implications":["Modular surface-code architectures need not demand interconnect fidelity comparable to local gates to stay below threshold for logical CNOTs.","Logical multipartite entanglement (GHZ) across modules can be prepared with only n−1 nonlocal fusions and a minimized ancilla footprint given by a tree vertex cover.","Star-like network layouts minimize ancilla count at the cost of sequential fusion depth O(n); more branched trees trade ancillas for near-logarithmic depth.","Resource estimates and compilers for modular FTQC can treat noisy interfaces as a secondary error budget once the nonlocality ratio is kept small."],"fun_headline_variants":["Noisy inter-QPU links tolerate 20× local error for lattice-surgery CNOTs","Surface-code threshold drops only 0.002–0.003 with α≈20 interface noise","Modular FT CNOTs work when interface noise far exceeds intra-QPU noise","Vertex-cover heuristic cuts ancilla overhead for distributed logical GHZ states","Nonlocal lattice surgery keeps FT threshold nearly intact despite noisy Bell pairs"],"cache_read_input_tokens":128,"weakest_assumption_plain":"Interface noise is treated as a fixed depolarizing multiplier α ≈ 20 obtained by counting extra fault locations and assuming Bell-pair infidelity of order 10ε, without a hardware-specific entanglement model or correlated/biased errors.","fun_headline_variants_meta":{"raw":{"variants":["Noisy inter-QPU links tolerate 20× local error for lattice-surgery CNOTs","Surface-code threshold drops only 0.002–0.003 with α≈20 interface noise","Modular FT CNOTs work when interface noise far exceeds intra-QPU noise","Vertex-cover heuristic cuts ancilla overhead for distributed logical GHZ states","Nonlocal lattice surgery keeps FT threshold nearly intact despite noisy Bell pairs"]},"model":"grok-4.5","effort":"low","cost_usd":0.002604,"raw_usage":{"total_tokens":1017,"prompt_tokens":820,"num_sources_used":0,"completion_tokens":92,"cost_in_usd_ticks":26044000,"prompt_tokens_details":{"text_tokens":820,"audio_tokens":0,"image_tokens":0,"cached_tokens":128},"completion_tokens_details":{"audio_tokens":0,"reasoning_tokens":105,"accepted_prediction_tokens":0,"rejected_prediction_tokens":0}},"tokens_in":820,"tokens_out":92,"duration_ms":3795,"temperature":1.0,"reasoning_tokens":105,"cache_read_input_tokens":128,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-07-30T10:53:57.309689+00:00","model_set":{"reader":"grok-4.5"},"falsifier":"Repeat the same circuit-level surface-code CNOT simulations (or a hardware experiment) with a realistic Bell-pair generation channel whose effective error is far above 20× local depolarizing noise or is strongly correlated; if the distributed–monolithic threshold gap then grows large or the threshold disappears, the resilience claim fails.","supporting_citations":[],"review_version":2}