{"id":"7a185c28-a4a2-438f-ba49-35919a8a5780","arxiv_id":"2607.28795","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":8.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"Non-abelian \"mitten\" qLDPC codes achieve 20% encoding rate with distances 10-24 on 150-975 qubits, and simulations indicate fault-tolerant processors sustaining ~10^10 logical operations at 0.1% physical error rate.","lead":"This paper introduces \"mitten codes,\" a new family of quantum error-correcting codes that pack protected logical qubits densely into physical qubits (a 20% encoding rate) and support fast, parallel, hardware-friendly logical operations. If the simulated performance holds on real hardware, they could cut the qubit overhead of fault-tolerant quantum computers dramatically compared with the standard surface-code approach.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"No-idling noise model is load-bearing for the processor-capacity claims; omitted idle/transport errors on 5–24 ms neutral-atom SE cycles may dominate the reported 10^-11 and 10^-10 rates.","rationale":"The reader's weakest assumption — that the headline logical-error-rate and processing-capacity claims rest on a circuit-level model with no idling noise — is exactly the most load-bearing concern I find. The paper's structural core (mitten codes as non-abelian lifted product codes with canonical logical basis, the five-gadget surgery toolkit, the distance-preserving parallel magic injection) is supported by explicit constructions and proofs in the appendices, and those results are independent of the Monte Carlo estimates. The performance numbers, on the other hand, are explicitly tied to a noise model that omits any decoherence or loss during the 5–24 ms syndrome-extraction cycles on the very neutral-atom platform the paper highlights. Because the processor-capacity claim is the paper's headline and the omission is in the direction of making the target hardware look more capable than the simulations justify, this is a genuine limitation — but it is a limitation of extrapolation, not a flaw in the code construction or the simulation methodology as stated. The paper is transparent about the assumption, and the numerical simulations themselves are honest Monte Carlo outputs with confidence intervals. Therefore the reader's CONDITIONAL verdict is appropriate unchanged; my analysis neither upgrades to ACCEPT nor demands rejection. The proposed concrete test — rerunning the key surgery experiment with idle errors added at experimentally plausible rates — would settle whether this concern materially changes the quantitative claims, which is exactly what would be needed to move toward ACCEPT.","tokens_in":63298,"tokens_out":3521,"duration_ms":42456,"concrete_test":"Re-run the Fig. 2(b) surgery simulation for the [540,108,18] code at p=0.1% in Stim, inserting a single-qubit idle error on every data qubit after each SE round: use a depolarizing channel with p_idle = 1 − exp(−t/T2), with t = 11.74 ms (the 4-AOD cycle time from Table I) and T2 = 1 s (e.g., coherence times quoted in Ref. [92]); alternatively, use a phase-flip channel of the same rate. Also add a check-atom transport error per movement step according to the Appendix J schedule. If the logical error rate per quop increases by more than ~3× above the reported 1.33e-10, the 10^10-quop processor claim requires qualification; if it stays below ~1e-9, the omission is benign for this headline.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central quantitative claims — ~10^-11 per round at 0.1% PER and ~10^10 quops from 2 failures in 15 billion — are generated under a circuit-level depolarizing-noise model applied only to state preparation, two-qubit gates, and measurements, with no idling noise (Fig. 2 caption; Section V). For the neutral-atom target, Table I lists SE cycles of 5–24 ms (2-AOD) or 5–15 ms (4-AOD) during which data atoms are idle and ancilla atoms are transported. Even a conservative idle dephasing rate with T2 ~ 1 s gives a per-cycle dephasing error of ~1 − exp(−10 ms / 1 s) ≈ 1%, orders of magnitude above the 0.1% gate error used in the simulations; atom loss and AOD movement errors are also absent. The code-construction claims (rate 1/5, check weight 9, canonical basis, distance-preserving gadgets) do not depend on this omission, but the abstract's 'capable of running ~10^10 logical operations' and 'sub-millisecond latency sufficient for real-time decoding' are extrapolations to hardware whose error model differs materially from the simulated one. The paper is transparent about the no-idling assumption, which makes it a limitation rather than an internal inconsistency; still, it is load-bearing for the headline processor performance.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper introduces mitten codes, a family of qLDPC codes constructed as 1×2 lifted products over non-abelian group algebras, and argues that they satisfy four processor desiderata: 20% encoding rate, check weight 9, hardware-friendly layouts, and fast decoding. The central structural contributions are a canonical logical basis obtained from the group action (Theorem 4), distance upper bounds for lifted products (Theorem 8), explicit surgery and extractor gadgets, a distance-preserving parallel magic-state injection scheme (Theorem 7), and a proof that the codes have planar thickness three (Theorem 15). The paper also reports an end-to-end design pipeline built on sQetch, a GPU-based distance estimator, and Monte Carlo decoding results: a [300,60,14] code with block logical error rate ~10^-11 per round at 0.1% PER, and a [540,108,18] code with 2 logical failures in 15 billion surgery experiments, quoted as a ~10^10-quop processing capacity. The simulations use circuit-level depolarizing noise on state preparation, two-qubit gates, and measurements, with no idling noise.","tokens_in":63555,"tokens_out":6582,"duration_ms":79056,"significance":"If the structural and performance claims hold, this is a substantial step toward practical qLDPC processors: the 1/5 rate at block sizes of a few hundred qubits, the group-orbit logical basis, and the modular five-gadget Clifford toolkit are notable and well-motivated. The paper is commendably explicit: it provides concrete code instances, exact distances for the first five codes, open-source pipeline components, and Monte Carlo data with Clopper-Pearson intervals and an exact integer-programming decoding stage. However, the headline quantitative claims—10^-11 per round and ~10^10 quops—are obtained under a no-idling noise model and are therefore not directly transferable to the neutral-atom hardware the paper targets.","major_comments":[{"comment":"The processor-capacity claims are load-bearing and are generated with 'no idling noise' (Fig. 2 caption). For the neutral-atom implementation, Table I lists syndrome-extraction cycles of 5–24 ms, during which data qubits idle and ancillas are transported by AODs. Under even a conservative T2 ~ 1 s, idle dephasing alone contributes ~1 − exp(−10 ms/1 s) ≈ 1% error per cycle, an order of magnitude above the 0.1% PER used in the simulations; atom loss and movement errors are also omitted. Consequently, the abstract's 'capable of running ~10^10 logical operations' and the related quantitative claims are not estimates for the hardware discussed. The paper is transparent about this assumption, but the claims in the abstract and conclusion should be restricted to the no-idling model or supplemented with a hardware-realistic idle/transport noise model.","section":"Section V, Fig. 2 caption, Table I"},{"comment":"Distances of the three largest instances (J630,126,≤20K, J780,156,≤22K, J975,195,≤24K) are estimates from sQetch and BP+OSD, not exact values, and the syndrome-extraction schedules are described as 'likely preserve' or 'verified with sQetch' rather than proven to preserve circuit-level distance. The abstract's 'distance 18 and beyond' is exactly supported only up to the [540,108,18] code; the performance of the [975,195,≤24] code and of all memory/surgery experiments depends on estimated distances. Because sQetch is a heuristic estimator, the possibility of a lower actual distance or a schedule-induced distance collapse is not excluded. Please either provide exact certificates/proofs for the reported distances and schedule fault-tolerance, or clearly label all performance claims that depend on these estimates as conditional.","section":"Table I, Section V, Appendix H.5"},{"comment":"The claim of a '~10^10-quop processor' rests on two logical failures in 15 billion surgery experiments. The Clopper-Pearson interval reported by the authors (1.33^{+1.76}_{−0.86}×10^-10) already shows a factor-of-several uncertainty, and the statement that the code is 'capable' of 10^10 quops is a consistency extrapolation rather than a direct demonstration. The phrase 'without extrapolation' is used only for the memory rate, but the processing-capacity summary in the abstract and conclusion should distinguish between the measured two-failure result and the inferred capacity.","section":"Section V, Fig. 2(b)"}],"minor_comments":[{"comment":"The no-idling assumption should be restated wherever 'capable of running ~10^10 logical operations' appears, so that hardware-readiness claims are not separated from the noise model that produced them.","section":"Abstract and Conclusion"},{"comment":"The distance column mixes exact and estimated values. Consider adding a symbol or footnote that explicitly marks which entries are exact and which are upper-bound estimates from sQetch, and mirror this in the abstract's 'distance 18 and beyond' statement.","section":"Table I"},{"comment":"The notation '(1B X, 1B Z)' and 'R=13' is not self-explanatory. Define whether these are numbers of shots, number of rounds per shot, or total syndrome-extraction rounds, so the reader can reconstruct the reported logical-error-rate denominators.","section":"Fig. 2(b)"},{"comment":"The claims about sQetch being up to 800,000× faster are impressive but should be accompanied by a reproducible benchmark procedure, including hardware, dataset, and the exact version/commit of the repository referenced as [61].","section":"Appendix H"}],"recommendation":"major_revision","confidential_remarks":"This is a strong paper with a novel and promising code family and a high-quality simulation stack. The main risk is overclaiming hardware readiness: the headline logical-error and processing-capacity numbers are produced under a no-idling noise model, while the neutral-atom implementation the paper targets has millisecond-scale idle and transport times. The structural contributions (canonical basis, gadget constructions, distance theorems) appear sound and would survive a revision that narrows the performance claims or adds a realistic noise model. I recommend major revision, not rejection."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Bottom line: the mitten code construction is the real thing, and the paper deserves a serious referee. The headline error rates are honest simulation results, but they sit inside a noise model that omits idle and movement errors, which is a material caveat for the neutral-atom hardware the paper targets.\n\nWhat is actually new: mitten codes are a genuinely new family of non-abelian lifted product codes with 1×2 base matrices. For abelian G a codeword of A caps the distance at the base check weight; taking G non-abelian removes that cap, and the paper backs this with a canonical logical basis in a single group orbit (Theorem 4), classical-distance upper bounds, distance-preserving magic injection, and thickness-3 results. The five-gadget surgery toolkit, the parallel magic injection, and the telescoping decoder are substantial engineering contributions. The paper is also unusually transparent about method: distances of the first five codes are exact, the rest are marked with ≤ and estimated by sQetch; decoder simulations use Clopper-Pearson intervals, and the code and pipeline are open-sourced.\n\nThe main soft spot is exactly what the stress test flags. The circuit-level simulations apply depolarizing noise to state preparation, two-qubit gates, and measurement, with no idling noise. For the neutral-atom implementation, syndrome extraction cycles run 5–24 ms, during which data atoms sit idle and ancillas move. With T2 around a second, even 10 ms of idle gives roughly 1% dephasing per cycle, orders of magnitude above the 0.1% gate error used in the simulations. The paper states this limitation clearly in the figure caption, so it is not an internal inconsistency, but it is load-bearing for the “~10^10 logical operations” claim and for the memory error rates as hardware predictions. That claim is also slightly rounded up: the central value from 2 failures in 15 billion is about 7.5e9 quops, not 1e10. And “sub-millisecond latency” is an FPGA extrapolation, not a measurement.\n\nNone of this touches the code construction. The structural theorems and exact parameters up to distance 18 are independent of the noise model, and the evidence for them looks solid.\n\nWho should read this: anyone working on high-rate qLDPC codes or fault-tolerant architectures on neutral atoms and multilayer superconducting platforms. It deserves a proper peer review; a good referee should check the appendix proofs and push the authors to separate the code-construction claims from the hardware-readiness claims, ideally by labeling the no-idling assumption in the abstract and reporting the 7.5e9 central value honestly. I would send it out.","headline":"Mitten codes are a genuinely new construction with solid structural proofs; the processor-level error numbers are honest simulations under a no-idling-noise model that materially limits their meaning for neutral-atom hardware.","tokens_in":64204,"tokens_out":2510,"would_cite":true,"duration_ms":27879,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":["81P70","94B05"],"pacs":["03.67.Pp"],"model":"deepseek-v4-flash","headline":"This paper claims that mitten codes, a family of non-abelian lifted product codes, reach 20% encoding rate and distances 18–24 with only hundreds of qubits, and that with a fast decoder they can sustain about 10^10 logical operations under","keywords":["quantum error correction","qLDPC codes","lifted product codes","non-abelian groups","fault-tolerant quantum computation","code surgery","magic state injection","neutral atom quantum computing"],"falsifier":"Simulate or run the [300,60,14] and [540,108,18] codes with a noise model that adds idle decoherence, atom loss, and movement error at 0.1% per gate; if observed per-round logical error rates rise above roughly 10^-8 or processing capacity falls below 10^8 quops, the central capacity claim fails. Independently, compute the exact distance of the [975,195,<=24] code; if it turns out to be below about 18, the high-distance claim fails.","tokens_in":63038,"feed_emoji":"🧤","tokens_out":4678,"duration_ms":53412,"temperature":0.7,"pith_summary":"This paper introduces mitten codes, a family of quantum low-density parity-check (qLDPC) codes built from non-abelian groups. The non-abelian structure escapes a distance bound that caps abelian designs, so a 540-qubit code can have distance 18 and a 975-qubit code roughly distance 24, each at 20% encoding rate. The authors show how to turn these codes into a full fault-tolerant processor: five reusable surgery gadgets provide Clifford logic, high-rate gadgets measure many logical products at once, and magic states can be injected into all logical qubits in parallel. Using a staged decoder in circuit-level simulations, they report block logical error rates around 10^-11 per round at 0.1% physical error, and a processing capacity consistent with 10^10 logical operations. If correct, this would make practical fault-tolerant quantum computation feasible on near-term neutral-atom and superconducting hardware with a manageable qubit count.","feed_headline":"A new code family clears 10^10 logical operations","feed_subtitle":"Non-abelian lifted-product codes reach distance 18 at 20% encoding rate, promising practical fault-tolerant processors.","key_machinery":"The central object is the mitten code: a lifted product code LP(A,B) with 1x2 base matrices A=[a0 a1] and B=[b0 b1] over the group algebra F2[G] for a non-abelian group G, where L(a1) and R(b1) are full-rank. This full-rank 'square invertibility' condition is what forces a canonical logical basis with single-orbit group symmetry, letting one rewired seed gadget measure any logical operator. The parity-check matrices have a five-block 'mitten' shape that interleaves left and right regular representations. The telescoping decoder is a staged pipeline that uses belief propagation and Relay-BP on GPU to quickly decode easy shots, then sends a small residual of harder shots to an exact integer-pr","core_discovery":"The central claim is that taking the lifted product of two 1x2 classical matrices over the group algebra of a non-abelian group, with the left and right regular representations full-rank, yields codes with 20% encoding rate, check weight 9, and distances reaching 18 or more with only a few hundred physical qubits. The same full-rank condition produces a canonical logical basis in which every logical X and Z operator is a group-action image of one seed operator, so that the entire logical toolkit reduces to two seed surgery gadgets plus a few bridged gadgets. Under a uniform depolarizing circuit-level noise model, the [300,60,14] code attains about 10^-11 block logical error per round, and th","pith_inferences":["The paper's simulations exclude idle-time decoherence and atom-movement errors; adding those to the noise model is the most direct test of whether the claimed error rates survive on real neutral-atom hardware.","The single-orbit symmetry likely extends beyond the specific mitten instances found here, suggesting a broader design space for any lifted product code with a square-invertible base matrix over a non-abelian group.","A natural next step is to simulate a complete end-to-end circuit that includes magic-state distillation and consumption, measuring wall-clock throughput in addition to per-round logical error rate.","If the estimated distances of the larger instances are certified exactly, the same group-searching pipeline may yield distance-30-plus codes in under 1500 qubits with only modest changes to the group or base matrices."],"forward_implications":["A single [300,60,14] block would run roughly a billion logical operations between errors at 0.1% physical gate error, enough for many small fault-tolerant algorithms.","The 20% encoding rate means about five physical qubits per logical qubit, roughly an order of magnitude fewer than surface-code stacks of comparable distance.","Parallel magic-state injection into all logical qubits at once removes the usual magic-state bottleneck that dominates spacetime overhead in surface-code architectures.","The decoder's estimated sub-millisecond latency fits inside the 5–24 ms syndrome-extraction cycle of neutral-atom hardware, keeping open the route to real-time decoding.","The 540-qubit distance-18 code reaches a 10^10-quop regime, a scale relevant for algorithmic demonstrations rather than only memory benchmarks."],"fun_headline_variants":["Mitten codes: 20% rate, distance 18, 10^10 ops","Non-abelian qLDPC codes hit 10^10 logical operations","High-rate qLDPC processor runs 10 billion logical ops","New qLDPC code: 20% rate, distance 18, fast decode","Non-abelian codes reach distance 18 at 20% rate"],"cache_read_input_tokens":2304,"weakest_assumption_plain":"The headline processor-capacity numbers rest on a circuit-level noise model with depolarizing gate and measurement noise but no idling noise, while the three largest code distances are certified by estimates rather than proofs; if real hardware adds idle decoherence and atom loss during the 5–24 ms syndrome-extraction cycle, or if the estimated distances are off, the claimed 10^-11 per-round and 10^10-quop figures could degrade.","fun_headline_variants_meta":{"raw":{"variants":["Mitten codes: 20% rate, distance 18, 10^10 ops","Non-abelian qLDPC codes hit 10^10 logical operations","High-rate qLDPC processor runs 10 billion logical ops","New qLDPC code: 20% rate, distance 18, fast decode","Non-abelian codes reach distance 18 at 20% rate"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000517,"raw_usage":{"total_tokens":2438,"prompt_tokens":933,"completion_tokens":1505,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":677,"completion_tokens_details":{"reasoning_tokens":1414}},"tokens_in":677,"tokens_out":1505,"duration_ms":10206,"temperature":1.0,"reasoning_tokens":1414,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-03T00:22:48.328446+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Simulate or run the [300,60,14] and [540,108,18] codes with a noise model that adds idle decoherence, atom loss, and movement error at 0.1% per gate; if observed per-round logical error rates rise above roughly 10^-8 or processing capacity falls below 10^8 quops, the central capacity claim fails. Independently, compute the exact distance of the [975,195,<=24] code; if it turns out to be below about 18, the high-distance claim fails.","supporting_citations":[],"review_version":1}