{"id":"b472f869-f1c1-4b0f-a151-7676cfff7cf7","arxiv_id":"2608.00483","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"Running I-frames and feature-reset operations in FP32 while P-frames run in FP16 gives cross-GPU deterministic bitstreams with negligible compression-efficiency cost.","lead":"A neural video codec is made streamable across different GPUs by running reference frames in precise FP32 arithmetic while predictive frames stay in fast FP16. The paper maps where GPU models agree and disagree, reporting near-zero loss in compression efficiency and measuring latency over real networks including satellite links.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"FP32 anchor determinism is contradicted by the paper's own FP32 non-determinism finding; mixed precision synchronization lacks evidence.","rationale":"The reader's weakest assumption correctly identifies the FP32 determinism premise as the fragile foundation of the mixed precision mechanism. My analysis turns this into a sharper internal contradiction: Section II-A asserts bit-identical FP32 CUDA cores, but Section III-B reports that full FP32 mode is strictly non-deterministic across architectures and attributes this to kernel selection and reduction-order differences. The mixed precision anchors—I-frame and feature-adapter reset—are exactly FP32 operations that would be subject to the same kernel-selection variation. The paper offers no evidence that these specific operations are immune, and its own hypothesis for the 4K fractures (\"tensor shapes cross cuDNN heuristic thresholds and dispatch generation-specific kernels\") implies that FP32 is not a reliable synchronization anchor at all resolutions. If the anchors diverge, the decoder desynchronizes and the main contribution fails. The empirical results reported (e.g., intra-generation identical hashes at 1080p) might still hold, but without source code or kernel-level verification they cannot be checked; the paper's own concluding statement that \"source code remains under active development\" confirms the absence of artifacts. This concern is substantial, but the reader's CONDITIONAL verdict already accounts for it by requiring code and clarification. I therefore see no reason to move the verdict; it should remain CONDITIONAL pending the requested evidence.","tokens_in":16280,"tokens_out":5727,"duration_ms":58335,"concrete_test":"Encode the a07 River sequence at 1080p and 2160p in Mixed Precision on an RTX 3090 (Ampere) and on an RTX PRO 5000 (Blackwell). Record the SHA-256 hash of the first I-frame packet and of each feature-adapter reset packet (frames 30, 60, 90) from both encoders; then cross-decode (e.g., 3090-encoded bitstream on the PRO 5000) and check for decoder crashes or PSNR drops. If any I-frame or reset packet hash differs between the two GPUs, or if cross-decoding fails at a reset boundary, the FP32 anchors are not cross-architecture deterministic, falsifying the central claim. Additionally, dump the intermediate FP32 feature tensors immediately after the I-frame and after each reset on both GPUs and compare them bitwise; any bit difference proves the anchor is not bit-exact.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central mechanism requires that FP32 execution on CUDA cores is bit-identical across GPU architectures (Section II-A: \"General-purpose CUDA cores provide bit-identical, IEEE-754 compliant FP32 arithmetic, ensuring hardware-agnostic consistency\"). The paper's own Section III-B reports that full FP32 mode is \"strictly non-deterministic, with each GPU architecture generating a unique bitstream with a different SHA-256 hash,\" and hypothesizes that cuDNN kernel selection varies by generation/resolution, causing differing reduction orders even under IEEE-754 FP32. Since the mixed precision scheme forces I-frames and feature-adapter resets through the FP32 CUDA core path (Section II-D: \"bypassing the custom CUDA kernel and its tensor core dispatch\" and \"forcing the PyTorch-native FP32 execution path\"), the same kernel-selection variation would apply to these anchor operations. The paper provides no evidence that the specific operations in the I-net and the synthesis network used for resets select identical kernels across architectures. If those FP32 anchors are not bit-exact across GPUs, the decoder's probability tables desynchronize at the next P-frame, causing decoding failure. The claim of \"absolute consistency across all hardware architectures\" in Section II-D is thus unsupported and contradicted by the paper's own FP32 non-determinism result. Without code or kernel-level traces, the empirical hash matches reported for mixed precision cannot be independently verified.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes a streamable client-server neural video codec built on DCVC-RT that uses a Mixed Precision (FP16/FP32) strategy: P-frame coding runs on FP16 tensor cores for throughput, while I-frames and periodic feature-adapter resets are forced to the FP32 CUDA-core path. The authors claim this design eliminates intra-generation bitstream fragmentation, broadens cross-GPU inter-decodability, and preserves compression efficiency, with a negligible throughput penalty. They support this with experiments on 12 NVIDIA GPUs across four generations, including cross-encode/decode tests, coding throughput measurements, BD-Rate comparisons, and end-to-end latency results over Ethernet, Wi-Fi 6, 5G NR/LTE, and Starlink Direct-to-Cell.","tokens_in":16595,"tokens_out":6251,"duration_ms":69551,"significance":"If the central claim holds, the paper addresses a real and practical obstacle to deploying learned video codecs: floating-point nondeterminism across heterogeneous GPUs. The proposed approach is attractive because it avoids the large efficiency penalties of INT8 and the computational overhead of INT16, and it requires no fine-tuning of pretrained weights. The hardware evaluation is broad (12 GPUs, four generations, multiple resolutions) and the end-to-end network measurements, including a Starlink D2C deployment, add practical value. However, the paper's key mechanism rests on an assumption—FP32 CUDA-core bit-exactness—that the paper itself appears to contradict in Section III-B. The cross-decodability classifications also depend on an unspecified PSNR threshold. These issues are central and currently unresolved, so the significance of the work is contingent on additional evidence.","major_comments":[{"comment":"The central determinism mechanism rests on a premise that the paper itself contradicts. Section II-A asserts that 'General-purpose CUDA cores provide bit-identical, IEEE-754 compliant FP32 arithmetic, ensuring hardware-agnostic consistency.' Section III-B then reports that full FP32 mode is 'strictly non-deterministic, with each GPU architecture generating a unique bitstream with a different SHA-256 hash,' and hypothesizes that cuDNN kernel selection varies by generation/resolution, changing reduction order even under IEEE-754 FP32. Since the mixed-precision anchors (I-net and feature-adapter resets) execute through 'the PyTorch-native FP32 execution path' (Section II-D), the same kernel-selection variability could affect them. The paper provides no kernel-level traces, no intermediate-tensor comparisons, and no bitwise verification that the specific anchor operations are identical acros","section":"Section II-A, II-D, III-B"},{"comment":"The cross-decodability result depends on an unspecified PSNR threshold. Section III-F3 states that a result is classified as compatible if 'the PSNR-Y against the reference exceeds a threshold indicating proper reconstruction,' but the threshold value and selection procedure are never given. Since the compatibility groups in Table IV are the paper's main empirical evidence, a free threshold could materially change the reported outcomes (e.g., the 1080p FP32 cross-generation group vs. the 4K fracture). Specify the exact threshold, how it was chosen, and report the full per-pair PSNR table and bitstream hashes so the classifications are reproducible.","section":"Section III-F3 / Table IV"},{"comment":"The compression-efficiency claim is supported only by maximum BD-Rate deviations of +0.0162% (Mixed) and -0.0112% (FP32), with no per-sequence, per-GPU, per-QP, or per-resolution breakdown and no confidence intervals. These deviations are far below the 0.1% noise floor mentioned in the same section, so the reported maxima cannot be distinguished from measurement noise. If the intent is to show 'virtually identical' efficiency, report the full BD-Rate distribution, pairwise comparisons, and an equivalence test or at least confidence intervals. Otherwise the claim is under-supported.","section":"Section III-C"}],"minor_comments":[{"comment":"The phrase 'bit-identical, IEEE-754 compliant FP32 arithmetic' conflates IEEE-754 compliance with bit-exactness across implementations. IEEE-754 does not fix operation ordering, fused multiply-add behavior, or transcendental-function implementations; bit-identical results across GPU architectures are an empirical property, not a compliance guarantee. Recommend rephrasing.","section":"Section II-A"},{"comment":"The SHA-256 hash comparison is described in text, but no hash table or per-configuration hash values are shown. Including a table or supplementary data with the hashes would make the 'identical bitstream' claims directly verifiable.","section":"Section III-B"},{"comment":"The drift-bound illustration lacks details: no error bars, no specification of which GPU/sequence/QP produced the PSNR progression, and no description of how many frames were averaged. Please clarify the experimental conditions for this figure.","section":"Fig. 2"},{"comment":"The resolution range '1760×990 to 3520×1980' is introduced without methodological context. Describe how this resolution sweep was performed and whether it used the same a07 River content or additional sequences.","section":"Section III-B"},{"comment":"The paper states that source code remains under active development and that 'extensive validation is currently underway' before release. As written, this limits reproducibility. Add a data/code availability statement and, if possible, provide the exact packet format and precision-casting implementation details in a supplement.","section":"Section IV"},{"comment":"The Starlink D2C loaded latency has a 95th percentile above 5.5 seconds. The claim that the architecture 'successfully sustained the decoded stream' should be qualified by the decoder-side buffering assumptions and the actual playout buffer size; otherwise this statement is misleading.","section":"Section III-D"}],"recommendation":"major_revision","confidential_remarks":"The paper is within the scope of the journal and the practical motivation is strong. However, the central float-determinism mechanism is currently undercut by the paper's own finding that full FP32 mode is non-deterministic across architectures. The authors need to provide kernel-level or intermediate-bitwise evidence for the specific FP32 anchor operations, or substantially weaken the 'absolute consistency' claims. The unspecified cross-decodability threshold and the absence of per-sequence BD-Rate data are secondary but should be fixed in revision. No public code is provided, which is a further limitation for a systems-oriented paper."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Worth a read, but the central claim is not yet proven. The systematic cross-GPU evaluation is the real contribution. The authors turn DCVC-RT into a streaming client-server codec, add a mixed FP16/FP32 mode that runs I-frames and feature-adapter resets in FP32, and show empirically that this expands cross-decodability compared to full FP16. The throughput tables are thorough, and the latency data over Wi-Fi, 5G, and Starlink D2C is a useful engineering data point.\n\nThe problem is the foundation. Section II-A claims CUDA cores give bit-identical IEEE-754 FP32 arithmetic across GPUs. Section III-B reports that full FP32 encoding is \"strictly non-deterministic,\" with unique SHA-256 hashes per architecture, blamed on cuDNN kernel selection varying by generation and resolution. That contradicts the earlier claim. The paper tries to reconcile this by saying per-op rounding is fixed but reduction ordering varies; but the mixed-precision anchors are run through the same PyTorch FP32 path, and no kernel-level evidence shows those specific ops select identical kernels across architectures. The \"absolute consistency\" of the reset is asserted, not shown.\n\nThe cross-decodability classification is also under-specified. The PSNR threshold separating \"compatible\" from \"incompatible\" is never given. Table IV shows a bimodal spread (~26 dB vs ~13 dB), so a plausible threshold may exist, but without it the group boundaries are not reproducible. No code or data is released, making the hash-equality claims impossible to check. There are also table errors: the RTX 6000 Ada row in Table III shows FP32 throughput equal to FP16 at 1080p, which looks like a copy-paste mistake.\n\nNone of this kills the idea. The mixed-precision intuition is reasonable and the empirical compatibility maps are potentially valuable. But as it stands, the paper's own FP32 non-determinism result means the mechanism is unsupported. For peer review, I'd send it out—the data scope warrants referee time—but with a strong request for code, the threshold, and a direct reconciliation of the two FP32 statements.","headline":"A genuinely useful empirical map of cross-GPU bitstream compatibility for a learned video codec, but the mixed-precision fix rests on an FP32 determinism assumption that the paper's own results undermine.","tokens_in":17053,"tokens_out":5604,"would_cite":false,"duration_ms":64166,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"The paper claims that a mixed FP16/FP32 execution strategy—FP16 for P-frames, FP32 for I-frames and periodic feature resets—gives a neural video codec bit-exact cross-GPU synchronization with negligible compression loss.","keywords":["neural video compression","mixed precision","cross-platform determinism","bitstream interoperability","GPU architecture","streaming latency","learned video codec","FP16/FP32"],"falsifier":"Encode a 120-frame 1080p GOP with mixed precision on one GPU and decode on another GPU from the same generation but a different die; if the decoded PSNR-Y falls below the compatibility threshold or the decoder crashes, the anchor claim is refuted. Sharper still: run the identical FP32 I-frame and reset computation on two different dies and compare per-frame SHA-256 hashes of the entropy-coded payload; any mismatch shows the bit-identical FP32 assumption fails at the operation level.","tokens_in":16191,"feed_emoji":"🎥","tokens_out":8468,"duration_ms":78116,"temperature":0.7,"pith_summary":"The paper argues that the main obstacle to shipping neural video codecs in real streaming systems is not rate-distortion performance but floating-point non-determinism: the same model run on two GPUs can produce slightly different probability estimates, causing the arithmetic entropy coder to desynchronize and decoding to crash. To fix this without giving up hardware-accelerated FP16 throughput, the authors propose a mixed-precision operating point: P-frames run in FP16 on tensor cores, while I-frames and periodic feature-adapter resets are forced through IEEE-754-compliant FP32 execution on general-purpose CUDA cores. Across 12 GPUs from four architectural generations, this eliminates intra-generation bitstream fragmentation, makes bitstreams broadly inter-decodable, and costs only about 7% encoding and 4% decoding throughput, with BD-Rate deviations under 0.02%. The paper also packages the codec as a client-server TCP streaming system and measures end-to-end latency over Wi-Fi 6, 5G NR, and Starlink Direct-to-Cell, showing viability except for multi-second satellite beam-handover jitter.","feed_headline":"Mixed precision makes neural video codecs bit-exact across GPUs","feed_subtitle":"I-frames run in FP32, P-frames in FP16, giving deterministic GPU sync with under 0.02% compression loss.","key_machinery":"The load-bearing mechanism is the mixed-precision anchor: P-frame networks run in FP16 for throughput, while the I-frame network and the periodic feature-adapter reset run in FP32 on general-purpose CUDA cores, which the paper asserts are bit-identical IEEE-754 across GPU architectures. The reset, executed every 30 frames, re-derives a pixel-domain reference from the propagated feature and hard-clamps to [0,1]; running it in FP32 prevents the clamp from amplifying tensor-core least-significant-bit differences into coder-desynchronizing jumps. A companion change aligns encoder and decoder Decoded Picture Buffer state at reset boundaries, so split-process deployments take the same code path.","core_discovery":"The paper's central claim: cross-platform bitstream determinism in neural video codecs need not be bought with integer arithmetic. P-frame networks keep running in fast FP16 because feature drift is bounded by a periodic feature-adapter reset; the I-frame network and that reset are where bit-exactness matters, because they re-seed the reference state for all subsequent frames. Forcing the I-frame network and the reset synthesis through IEEE-754-compliant FP32 execution on general-purpose CUDA cores creates a deterministic anchor at every GOP/reset boundary. On 12 GPUs from four generations, this removes intra-generation bitstream fragmentation, enables cross-generation decoding at 1080p, and","pith_inferences":["The anchoring mechanism should transfer to any accelerator family that pairs a fast low-precision path with a slow but deterministic high-precision path; the paper's specific FP16/FP32 split on general-purpose cores is one instance of a general deterministic-reset-at-critical-state-boundaries recipe.","The 4K fracture under full FP32 suggests the true determinism boundary is kernel selection, not arithmetic precision; if kernel-level tracing confirms this, pinning the deep-learning library's algorithm choices could restore 4K interop at much lower cost than a full FP32 pipeline.","A direct testable extension: measure whether the same mixed-precision anchor works at 4K on two same-generation, different-die GPUs; the paper's claims predict success, while its own kernel-selection hypothesis warns that FP32 kernel dispatch at larger tensor shapes could break bit-exactness.","The TDD/FDD loaded-latency inversion implies that for learned codecs, network scheduling matters more than raw link latency; adaptive bitrate controllers should be tuned on loaded round-trip time instead of ping, which the paper's measurements support but do not implement."],"forward_implications":["Neural video codecs can be deployed in heterogeneous client-server pairs—high-end encoder GPU, lower-tier decoder GPU—without integer quantization, preserving hardware FP16 acceleration.","Intra-generation bitstream fragmentation disappears: all die variants of a GPU generation encode and decode identical SHA-256-verified bitstreams in mixed precision, removing a whole class of device-compatibility bugs.","Cross-generation decodability becomes practical at 1080p across recent architectures; at 4K, full FP32 decoding still fractures into three compatibility groups (Turing / Ampere-Ada / Blackwell), so full interop at 4K remains open.","The compression-efficiency cost of determinism is effectively zero (<0.02% BD-Rate), so the only real price is a modest, bounded throughput penalty (~7% encode, ~4% decode) and the power-envelope sensitivity that comes with FP32.","End-to-end streaming over terrestrial links is viable (≈40–70 ms loaded round-trip time); satellite direct-to-cell links work but expose 3–6 s beam-handover bufferbloat, which calls for rate-adaptive, error-resilient codec design."],"supporting_citations":[{"why":"Supplies the base real-time neural video codec whose weights, arithmetic coder, and feature-adapter reset the paper reuses and wraps into a streaming format.","marker":"[4]"},{"why":"Frames floating-point non-determinism as a reproducibility problem in learned compression, motivating the need for a synchronization mechanism.","marker":"[11]"},{"why":"Prior calibration-based cross-platform codec approach; the paper positions its precision-based solution against this line of work.","marker":"[12]"},{"why":"Prior quantized-decoder method for deterministic reconstruction, one of the integer-based alternatives the paper argues against.","marker":"[13]"},{"why":"Prior codebook-based cross-platform video codec, an alternative deterministic approach contrasted with mixed precision.","marker":"[14]"},{"why":"Reports integer-centric neural video compression variants whose INT8/INT16 trade-offs the paper positions against its FP16/FP32 design.","marker":"[15]"},{"why":"Documents the large INT8 BD-Rate penalty on a mobile-scale codec, supporting the claim that integer quantization is too costly.","marker":"[16]"},{"why":"Defines the BD-Rate metric used to show that mixed precision changes compression efficiency by less than 0.02%.","marker":"[24]"}],"fun_headline_variants":["FP16/FP32 split yields bit-exact neural video on any GPU","I-frames FP32, P-frames FP16: exact sync, tiny loss","Mixed precision anchors neural codec determinism across GPUs","Bit-exact neural video: FP32 anchors, FP16 speed, no crash","Cross-GPU sync for neural codecs via mixed precision (≤0.02% loss)"],"cache_read_input_tokens":2688,"weakest_assumption_plain":"The whole mechanism rests on the premise that FP32 arithmetic on general-purpose CUDA cores is bit-identical across GPU die variants and architectures, so an FP32 I-frame and reset can act as a deterministic sync point; the paper itself reports that full FP32 mode is not bit-deterministic across architectures at 4K due to kernel selection, making this per-operation determinism the fragile load-bearing assumption.","fun_headline_variants_meta":{"raw":{"variants":["FP16/FP32 split yields bit-exact neural video on any GPU","I-frames FP32, P-frames FP16: exact sync, tiny loss","Mixed precision anchors neural codec determinism across GPUs","Bit-exact neural video: FP32 anchors, FP16 speed, no crash","Cross-GPU sync for neural codecs via mixed precision (≤0.02% loss)"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000172,"raw_usage":{"total_tokens":1155,"prompt_tokens":832,"completion_tokens":323,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":576,"completion_tokens_details":{"reasoning_tokens":220}},"tokens_in":576,"tokens_out":323,"duration_ms":4327,"temperature":1.0,"reasoning_tokens":220,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-05T00:51:13.729434+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Encode a 120-frame 1080p GOP with mixed precision on one GPU and decode on another GPU from the same generation but a different die; if the decoded PSNR-Y falls below the compatibility threshold or the decoder crashes, the anchor claim is refuted. Sharper still: run the identical FP32 I-frame and reset computation on two different dies and compare per-frame SHA-256 hashes of the entropy-coded payload; any mismatch shows the bit-identical FP32 assumption fails at the operation level.","supporting_citations":[{"cited_title":"Towards practical real-time neural video compres- sion,","cited_arxiv_id":null,"evidence_quote":"Supplies the base real-time neural video codec whose weights, arithmetic coder, and feature-adapter reset the paper reuses and wraps into a streaming format."},{"cited_title":"Towards reproducible learning-based com- pression,","cited_arxiv_id":null,"evidence_quote":"Frames floating-point non-determinism as a reproducibility problem in learned compression, motivating the need for a synchronization mechanism."},{"cited_title":"Quantized decoder in learned im- age compression for deterministic reconstruction,","cited_arxiv_id":null,"evidence_quote":"Prior quantized-decoder method for deterministic reconstruction, one of the integer-based alternatives the paper argues against."},{"cited_title":"Effortless Cross-Platform Video Codec: A Codebook-Based Method","cited_arxiv_id":"2310.10292","evidence_quote":"Prior codebook-based cross-platform video codec, an alternative deterministic approach contrasted with mixed precision."},{"cited_title":"Integer-centric neural video compression,","cited_arxiv_id":null,"evidence_quote":"Reports integer-centric neural video compression variants whose INT8/INT16 trade-offs the paper positions against its FP16/FP32 design."},{"cited_title":"Mobilenvc: Real-time 1080p neural video compression on a mobile device,","cited_arxiv_id":null,"evidence_quote":"Documents the large INT8 BD-Rate penalty on a mobile-scale codec, supporting the claim that integer quantization is too costly."},{"cited_title":"Bjøntegaard delta (bd): A tutorial overview of the metric, evolution, challenges, and recommendations,","cited_arxiv_id":null,"evidence_quote":"Defines the BD-Rate metric used to show that mixed precision changes compression efficiency by less than 0.02%."}],"review_version":1}