{"id":"4bfac103-0b91-4fce-9bdb-182732c0ea5a","arxiv_id":"2608.00734","paper_version":1,"verdict":"CONDITIONAL","confidence":"HIGH","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":4,"one_line_summary":"A distributed Ethernet-based readout with continuous up-the-ramp streaming could cover WST's ~750 detectors within about 30 kW and 100 GbE aggregate links.","lead":"This paper outlines a distributed detector-control system for the proposed Wide-field Spectroscopic Telescope, using one small Ethernet module per detector plus rack-mounted aggregators. It matters because it quantifies how a 750-detector instrument can handle data, power, and timing over a single cable per detector.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The white-noise UTR assumption is load-bearing; realistic correlated noise could push required sampling cadence past the 1 fps / 2.5-10 GbE envelope, so the paper's planned Pyxel assessment is the deciding check.","rationale":"The paper is a conceptual architecture study, and its central quantitative claim is that a distributed detector module plus xTCA aggregator design can handle ~750 detectors at the stated cadence, bandwidth, and power envelope. The reader's weakest-assumption call is correct: the Garnett & Forrest white-noise formula is the single point on which all sizing depends, and the authors themselves flag it as optimistic and not sufficient to close requirements. I agree with the reader's conditional verdict: the architecture is internally consistent, the limitations are explicit, and the planned Pyxel/laboratory characterization is a genuine path to closure. I considered other possible concerns—the 12k link is spec'd at 10 GbE when Table 2 gives only 2.4 Gbit/s, and the 12k power budget of 45 W is below the PoE Type 3 limit while Type 4 is chosen—but these are conservative over-specifications or minor inconsistencies, not threats to the central claim. The white-noise dependency, by contrast, directly controls whether the nominal envelope is feasible. Because the paper is explicitly conditional on the follow-up detector assessment, no change to the reader's verdict is warranted.","tokens_in":5597,"tokens_out":5690,"duration_ms":74447,"concrete_test":"Run Pyxel end-to-end simulations using measured noise power spectra of candidate cooled CMOS sensors (including 1/f knee, correlated row/common-mode noise, dark-current shot noise, and image lag) over 900 s ramps. Fit the synthetic ramps with the same O(1) running-sum algorithm used in Section 5.2 and extract effective read noise as a function of M. Determine the Mmin needed for <1 e- and compare it with the 1 fps ceiling (M=900). If Mmin > 900, or if no M reaches <1 e-, the stated link speeds (2.5/10 GbE), PoE classes, and aggregator counts are underestimated in the nominal scenarios, and the paper's conditional claim would need revision.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper sizes the entire infrastructure—M, cadence, per-detector bandwidth, Ethernet link class, PoE class, and aggregator throughput/count—from the Garnett & Forrest white-noise scaling, sigma(Q) ~ sigma_read*sqrt(12/M). The paper itself explicitly labels this 'deliberately optimistic' (Section 2, after Table 1, and in the Conclusions) and lists the breaking mechanisms: 1/f and low-frequency noise, correlated row/common-mode noise, dark-current shot noise, and image lag. This is load-bearing because all downstream numbers are monotone functions of M. If a real CMOS sensor's correlated noise floor prevents the effective read noise from reaching <1 e- at M=900 (the 1 fps ceiling), then the nominal 6k/12k scenarios cannot be supported on the stated Cat6A+PoE+2.5/10 GbE links. The concern is not an internal inconsistency; the arithmetic is correct and the limitations are honestly disclosed. It is an unresolved dependency: the architecture's feasibility envelope is conditional on a noise model that is known to be optimistic. The paper defers to a Pyxel end-to-end simulation, which is the right next step but is not yet performed.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents a conceptual, distributed detector-controller architecture for the Wide-field Spectroscopic Telescope (WST), in which each detector is served by a minimal warm proximity module and groups of modules are aggregated by xTCA-based edge nodes. The same Cat6A Ethernet cable carries packetized data, PTP timing, and PoE power. The infrastructure is sized from the Garnett & Forrest up-the-ramp (UTR) read-noise formula: for a 15-minute sub-exposure and a target integrated read noise below 1 e-, the required number of non-destructive reads M and hence the raw per-detector bandwidth, link rate, PoE class, aggregator count, and edge-compute throughput are derived for 6k and 12k detector scenarios. The paper explicitly labels the white-noise assumption as deliberately optimistic, lists the mechanisms that break it, and defers a quantitative noise assessment to planned Pyxel simulations.","tokens_in":5911,"tokens_out":3222,"duration_ms":42252,"significance":"If the assumed noise envelope holds, the paper provides a credible and internally consistent first-order architecture for a detector infrastructure at an unprecedented scale. Its strengths are the transparent use of an external published noise formula, explicit order-of-magnitude budgets, the integration of power, timing, and data on one cable, and a clear separation between transport and processing layers. The paper also connects the design to the facility's sustainability goals and to available standards (IEEE 802.3bt, PTPv2, xTCA). The contribution is conceptual rather than final, and the authors are honest about the conditional nature of the numbers; nevertheless, the central feasibility envelope is monotone in the UTR sampling requirement, so the white-noise assumption is a load-bearing dependency that needs more quantitative treatment before the architecture can be considered closed.","major_comments":[{"comment":"The entire sizing (M, cadence, per-detector bandwidth, link class, PoE class, aggregator throughput) scales with the Garnett & Forrest white-noise formula. The paper itself acknowledges that real CMOS noise (1/f, correlated row/common-mode, dark current, image lag) breaks this scaling, but it provides no sensitivity analysis. Since the 1 fps ceiling and the 2.5/10 GbE choices are monotone in M, a correlated-noise floor that raises the required M from, say, 298 to above 900 would move the nominal 5 e- scenario outside the stated envelope. The planned Pyxel study is the right next step, but the present paper should either present the architecture as explicitly conditional on a specified maximum M, or include a parametric sensitivity table showing how Mmin and the required cadence vary with a noise-floor parameter. This is not a request for new simulations, but for making the dependency exp","section":"Section 2, Eq. (1) and Table 1"},{"comment":"The PoE Type 3/Type 4 assignment rests on the per-module power budgets of 20 W and 45 W, described only as concept-stage allocations. No margin for cable resistance, connector losses, or PSE-to-PD efficiency is discussed, and no reference is made to the maximum powered cable length under IEEE 802.3bt at Cat6A with data transmission. Since PoE class selection is a stated outcome of the paper, the power budget should at least include a standard derating or a clear statement that the quoted budgets are PD-side values and that the PSE budgets include loss. Without this, the reader cannot verify that the two classes indeed bracket the scenarios.","section":"Section 4, power budgets and PoE class"},{"comment":"The claim that buffering each frame in DDR-SDRAM and spreading transmission over the inter-read interval 'removes congestion by construction' presupposes that the buffer is large enough to hold a full frame at the highest format (for a 12k detector, of order 288 MB at 16-bit). The proximity module is described as 'minimal' but no DDR capacity is given. A short sentence quantifying the required buffer per format and confirming that the module's DDR-DRAM meets it would close this gap; otherwise the continuous-streaming guarantee is not established for the 12k tier.","section":"Section 5.1, continuous streaming claim"}],"minor_comments":[{"comment":"Two different figures are both numbered 'Figure 1': the cadence plot in Section 2 and the architecture diagram in Section 3. Renumber the second figure and update all references.","section":"Figures"},{"comment":"The sentence 'the link approaches saturation at the upper end of the operating range' is imprecise: Table 2 gives 800 Mbit/s on a 1 GbE link for the 12k, 5 e- nominal case, which is 80% utilization, not saturation. Reword to 'reaches about 80% utilization without margin'.","section":"Section 2, text near Table 2"},{"comment":"Typo: 'approximately 2 height-unit 19” device unit per detector' should read 'approximately one 2 height-unit 19\" device unit per detector'.","section":"Section 3, first paragraph"},{"comment":"The arithmetic intensity is stated as '~10 FLOP/byte' but the two components are 4 and 6 FLOP/byte, giving a sum of 10. Consider clarifying that the kernels are not mutually exclusive or that the 10 is a combined figure, to avoid confusion.","section":"Section 5.2, FLOP/byte discussion"}],"recommendation":"major_revision","confidential_remarks":"The paper is a well-written conceptual architecture study with honest caveats. The main reason for major revision, rather than acceptance, is that the load-bearing white-noise assumption is acknowledged but not quantified; the planned Pyxel work is mentioned but does not yet appear in the paper. I would ask the authors to either add a sensitivity analysis or explicitly restate the architecture's conclusions as conditional on the UTR sampling ceiling. The duplicate figure numbering and the PoE margin question are easily fixed. The paper is within scope for an instrumentation journal and does not suffer from internal inconsistency."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The one thing you need to know: this is a solid, honestly-scoped conceptual design paper, but the whole sizing exercise hinges on an assumption the authors themselves call optimistic. If real CMOS 1/f noise breaks the √(12/M) scaling, all the link speeds, PoE classes, and aggregator counts shift. The paper says this plainly and defers to a planned Pyxel simulation, so treat it as a conditional architecture study, not a closed feasibility proof.\n\nWhat is actually new: the WST-specific sizing itself — the M values, cadence, per-detector bandwidth, PoE classes, and aggregator counts derived from the Garnett & Forrest formula and the stated envelope. The arithmetic checks out; I re-derived the Mmin values in Table 1 and they match. The bandwidth and power tables are internally consistent. The continuous UTR streaming idea to remove simultaneous-readout bursts is well-motivated and the single-cable data/timing/power concept is clean. The paper is also unusually clear about what is a concept-stage estimate versus a firm requirement. That honesty is real and earns credit.\n\nThe soft spot is load-bearing: the entire infrastructure is sized on the white-noise UTR model. The paper itself lists the breaking mechanisms — 1/f and low-frequency noise, correlated row/common-mode noise, dark-current shot noise, image lag — and notes that real CMOS will not behave this way. If correlated noise keeps the effective read noise above 1 e− at M=900 (the 1 fps ceiling), then the 6k and 12k scenarios cannot be supported on the stated Cat6A+PoE+2.5/10 GbE links. The paper knows this and defers to Pyxel, which is the right next step. That makes the architecture conditional, not wrong. It's an unresolved dependency, and it's out in the open. For a conceptual design paper at this stage, that's acceptable, but readers should not think the envelopes are settled. Minor production issues: duplicate Figure 1 captions and a repeated paragraph in Section 5.2; these don't affect content.\n\nWho this is for: the WST consortium, detector-controller engineers, and anyone planning readout for a facility with hundreds of detectors. It's not a fundamental science advance, but it is a carefully quantified engineering reference with a clear critical path. I'd send it to peer review for an instrumentation venue. The conditional caveat is explicit, and the appropriate ask is to require the Pyxel results in revision so the sizing can be re-benchmarked against realistic correlated noise. That would turn a conditional architecture into one you can actually plan against.","headline":"A well-scoped, internally consistent concept paper for WST detector readout; the feasibility envelope rests on an explicitly optimistic white-noise model, so treat the numeric sizing as conditionally valid until the Pyxel assessment lands.","tokens_in":6399,"tokens_out":2736,"would_cite":false,"duration_ms":33025,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper argues that the Wide-field Spectroscopic Telescope's ~750 detectors can be operated through a two-level distributed readout, with a single Cat6A cable per detector carrying data, timing, and power.","keywords":["WST","detector infrastructure","distributed detector controller","up-the-ramp readout","CMOS detectors","Power over Ethernet","read noise","spectroscopic telescope instrumentation"],"falsifier":"Take a representative scientific CMOS sensor and measure its noise power spectrum over a 900 s up-the-ramp sequence. If the fitted-slope variance stops decreasing according to sqrt(12/M) once M exceeds the ramp duration divided by the 1/f corner time, the Table 1 Mmin values are too low; recomputing cadence and bandwidth with the measured correlated noise would settle whether the 1 fps ceiling, 2.5/10 GbE choices, and PoE classes still hold.","tokens_in":5536,"feed_emoji":"🔭","tokens_out":12194,"duration_ms":129041,"temperature":0.7,"pith_summary":"This paper is a conceptual sizing study for the detector control system of the proposed 12 m Wide-field Spectroscopic Telescope (WST), which would need on the order of 750 detectors across three instruments. At that scale, a centralized controller per detector becomes impractical, so the authors argue for a distributed two-level readout: a minimal warm electronics module placed at each detector, and networked aggregator shelves per instrument. A single Cat6A cable per detector carries the pixel stream, the timing signal, and electrical power, with Power-over-Ethernet Type 3 for 6k detectors and Type 4 for 12k detectors. The sizing—number of non-destructive up-the-ramp samples, frame cadence, raw bandwidth, compute load, and power—is derived from the multiply-sampled read-noise formula, and the target 3–5 e⁻ CMOS regime fits comfortably under a 1 frame/s ceiling with a 1 GbE link (6k) or 2.5 GbE (12k). The authors state clearly that this envelope is deliberately optimistic because real CMOS noise has 1/f and correlated components that do not average down as sqrt(12/M), so the figures are lower bounds to be consolidated by a planned end-to-end detector simulation.","feed_headline":"One cable can power and read out WST's ~750 detectors","feed_subtitle":"Warm per-detector modules and PoE links keep data, timing and power on one cable; 12k can wait.","key_machinery":"The two-level distributed architecture: (1) a minimal warm proximity module per detector that serializes, timestamps, buffers, and packetizes the pixel stream onto one Ethernet link, and (2) an xTCA aggregator shelf per instrument that terminates up to 32 links and performs the first reduction. The sizing machinery is the multiply-sampled read-noise relation sigma(Q) ≈ sigma_read sqrt(12/M), which fixes the minimum number of up-the-ramp samples M and therefore the required cadence, bandwidth, and link/power classes. The continuous-streaming mechanism—each buffered frame spread over the whole inter-read interval instead of being burst out—is what removes switch congestion, makes transport los","core_discovery":"The central claim is that WST's detector system, roughly 750 detectors, exceeds the practical limit of a centralized controller requiring one 2U unit per detector, and can instead be served by two levels: a minimal warm proximity module per detector that digitizes, timestamps, buffers, and packetizes pixels, and networked xTCA aggregator shelves per instrument that terminate up to 32 links and run the first reduction. The paper derives the envelope from the multiply-sampled up-the-ramp formula sigma(Q) ≈ sigma_read sqrt(12/M): to reach an effective read noise below 1 e⁻ in a 15-minute sub-exposure, a 3 e⁻ single-read sensor needs about 106 samples (0.12 fps), 5 e⁻ needs 298 (0.33 fps), 10 e⁻","pith_inferences":["Beyond the paper: the clean separation between proximity module and aggregator suggests the cable plant and shelves could outlive the first sensor generation—swapping only the detector module would adapt the same infrastructure to a different CMOS device within the link-rate and PoE-class constraints.","Beyond the paper: a direct test of the white-noise caveat would be to measure a sensor's fitted-slope variance as a function of M; once the ramp exceeds the 1/f corner time, the variance stops following sqrt(12/M), and the remaining link margin determines how much of the proposed 5× headroom is real.","Beyond the paper: the per-instrument partitioning means spare aggregator capacity cannot be pooled facility-wide, so an instrument whose noise forces higher cadence would need its own oversized processing rather than borrowing from a quieter instrument.","Beyond the paper: the same single-cable, PoE-fed, warm-module pattern could generalize to other multi-detector survey instruments, making the architecture a reusable template for detector-fleet control rather than a WST-specific solution."],"forward_implications":["A centralized controller with one 2U unit per detector becomes impractical at ~750 detectors; the distributed design replaces per-detector controllers with commodity Ethernet and rack-scale aggregators.","The 6k scenario (IFS and MOS-LR) can proceed with 1 GbE links and PoE Type 3, while the 12k detector and its FPGA choice can be deferred to MOS-HR maturity because only the interfaces between the two levels are frozen.","Streaming each up-the-ramp sample continuously over the inter-read interval removes simultaneous readout bursts, reducing peak aggregate traffic by roughly a factor of 5–14 and enabling lossless retransmission at no extra hardware cost.","Running slope fitting and cosmic-ray rejection as O(1) per-pixel state at the edge keeps compute one to two orders of magnitude below platform capability and keeps archived data near the few PB/year target.","If correlated or 1/f noise dominates, the required M and cadence increase; the 10 e⁻ and 15 e⁻ rows of Table 1 already exceed the 1 fps ceiling, so the paper's envelope is a lower bound, not a closed detector requirement."],"supporting_citations":[{"why":"defines the WST instrument suite and the ~15-minute sub-exposure used as the sizing integration","marker":"[1]"},{"why":"supplies the detector population and module counts, and flags controller complexity as a dedicated technology study","marker":"[2]"},{"why":"surveys the large-detector-controller trade space, proposes the distributed approach, and gives per-detector power and cold-electronics constraints","marker":"[3]"},{"why":"gives the multiply-sampled read-noise formula that sets the minimum number of UTR samples and hence cadence and bandwidth","marker":"[5]"},{"why":"defines PoE Type 3 and Type 4 classes used to size power delivery over the data cable","marker":"[8]"},{"why":"provides the xTCA/MicroTCA carrier standard the aggregator shelves are based on","marker":"[10]"},{"why":"supplies life-cycle and per-unit power assumptions behind facility power and archive-volume sizing","marker":"[12]"},{"why":"provides the streaming cosmic-ray rejection/jump-detection approach used in the edge-reduction kernels","marker":"[13]"},{"why":"is the planned end-to-end detector simulation path for replacing the optimistic white-noise assumption with correlated-noise models","marker":"[14]"}],"fun_headline_variants":["One cable per detector: power, data, timing for WST's 750","WST's 750 detectors run on distributed PoE nodes","Modular detector nodes slash WST's cabling burden","WST readout: 750 detectors, one cable, no central stack","PoE-powered detector modules simplify WST's readout"],"cache_read_input_tokens":2688,"weakest_assumption_plain":"Everything is sized on the premise that read noise is white and uncorrelated sample to sample, so M non-destructive reads reduce the integrated noise as sqrt(12/M); if 1/f or correlated row noise dominates, the required M and cadence grow and can break the 1 frame/s ceiling, the link speeds, and the PoE class sizing.","fun_headline_variants_meta":{"raw":{"variants":["One cable per detector: power, data, timing for WST's 750","WST's 750 detectors run on distributed PoE nodes","Modular detector nodes slash WST's cabling burden","WST readout: 750 detectors, one cable, no central stack","PoE-powered detector modules simplify WST's readout"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000247,"raw_usage":{"total_tokens":1338,"prompt_tokens":662,"completion_tokens":676,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":406,"completion_tokens_details":{"reasoning_tokens":599}},"tokens_in":406,"tokens_out":676,"duration_ms":8314,"temperature":1.0,"reasoning_tokens":599,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-05T00:23:36.326476+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Take a representative scientific CMOS sensor and measure its noise power spectrum over a 900 s up-the-ramp sequence. If the fitted-slope variance stops decreasing according to sqrt(12/M) once M exceeds the ramp duration divided by the 1/f corner time, the Table 1 Mmin values are too low; recomputing cadence and bandwidth with the measured correlated noise would settle whether the 1 fps ceiling, 2.5/10 GbE choices, and PoE classes still hold.","supporting_citations":[{"cited_title":"WST — Widefield Spectroscopic Telescope: motivation, science drivers and top-level requirements for a new dedicated facility,","cited_arxiv_id":null,"evidence_quote":"defines the WST instrument suite and the ~15-minute sub-exposure used as the sizing integration"},{"cited_title":"WST -- Widefield Spectroscopic Telescope: addressing the instrumentation challenges of a new 12m class telescope dedicated to widefield Multi-object and Integral Field Spectroscopy","cited_arxiv_id":"2405.19198","evidence_quote":"supplies the detector population and module counts, and flags controller complexity as a dedicated technology study"},{"cited_title":"An analysis of large astronomical detector controller systems and implications for future ESO detector systems,","cited_arxiv_id":null,"evidence_quote":"surveys the large-detector-controller trade space, proposes the distributed approach, and gives per-detector power and cold-electronics constraints"},{"cited_title":"Multiply sampled read -limited and background -limited noise performance,","cited_arxiv_id":null,"evidence_quote":"gives the multiply-sampled read-noise formula that sets the minimum number of UTR samples and hence cadence and bandwidth"},{"cited_title":"Power over Ethernet over 4 pairs (Type 3 and Type 4)","cited_arxiv_id":null,"evidence_quote":"defines PoE Type 3 and Type 4 classes used to size power delivery over the data cable"},{"cited_title":"MicroTCA.4 — enhancements for rear I/O and precision timing,","cited_arxiv_id":null,"evidence_quote":"provides the xTCA/MicroTCA carrier standard the aggregator shelves are based on"},{"cited_title":"Sustainability as a design parameter in the early development of the Wide - field Spectroscopic Telescope,","cited_arxiv_id":null,"evidence_quote":"supplies life-cycle and per-unit power assumptions behind facility power and archive-volume sizing"},{"cited_title":"Cosmic -ray rejection and readout efficiency for large -area arrays,","cited_arxiv_id":null,"evidence_quote":"provides the streaming cosmic-ray rejection/jump-detection approach used in the edge-reduction kernels"}],"review_version":1}