{"id":"c81ddcf9-1808-4341-97d0-4d4389d35a7a","arxiv_id":"2608.00754","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":4,"one_line_summary":"A digital chip built from stochastic-computing logic instantiates thermodynamic computing and runs VAEs, flow matching, and free-energy estimation with time-averaged readouts.","lead":"This paper presents a substrate-agnostic theory for thermodynamic computing and a prototype silicon chip, CN101, that runs generative AI models on standard CMOS using random bitstreams instead of traditional arithmetic. It reports that dependent stages of a model can run concurrently, letting deep pipelines finish in roughly the time of one stage rather than the sum.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Section 3.2 asserts without proof that CN101's stochastic-computing datapath has stationary expectation equal to the intended layer function; the known-answer TLA validation uses a different datapath, so the central claim rests on an untested stationarity assumption.","rationale":"The chip's status as a thermodynamic computer depends on f(x)=Eπ[φ(S)] for its actual dynamics. This equality is not derived anywhere for the stochastic-computing multiplier path; Section 3.1.1 even flags the OR-saturation correction as something to be applied at readout, but no unbiased estimator is specified. The paper's strongest independent check (Section 4.1) is on a deliberately different datapath, so the nonlinear AND/OR path is only ever compared to a same-quantization reference under per-T tuned operating points. That arrangement could hide a systematic per-layer bias behind the scale/precision search. This is more load-bearing than the Eq. (5) proof gap in the sense that stage consistency presupposes per-stage stationarity; if the per-tile expectation is wrong, no amount of sequential-parallelism theorem work can rescue the composed result. The concern is empirical and potentially addressable: a fixed-configuration stationarity test against exact arithmetic would either confirm or refute it. The reader's CONDITIONAL verdict is appropriate; the paper should not be ACCEPTed until this is demonstrated or the claim narrowed. The authors are explicit about prototype limitations and bias floors, so this is a technical gap rather than a question of good faith.","tokens_in":24669,"tokens_out":11673,"duration_ms":112982,"concrete_test":"On a single CN101 tile with fixed random 8-bit weights W and bias b, fixed input x, and fixed scale/weight-precision settings (no per-T search), run ReLU and a generic FSM nonlinearity to T=10^8 and compare the time-averaged readout to an independent high-precision floating-point evaluation of σ(Wx+b) over many random x. In parallel, compute the OR-saturation readout correction analytically or by simulation: check whether E[h(OR_T)] converges to h(E[OR]) as T→∞ for the actual product-stream distributions; any nonzero difference quantifies the stationarity bias. If the bias exceeds the reported ~10^-2 floor or scales with the number of OR inputs, the stationarity assumption in Section 3.2 fails.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Section 3.2 states that the weights, biases, and activations loaded onto the chip fix a stationary distribution π satisfying Lπ=0 and f(x)=Eπ[φ(S)], but the transition kernel of the actual datapath is never written down. Section 3.1.1 notes that OR accumulation saturates to mean 1−∏(1−p_i), 'which has to be corrected at readout'; no unbiased correction is specified, and applying a nonlinear inverse to a time average is generally biased (E[h(ÔR)] ≠ h(E[ÔR])), so even infinite T may not recover σ(Wx+b). The one known-answer check, Section 4.1, is explicitly 'a different datapath from the stochastic-computing equilibration the generative models use,' namely linear-integration OU dynamics, so it does not validate the AND/OR SMM-plus-FSM path. The generative comparisons (Appendix F) are against a floating-point reference of the same 8-bit-quantised model, not an independent ground truth, and the VAE per-T operating points are chosen by a search over scale and weight precision (Appendix C), which can absorb systematic datapath bias. If the stationary equality fails for OR saturation, FSM nonlinearities, or split-unipolar readout, CN101 converges to the wrong function on every generative workload.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript proposes a substrate-independent formalization of equilibrium thermodynamic computing, defined by a tuple (S,L,π,φ) with f(x)=E_π[φ(S)], and claims three hardware-level scaling properties: anytime precision, parallel sample aggregation, and sequential parallelism. It then presents CN101, a fabricated digital CMOS chip that implements the formalism using stochastic-computing accumulator dynamics and AND/OR arithmetic, and reports experimental results on digital thermodynamic linear algebra, a conditional VAE on MNIST, a convolutional flow-matching model on CIFAR-10, and free-energy estimation on alanine dipeptide across multiple chips. The central claims are that the chip's dynamics are an ergodic Markov chain whose stationary expectation equals the intended network function, and that concurrent execution of dependent layers converges to the composed function via Eq. (5).","tokens_in":24830,"tokens_out":5311,"duration_ms":52805,"significance":"If the central claims hold, this is a significant contribution: it would decouple the equilibration-style thermodynamic computing formulation from analogue Langevin hardware and demonstrate a digital CMOS instantiation with concrete scaling advantages for generative AI workloads. The formalism is clearly stated and is not circular, since f(x) is defined from a designer-chosen generator and the chip outputs are compared against reference computations. The paper also deserves credit for fabricating a prototype chip, running standard generative models without custom layers, reporting explicit bias floors and burn-in limitations, and providing extensive experimental details in appendices. The significance is conditional, however, on resolving the load-bearing gap identified below: the stationarity of the stochastic-computing datapath is asserted rather than proved or validated on a known-answer test.","major_comments":[{"comment":"The paper asserts, in Section 3.2, that the weights, biases, and activations loaded onto the chip fix a stationary distribution π satisfying Lπ=0 and that the time-averaged readout converges to E_π[φ(S)] = f(x). The transition kernel of the actual stochastic-computing datapath is never written down, and the assertion is not supported for the AND/OR arithmetic. Section 3.1.1 states that OR accumulation 'saturates to mean 1−∏(1−p_i), which has to be corrected at readout,' but no unbiased correction is specified. Applying a nonlinear inverse to a time average is generally biased, so even as T→∞ the readout may not equal the intended layer function σ(Wx+b). Because every generative workload relies on this datapath, this is a load-bearing gap rather than a presentation issue.","section":"Section 3.1.1 / 3.2"},{"comment":"The only known-answer validation on the chip is the thermodynamic linear algebra experiment, but Section 4.1 explicitly states that it exercises 'a different datapath from the stochastic-computing equilibration the generative models use,' namely linear-integration OU dynamics. This experiment therefore cannot confirm that the AND/OR SMM path, the 8-bit deterministic weight gating, the OR saturation readout, or the FSM nonlinearities have stationary expectations equal to the intended functions. A known-answer test on the stochastic-computing path itself, such as exact verification of a random affine-plus-nonlinear layer against a floating-point computation for the same inputs, is needed before the central claim of Section 3.2 can be accepted.","section":"Section 4.1"},{"comment":"The sequential-parallelism guarantee is asserted through the continuous-mapping theorem without proving that the coupled joint Markov chain is ergodic or that its stationary expectation is the composed function (f_L∘⋯∘f_1)(x). The argument requires each stage's time-averaged readout to converge to f_ℓ of the current upstream estimate, which is exactly the property in question; Appendix A defines this as an assumption ('assume each stage is consistent'), effectively restating the claim. The authors need to provide conditions under which the joint chain's stationary distribution yields the composed expectation, or a direct proof that the stage-wise consistency plus continuity of the f_ℓ is sufficient in this coupled, non-independent setting.","section":"Section 2.3.3, Eq. (5)"},{"comment":"The anytime-precision demonstration selects a different operating point for each T by searching over the chip's input-scale and weight-precision knobs (Appendix C). These knobs are free parameters that can absorb systematic datapath bias, so the reported RMSE-versus-T curve does not isolate the anytime property of the hardware. Additionally, the generative reference is the same 8-bit-quantized model run in floating point (Appendix F), which tests consistency with a chosen quantization rather than correctness against independent ground truth; this is a meaningful but weaker claim than 'the chip computes the intended function.'","section":"Appendix C / Fig. 6(c)"}],"minor_comments":[{"comment":"The abstract uses L* for the dynamical generator while Section 2.2 defines L; the notation should be unified.","section":"Abstract / Section 2.2"},{"comment":"The symbol T is used both for temperature (T=300 K) and for readout window length; this overloading is confusing and should be resolved, for example by using β for inverse temperature.","section":"Appendix E"},{"comment":"The caption says the OR gate 'accumulates a column of products,' but an OR gate is not an accumulator in the usual stochastic-computing sense; the caption should clarify that the time average of the OR output is what accumulates the saturation-corrected sum.","section":"Fig. 3(b) caption"},{"comment":"Reference [23] appears incomplete as printed; the author list and full bibliographic details should be supplied.","section":"References"},{"comment":"The caption of Fig. 8 does not define the color scale or the units of per-tile error; these should be stated explicitly.","section":"Fig. 8"}],"recommendation":"major_revision","confidential_remarks":"The core issue is the unproven stationarity of the stochastic-computing datapath. If the authors can supply a rigorous treatment of the transition kernel and its stationary expectation, or a known-answer validation of the AND/OR path, the paper may be publishable; without that, the main claim that CN101 computes f(x)=E_π[φ(S)] is unsupported. The per-T operating-point search and same-model references reduce the force of the experimental validation, but these are secondary to the stationarity gap."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Two things up front. CN101 is a real fabricated chip, and the authors have done genuinely careful measurements on it. The paper's load-bearing assertion, however, is stated, not proved: that the AND/OR stochastic datapath has a stationary expectation equal to the intended layer map, and the one known-answer validation uses a different datapath.\n\nWhat is new: the first digital CMOS instantiation of equilibration-style thermodynamic computing, with four tiles, an on-chip streaming network, and measured generative workloads (VAE, flow matching, alanine free-energy). The formalisation f(x)=Eπ[φ(S)] for an arbitrary ergodic generator is clean, and the analogue Langevin case falls out as a special case. The scaling axes are recognisable properties of Monte Carlo estimation, but the paper states them precisely and the chip demonstrates all three. Credit where due: parity plots are there, bias floors are reported rather than hidden, and energy/latency claims are explicitly deferred.\n\nThe soft spots are in proportion to how much they matter. The biggest one is the stationarity claim. Section 3.1.1 says OR accumulation saturates to mean 1−∏(1−p_i) and has to be corrected at readout; applying a nonlinear inverse to a time average is biased in general, so even infinite T may not recover the intended sum. No unbiased correction is specified. The TLA validation in Section 4.1 is explicitly 'a different datapath' from the stochastic-computing equilibration the generative models use, so it does not cover this path. Because the generative reference is the same 8-bit quantised model in floating point, systematic datapath error could be absorbed by the comparison. This is not a small objection; it is the center of the paper. It is fixable: write down the transition kernel for one tile and prove the stationary expectation, or supply an unbiased readout correction and validate on a known nonlinear map.\n\nSecond, the sequential-parallelism guarantee (Eq. 5) is asserted through the continuous-mapping theorem, but that theorem applies to a fixed input sequence, not to a coupled joint chain with feedback. Appendix A's induction assumes exactly the consistency that needs proving. The VAE experiment is suggestive, not proof. Third, the CIFAR sequential baseline is self-admittedly unfinished — 60 of 100 layers never meet their convergence target — so the 62× figure is not a clean comparison. The VAE anytime curve is per-T operating-point search; less serious, but it should be labelled as such.\n\nWho is this for: anyone working on stochastic-computing accelerators, thermodynamic computing, or energy-constrained generative AI. It deserves a serious referee. I would send it to one with a request for a proof or a fixed-configuration known-answer experiment on the nonlinear path, and a clean sequential baseline, before accepting.","headline":"A real digital CMOS prototype with honest measurements, but the central stationarity claim is asserted rather than proved, and the baseline comparisons are softer than the headline numbers suggest.","tokens_in":25537,"tokens_out":3534,"would_cite":false,"duration_ms":33421,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A digital CMOS chip computes generative AI by averaging random bitstreams.","keywords":["thermodynamic computing","equilibration formalism","stochastic computing","generative AI","flow matching","sequential parallelism","anytime precision","free-energy estimation"],"falsifier":"Program a single tile with known weights and bias, choose an activation that is neither linear nor ReLU (for example the finite-state-machine sigmoid path), run to a long averaging window, and compare the chip's time-averaged readout against the exact $\\sigma(Wx+b)$ computed in floating point; a systematic offset that persists beyond the 8-bit weight-quantisation floor would falsify the claim that the chip's stationary expectation equals the intended function.","tokens_in":24315,"feed_emoji":"⚙️","tokens_out":11140,"duration_ms":91626,"temperature":0.7,"pith_summary":"The paper tries to establish that the equilibration style of thermodynamic computing—evaluating a function as the stationary expectation of an ergodic stochastic process—is not tied to analogue Langevin hardware. It gives a substrate-independent definition of such a computation as a tuple $(S,L,\\pi,\\varphi)$ with $f(x)=E_\\pi[\\varphi(S)]$, where $L$ is any ergodic dynamical generator. The authors then instantiate this definition on CN101, a digital CMOS test chip whose accumulator-based stochastic-computing dynamics form a discrete Markov chain. On that chip they demonstrate digital thermodynamic linear algebra, a conditional VAE on handwritten digits, flow-matching image generation, and free-energy estimation on alanine dipeptide, matching floating-point references of the same quantized models. If the central claim holds, thermodynamic computing's hardware benefits—anytime precision, parallel sample aggregation, and sequential parallelism—are available on ordinary digital silicon rather than only on analogue substrates.","feed_headline":"A digital CMOS chip computes generative AI by averaging random bitstreams","feed_subtitle":"On a standard CMOS test chip, the same equilibration logic runs VAEs, flow matching, and free-energy estimation.","key_machinery":"The load-bearing object is the equilibration tuple $(S,L,\\pi,\\varphi)$ together with the time-averaged readout equation. $L$ is the generator of an ergodic Markov chain; the paper's key move is that $L$ may be a discrete accumulator-based stochastic-computing datapath rather than a continuous Langevin operator. On CN101 the machinery consists of 8-bit deterministic weights gated by AND gates against stochastic input bitstreams, OR-based column accumulation, split-unipolar encoding for signed arithmetic, per-neuron 65-bit LFSR pseudo-random generators, a deterministic multi-bit path inside each tile, and the stochastic streaming network-on-chip that carries bitstreams between tiles on independent clocks. The analytical engine for sequential parallelism is the continuous-mapping theorem: if each layer map is continuous, a downstream stage consuming a still-converging estimate stays consistent, so the pipeline converges almost surely to the composed function as the joint relaxation proceeds.","core_discovery":"The paper's central claim is that a thermodynamic computation is fully specified by the dynamical generator $L$ of an ergodic process, not by any specific physics. On a state space $S$, with generator $L$ parametrized by the input $x$, unique stationary distribution $\\pi$ satisfying $L\\pi=0$, and readout $\\varphi$, the computed function is $f(x)=E_\\pi[\\varphi(S)]$, returned as the time-averaged readout $\\hat y_T=\\frac{1}{T}\\sum_t \\varphi(S_t)$, which converges almost surely as $T\\to\\infty$. The Ornstein–Uhlenbeck dynamics of prior analogue work are one special case; a discrete-state Markov chain realized in digital logic is another. The paper reports that CN101 embodies the second case: four tiles of $64\\times 64$ stochastic matrix multipliers, reconfigurable neuron banks, and a stochastic streaming network-on-chip form a joint Markov chain whose stationary expectation is the composed network function. The paper's Eq. (5) claims, via the continuous-mapping theorem, that an $L$-stage pipeline of continuous layer maps converges almost surely to the composed function $(f_L\\circ\\cdots\\circ f_1)(x)$ even when downstream stages consume still-converging upstream estimates, which is the basis for running dependent stages concurrently.","pith_inferences":["One extension the paper does not itself run is a stress test of the stationarity assumption on a generic finite-state-machine nonlinearity such as sigmoid or tanh; the chip contains an FSM activation path, and a direct long-window readout comparison would show whether the accumulator dynamics' stationary mean equals the intended function for non-ReLU layers.","If the same joint-relaxation argument transfers to autoregressive language models, token generation could be organized as a single relaxation over token positions, each consuming still-converging estimates of earlier positions, so wall-clock could scale sublinearly in sequence length; the paper does not attempt this extension.","Building on the paper's stated preference for learned non-equilibrium protocols, one testable extension is to drive the accumulator chain through a finite-time schedule and see whether the burn-in floor that limits parallel sample aggregation is reduced.","The reported bias floor is attributed to 8-bit weight-register precision, which suggests a testable hardware lever: increasing register width or adding a readout correction should lower the floor on all workloads, since the paper identifies quantisation rather than the formalism as the cause."],"forward_implications":["Precision becomes a runtime knob: a single run of the chip returns a usable coarse estimate at short windows and refines it monotonically as the averaging window grows, so workloads can stop once the downstream task's accuracy is reached.","Independent trajectories are statistically independent, so averaging $K$ parallel replicas reduces the estimator variance by a factor $K$ with no inter-replica coordination, although the burn-in bias is shared across replicas and cannot be averaged away.","Dependent stages of a deep generative model can relax concurrently: in the CIFAR-10 flow-matching experiment the unrolled 100-layer integration reached the floating-point reference at about $10^7$ cycles per pixel, versus roughly $6.2\\times 10^8$ cycles when layers were run sequentially, a factor near 62 at that accuracy target.","The formulation is substrate-independent, so future instantiations may use any ergodic dynamics—analogue, digital, or hybrid—whose stationary distribution is programmable, removing the CMOS toolchain restriction that analogue thermodynamic hardware faces.","On a molecular benchmark, the chip's free-energy estimates agree with the CPU estimate of the same flows to within $0.8$ kJ/mol and track an umbrella-sampling reference for five of the six alanine-dipeptide basins."],"supporting_citations":[{"why":"Defines Thermodynamic Linear Algebra and the Ornstein–Uhlenbeck encoding whose stationary mean solves Ax=b; this is the formalism's original problem class and the linear-system encoding the chip validates.","marker":"[5]"},{"why":"The analogue Stochastic Processing Unit that first implemented TLA in hardware; provides the analogue baseline and the bias-floor comparison for CN101.","marker":"[6]"},{"why":"Introduces stochastic computing systems, the bitstream representation and AND/OR arithmetic on which the chip's datapath is built.","marker":"[15]"},{"why":"Survey of stochastic computing that supplies the design context for the accumulator datapath and finite-state-machine nonlinear activations.","marker":"[16]"},{"why":"The ergodic theorem for Markov chains that guarantees the time-averaged readout converges almost surely to E_π[φ(S)].","marker":"[18]"},{"why":"The continuous-mapping theorem used to show an L-stage pipeline of continuous maps converges almost surely to the composed function, the basis of sequential parallelism.","marker":"[21]"},{"why":"Defines flow matching, the generative model class used for the CIFAR-10 and alanine-dipeptide workloads.","marker":"[49]"},{"why":"Provides the multistate free-energy estimation protocol and the flat-bottom basin state definitions used for alanine dipeptide.","marker":"[55]"},{"why":"Targeted free-energy perturbation, the estimator whose forward and reverse works the chip computes and combines with the Bennett acceptance ratio.","marker":"[57]"}],"fun_headline_variants":["Digital thermodynamic AI chip averages random bitstreams","Thermodynamic computing goes digital for generative AI","No analog needed: digital chip does thermodynamic AI","Averaging random bits runs generative AI on CMOS"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The argument assumes that for every implemented layer the stochastic-computing accumulator dynamics settle to a long-run average exactly equal to the layer's mathematical output; if a nonlinearity or saturation effect makes that average come out differently, the chip would converge to the wrong function.","fun_headline_variants_meta":{"raw":{"variants":["Digital thermodynamic AI chip averages random bitstreams","Thermodynamic computing goes digital for generative AI","No analog needed: digital chip does thermodynamic AI","Averaging random bits runs generative AI on CMOS"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001025,"raw_usage":{"total_tokens":4406,"prompt_tokens":1113,"completion_tokens":3293,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":729,"completion_tokens_details":{"reasoning_tokens":3233}},"tokens_in":729,"tokens_out":3293,"duration_ms":21732,"temperature":1.0,"reasoning_tokens":3233,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T15:17:07.165022+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Program a single tile with known weights and bias, choose an activation that is neither linear nor ReLU (for example the finite-state-machine sigmoid path), run to a long averaging window, and compare the chip's time-averaged readout against the exact $\\sigma(Wx+b)$ computed in floating point; a systematic offset that persists beyond the 8-bit weight-quantisation floor would falsify the claim that the chip's stationary expectation equals the intended function.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Introduces stochastic computing systems, the bitstream representation and AND/OR arithmetic on which the chip's datapath is built."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Survey of stochastic computing that supplies the design context for the accumulator datapath and finite-state-machine nonlinear activations."},{"cited_title":"Meyn and Richard L","cited_arxiv_id":null,"evidence_quote":"The ergodic theorem for Markov chains that guarantees the time-averaged readout converges almost surely to E_π[φ(S)]."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"The continuous-mapping theorem used to show an L-stage pipeline of continuous maps converges almost surely to the composed function, the basis of sequential parallelism."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Defines flow matching, the generative model class used for the CIFAR-10 and alanine-dipeptide workloads."},{"cited_title":"Bronstein, and Max Welling","cited_arxiv_id":null,"evidence_quote":"Provides the multistate free-energy estimation protocol and the flat-bottom basin state definitions used for alanine dipeptide."}],"review_version":2}