{"id":"7bba4b22-14ab-4ad7-8930-70c06895d780","arxiv_id":"2608.00990","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":7,"one_line_summary":"Including readout-amplifier bias-wire heat in cryogenic models moves the bottleneck to the 4 K stage and lowers estimated qubit capacity for modern superconducting systems.","lead":"This paper builds a heat-flow model for the wiring and amplifiers inside dilution refrigerators that cool superconducting quantum computers, and shows the readout amplifier chain, not the qubit wiring, becomes the main heat bottleneck in modern machines. It matters because earlier models missed this and may have overestimated how many qubits a fridge can support.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Headline capacity drop depends on AWG30 copper bias wires and 4× readout multiplexing; with AWG35 or 8× multiplexing the 4 K bottleneck weakens and the '2× overestimation' result may not hold.","rationale":"The paper is a serious engineering model with posted code, and the qualitative point—bias-line PHL/OHL are absent from several prior models and matter at scale—is worth publishing. My concern is not that the model is internally inconsistent; it is that the headline conclusion is conditioned on a narrowly chosen baseline amplifier module. The paper itself says 'the choice of bias-wire material directly determines the total thermal load' (Section V), and Table 10 shows ULP-HEMT goes from 40.74 mW (Cu) to 0.369 mW (Manganin), nearly two orders of magnitude. With that much sensitivity, a single default wire gauge cannot support the universal 'dominant bottleneck' statement. The reader's KIDE concern is a special case of the same problem (unverified inputs); I would prioritize the wire-gauge/multiplexing sensitivity because it can be tested with the existing code and because even vendor-quoted KIDE powers would not rescue the conclusion if the real system uses thinner or alloy bias wires. Therefore I keep the CONDITIONAL verdict—the model is useful as a framework, but the headline numbers should be labeled with the exact wire and multiplexing assumptions, or replaced by a sensitivity range.","tokens_in":53745,"tokens_out":10235,"duration_ms":104791,"concrete_test":"Rerun the posted code for the Section IV-C HDW/XLD1000sl configuration with AWG35 copper bias wires (use Table 3's 1.23 mW/wire PHL; set OHL negligible since Cu OHL is <1 µW) and with 8× instead of 4× readout multiplexing, keeping all other parameters fixed. Also rerun Section IV-A (Cri/oFlex+KIDE) with AWG35. If the HDW capacity returns to ≥120 or the 4 K stage ceases to be the unique bottleneck, the headline 'amplifier heat dominates modern systems' is an artifact of the AWG30/4× assumptions rather than a robust result.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central quantitative result is set by two input choices that are not varied in the headline: (i) every 4 K HEMT is biased by three AWG30 copper wires, and (ii) readout is 4× multiplexed. Table 3 lists 6.81 mW/wire PHL into 4 K for AWG30, versus 1.23 mW/wire for the AWG35 copper wires used in the canonical system [8]—a 5.5× difference. Because the paper switches from AWG35 (only for [8]) to AWG30 (for all other configurations, Section III-B/Table 3), the per-amplifier 4 K load is 28.07 mW in Table 10 instead of ~11.5 mW with AWG35. This is exactly what produces the Section IV-C HDW result: capacity drops from [11]'s 144 to ~80 when bias-line PHL is added. If installed bias wiring is AWG35 (or a lower-conductance alloy such as Manganin, which the paper itself treats as a mitigation), the same model would return ~144 or higher, and the 'omission causes ~2× overestimation' claim would not hold. The 4× multiplexing assumption similarly sets one amplifier per 4 qubits; at 8× multiplexing the per-qubit amplifier heat is halved. The paper notes this sensitivity in Section V but does not propagate it into the abstract or Section IV-A conclusion. Section VII hedges that the model identifies trends rather than exact operating points, but the headline is stated without these conditions. The KIDE cooling-power uncertainty flagged by the reader is real, but this bias-wire/multiplexing sensitivity is more direct: it changes the conclusion even under the paper's own assumed fridge.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper develops a steady-state thermal scalability model for large-scale superconducting quantum systems, adding previously omitted readout-amplifier heat terms: active dissipation, passive conduction through bias wires, and ohmic (Joule) heating in those wires. The model is validated against the 100-qubit-scale system of [8], reproducing its 144-qubit capacity with CP as the bottleneck. The authors then apply the model to modern configurations with lower-PHL wiring (HDW, Cri/oFlex) and higher-capacity fridges (KIDE), concluding that amplifier-associated heat at 4 K becomes the dominant bottleneck and that prior system-level models that omit amplifier bias-wire loads misidentify the bottleneck and overestimate physical-qubit capacity. The paper also explores mitigation options (Manganin or YBCO bias wires, ULP-HEMT and SIS amplifiers, current splitting), integrates surface-code logical-error simulations to estimate logical-qubit yield, and assesses forward-looking 10k-qubit pathways with optical interconnects and the Colossus platform.","tokens_in":54292,"tokens_out":5438,"duration_ms":63608,"significance":"If the central claim survives scrutiny, this is a useful and timely correction to system-level cryogenic scalability models: it identifies a concrete, currently omitted heat term that changes the location of the thermal bottleneck and the estimated qubit capacity of modern systems. The framework is flexible and transparent, with the full implementation publicly available, validation against a real system (Section IV-A), and a conservative treatment of several secondary heat sources. The T-pad attenuator analysis (Appendix A-E) and the optimal current-splitting expression (Eq. 8) are clean and transferable. However, the main quantitative conclusions are conditional on a few unvaried architectural assumptions, so the strength of the abstract currently runs ahead of the demonstrated robustness.","major_comments":[{"comment":"The HDW comparison that yields the headline 'roughly half' capacity reduction (144 to ~80 qubits) is driven by the choice of AWG30 copper bias wires, whose PHL into 4 K is 6.81 mW/wire, versus 1.23 mW/wire for the AWG35 wires used in [8]. Using AWG35, the per-amplifier 4 K load in Table 10 would be about 7.8 mW + 3×1.23 mW ≈ 11.5 mW instead of 28.07 mW, which could largely or entirely close the gap with [11]'s 144-qubit estimate. The paper does not report this sensitivity, even though AWG35 is a plausible installed-wire choice. The claim that omitting bias-line PHL causes a ~2× overestimation therefore needs to be quantified as a function of wire gauge.","section":"Section IV-C / Table 3 / Appendix B-G"},{"comment":"All system-level results assume 4× readout multiplexing, which fixes one amplifier per four qubits. Section V acknowledges that 8× multiplexing halves the number of amplifiers and their associated heat, but no system-level sweep over the multiplexing factor is presented. Since the central claim is that amplifier heat is the dominant 4 K bottleneck, halving that load could shift the bottleneck to CP or MXC under otherwise identical assumptions. The abstract and the Section IV-A conclusion should either be conditioned on the multiplexing factor or accompanied by a sensitivity analysis showing that the bottleneck identification is robust.","section":"Section V / Section IV-A"},{"comment":"The modern-system scenarios in Section IV-A and Section V rely on KIDE cooling powers (90 W at 50 K, 6 W at 4 K, 90 mW at Still, 3 mW at CP, 90 µW at MXC) estimated by treating KIDE as three independent XLD1000sl-class dilution units. These values are not measured, as the paper states. The claim that the bottleneck 'has shifted to 4 K' and is dominated by amplifier heat depends on these assumed powers. The authors should provide a sensitivity analysis varying the KIDE cooling profile, or explicitly restrict the conclusion to 'under the assumed KIDE cooling budget.'","section":"Appendix A-A / Table 1"}],"minor_comments":[{"comment":"The notation 'L / A(TH-TL) ∫' is ambiguous: it should be written as (L/(A(TH-TL))) ∫ or with explicit parentheses, since it could be read as L/(A(TH-TL)) or L/A × (TH-TL).","section":"Eq. (3) and Eq. (4)"},{"comment":"The resistance entries for AWG35 copper are listed as '-' even though the OHL for the [8] reconstruction depends on it. If AWG35 resistance is unavailable, the text should state the impact of this missing parameter on the relevant heat budgets.","section":"Table 3"},{"comment":"The PHL of the hypothetical shielded YBCO stripline is set to 5× the PHL of a single YBCO bias wire by assumption. This multiplier directly affects the 12k/16k qubit estimates. It is flagged in the text as an estimate, but the basis for the factor of five should be stated more explicitly.","section":"Section VI-1"},{"comment":"Section VII appropriately states that the model identifies trends rather than exact operating points, but the abstract states the bottleneck shift as an unconditional result. The abstract should be softened to reflect the parametric dependence noted above.","section":"Abstract / Section VII"}],"recommendation":"major_revision","confidential_remarks":null},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Worth a read, but read the fine print. The paper extends prior cryogenic heat models by adding the passive and ohmic load of readout-amplifier bias wires. That is a real omission in [8]/[11], and the authors make a clean case that once you switch to low-PHL microwave cabling and a stronger fridge, the 4 K budget fills up with amplifier active heat plus bias-line conduction. The model itself is transparent, the code is posted, and they reproduce the [8] CP bottleneck, which is the right kind of validation for a systems paper. The T-pad circuit derivation and the current-splitting optimum are also straightforward and useful.\n\nThe soft spot is the headline. The HDW result — 144 to ~80 qubits — is set by two assumptions that are not varied in the abstract: three AWG30 copper bias wires per amplifier and 4× readout multiplexing. AWG30 is 6.81 mW/wire into 4 K; the AWG35 copper wires in the canonical [8] system are 1.23 mW/wire. If installed wiring is AWG35, the same model puts the HDW system at roughly 144 qubits again, and the “2× overestimation” claim collapses. The paper does disclose the multiplexing sensitivity in Section V and hedges in Section VII that the model tracks trends rather than exact operating points, but the abstract and Section IV conclusion are categorical. The KIDE cooling power is also an estimate (3× XLD1000sl), and there are no error bars. None of this kills the core qualitative message — amplifier bias PHL is a first-order term that prior models ignored — but the quantitative capacity numbers should be presented as a scenario, not a measurement.\n\nThe citation pattern looks honest: they build on [8], [9], [11] and are clear about what is new. The “invented entities” in the stress-test note are labeled as hypothetical, so no problem there. The logical-qubit yield part is more auxiliary than central, but it doesn't undercut the thermal analysis.\n\nWho this is for: cryogenic system architects and anyone doing full-stack scaling estimates for superconducting quantum computers. It belongs in the literature, but the version in front of us needs a sensitivity sweep over wire gauge, multiplexing factor, and fridge cooling profile before its conclusions can be taken at face value. I would not desk-reject; send it to review with a referee who will push on those parameters.","headline":"Careful model that adds a real missing term, but the flashy result (144→80 qubits) depends on AWG30 copper wire and 4× multiplexing; still worth refereeing.","tokens_in":54734,"tokens_out":2785,"would_cite":true,"duration_ms":32855,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":["03.67.Lx","07.20.Mc","85.25.-j"],"model":"deepseek-v4-flash","headline":"Readout-amplifier heat—dissipation plus bias-wire conduction—is the dominant thermal bottleneck in modern superconducting quantum systems, and omitting it overestimates qubit capacity by up to about a factor of two.","keywords":["thermal scalability","superconducting qubits","cryogenic readout amplifiers","passive heat load","dilution refrigerator","bottleneck migration","fault-tolerant quantum computing","amplifier bias wiring"],"falsifier":"Measure the actual residual cooling power of a KIDE-class platform at 4 K and CP under load, and calorimetrically measure the steady heat conducted into 4 K by one AWG30 copper amplifier-bias wire over the 50 K–4 K span. If the per-wire conduction is well below the model's roughly 6.8 mW, or if the real 4 K capacity is much larger than 6 W, the claim that amplifier bias wires dominate the modern 4 K budget and cap capacity at about 80 qubits in the HDW case would fail, and the bottleneck would sit elsewhere.","tokens_in":53645,"feed_emoji":"❄️","tokens_out":8132,"duration_ms":76139,"temperature":0.7,"pith_summary":"The paper sets out to correct the system-level heat accounting used to decide how many superconducting qubits a dilution refrigerator can support. Its central claim is that the readout amplification chain—the active power dissipated by 4 K amplifiers, the passive heat conducted down their bias wires, and Joule heating in those wires—is now the dominant thermal bottleneck in modern cryogenic systems, a term earlier scalability models omit or only partially include. Under the paper's accounting, that omission is not benign: in the high-density-wiring system previously estimated to hold about 144 qubits, the corrected model supports about 80; in an optical-architecture claim of roughly 3,000 qubits, the corrected model yields about 170. The paper then maps which amplifier-and-wiring combinations reduce the amplifier load and shows that lowering amplifier power alone often does not help because bias-wire conduction or ohmic heat takes over. A sympathetic reader would care because the paper redirects engineering priorities: improving refrigeration and cable heat loads only exposes amplifier heat as the next wall, so single-fridge 10k-qubit systems require solving the readout chain's thermal footprint first.","feed_headline":"Amplifier heat cuts cryogenic qubit capacity in half","feed_subtitle":"Bias-wire conduction, not fridge power, now sets the limit on how many qubits a dilution refrigerator can hold.","key_machinery":"The carrying device is a stage-by-stage ledger of normalised heat load (NHL): each contribution—passive conduction, active dissipation, ohmic (Joule) heating—is divided by the cooling power of the stage that absorbs it, and the first stage whose cumulative NHL reaches unity sets the physical-qubit capacity. The new term inserted into that ledger is the amplifier module's full three-part load, and the argument's engine is bottleneck migration: improving wiring and refrigeration moves the limiting stage from the cold plate toward 4 K, where the amplifier terms dominate.","core_discovery":"The paper's central discovery is that amplifier-associated heat—three mechanisms bundled in one module: the always-on dissipation of the cryogenic readout amplifier, passive conduction through its DC bias wires, and Joule heating in those same wires—emerges as the dominant normalised heat load at the 4 K stage once modern low-PHL wiring and higher-capacity refrigerators relieve the millikelvin stages. Where prior models placed the bottleneck at the cold plate (as in the stainless-steel, XLD400 system that supports 144 qubits), the modernised configuration (Cri/oFlex wiring in a KIDE fridge) shifts the bottleneck to 4 K and makes amplifier heat the first constraint; when bias-wire passive con","pith_inferences":["If the paper's accounting is right, an immediate test is available from operating hardware: calorimetric measurement of the 4 K heat floor of one tiled readout chain (amplifier plus its bias wires) in a production dilution refrigerator would either confirm or contradict the roughly 7 mW per wire of passive conduction that drives the headline result.","The same three-term ledger should apply to any other always-on component with room-temperature-to-4 K wiring—bias-T networks, DC blocks, cryogenic CMOS control electronics—so the framework is a template for auditing those subsystems as they scale.","The results imply readout multiplexing is a thermal lever as much as a wiring one: doubling multiplexing from 4x to 8x halves the number of amplifier modules and, with copper wiring, nearly halves the dominant 4 K load—a tradeoff the paper flags but does not quantify.","A testable engineering corollary: because bias-wire material alone moves the per-amplifier load by nearly two orders of magnitude, swapping copper bias wires for Manganin or YBCO in an existing machine should measurably extend the 4 K margin before any amplifier or fridge upgrade."],"forward_implications":["Systems designed with older models will underestimate the 4 K stage's stress; adding amplifier bias-line passive conduction alone cuts the HDW/XLD1000sl capacity from about 144 to about 80 physical qubits.","Reducing amplifier active power is not sufficient: with copper bias wires every amplifier option is dominated by bias-wire passive conduction, so the lowest-active-power amplifier (ULP-HEMT) carries the largest total load when paired with copper.","Amplifier-heat reductions saturate: once the per-amplifier 4 K budget drops below about 2 mW, the bottleneck migrates to MXC at roughly 4,688 qubits, so further amplifier improvements add no capacity.","With today's components in a KIDE-class fridge the system reaches only about 700–800 physical qubits; reaching 10k requires optical interconnects with the photodetector at 4 K, YBCO-based superconducting microwave striplines, or a Colossus-class fridge with dilution units redistributed toward the cold plate.","Even if lower-gain amplifier chains degrade measurement error by up to 4x, the larger physical-qubit budget still yields more logical qubits than the current HEMT-copper baseline (about 4 versus 2 at a target logical error rate of 0.001)."],"supporting_citations":[{"why":"Original 100-qubit-scale system model (SS cables, XLD400); supplies the canonical baseline the paper reproduces and the SS/copper heat values it renormalizes.","marker":"[8]"},{"why":"HDW + XLD1000sl scalability study whose 144-qubit estimate falls to about 80 once amplifier-bias PHL is added.","marker":"[11]"},{"why":"Optical-interconnect study (photodetector at 4 K) whose multi-thousand-qubit estimate the paper shows misidentifies the photodetector as the bottleneck.","marker":"[9]"},{"why":"Cri/oFlex microstrip wiring data; the low-PHL interconnect whose adoption drives the bottleneck migration toward 4 K.","marker":"[12]"},{"why":"KIDE platform specification; the projected fridge cooling profile used for all modern-system scenarios.","marker":"[14]"},{"why":"YBCO-on-Kapton cable measurements; the superconducting bias-wire and stripline option that sets the optimistic upper bound.","marker":"[25]"},{"why":"Sub-milliwatt ULP-HEMT amplifier; the low-active-power option whose bias-line count makes it best or worst depending on wiring material.","marker":"[38]"},{"why":"Surface-code error-correction demonstration; supplies the physical error rates and CZ operation latencies used in both the ESM workload and the logical-error model.","marker":"[3]"}],"fun_headline_variants":["Amplifier heat, not fridge, now sets qubit scalability limit","Readout amp heat is the new bottleneck for cryogenic qubits","Bias-wire conduction and amp heat cap qubit count in cryostats","Thermal bottleneck shifts to amplifier module in modern quantum systems","Amp heat at 4K stage limits qubit packing more than fridge power"],"cache_read_input_tokens":2816,"weakest_assumption_plain":"The modern-system numbers rest on an unverified input: the cooling powers assumed for the KIDE refrigerator (90 W at 50 K, 6 W at 4 K, 90 mW at Still, 3 mW at CP, 90 µW at MXC) are estimates obtained by treating KIDE as three independent XLD1000sl-class units, because measured values are not public; if the real 4 K or CP cooling profile differs materially, the point at which amplifier heat becomes the dominant bottleneck, and the headline capacity figures, would shift.","fun_headline_variants_meta":{"raw":{"variants":["Amplifier heat, not fridge, now sets qubit scalability limit","Readout amp heat is the new bottleneck for cryogenic qubits","Bias-wire conduction and amp heat cap qubit count in cryostats","Thermal bottleneck shifts to amplifier module in modern quantum systems","Amp heat at 4K stage limits qubit packing more than fridge power"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000168,"raw_usage":{"total_tokens":1079,"prompt_tokens":708,"completion_tokens":371,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":452,"completion_tokens_details":{"reasoning_tokens":275}},"tokens_in":452,"tokens_out":371,"duration_ms":4113,"temperature":1.0,"reasoning_tokens":275,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-06T00:35:49.836577+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the actual residual cooling power of a KIDE-class platform at 4 K and CP under load, and calorimetrically measure the steady heat conducted into 4 K by one AWG30 copper amplifier-bias wire over the 50 K–4 K span. If the per-wire conduction is well below the model's roughly 6.8 mW, or if the real 4 K capacity is much larger than 6 W, the claim that amplifier bias wires dominate the modern 4 K budget and cap capacity at about 80 qubits in the HDW case would fail, and the bottleneck would sit elsewhere.","supporting_citations":[{"cited_title":"Engineering cryogenic setups for 100-qubit scale superconduct- ing circuit systems","cited_arxiv_id":null,"evidence_quote":"Original 100-qubit-scale system model (SS cables, XLD400); supplies the canonical baseline the paper reproduces and the SS/copper heat values it renormalizes."},{"cited_title":"Cryogenic thermal modeling of microwave high density signaling","cited_arxiv_id":null,"evidence_quote":"HDW + XLD1000sl scalability study whose 144-qubit estimate falls to about 80 once amplifier-bias PHL is added."},{"cited_title":"Scaling up superconducting quantum computers with cryogenic rf-photonics","cited_arxiv_id":null,"evidence_quote":"Optical-interconnect study (photodetector at 4 K) whose multi-thousand-qubit estimate the paper shows misidentifies the photodetector as the bottleneck."},{"cited_title":"Flexible cryogenic i/o","cited_arxiv_id":null,"evidence_quote":"Cri/oFlex microstrip wiring data; the low-PHL interconnect whose adoption drives the bottleneck migration toward 4 K."},{"cited_title":"KIDE Cryogenic Platform — bluefors.com","cited_arxiv_id":null,"evidence_quote":"KIDE platform specification; the projected fridge cooling profile used for all modern-system scenarios."},{"cited_title":"Ybco-on-kapton: Material for high-density quantum computer interconnects with ultra-low thermal loss","cited_arxiv_id":null,"evidence_quote":"YBCO-on-Kapton cable measurements; the superconducting bias-wire and stripline option that sets the optimistic upper bound."},{"cited_title":"Sub-mw cryogenic inp hemt lna for qubit readout","cited_arxiv_id":null,"evidence_quote":"Sub-milliwatt ULP-HEMT amplifier; the low-active-power option whose bias-line count makes it best or worst depending on wiring material."},{"cited_title":"Abanin, Laleh Aghababaie-Beni, Igor Aleiner, Trond I","cited_arxiv_id":null,"evidence_quote":"Surface-code error-correction demonstration; supplies the physical error rates and CZ operation latencies used in both the ESM workload and the logical-error model."}],"review_version":1}