{"id":"32a4c542-6c58-4887-be89-91d98168b5f1","arxiv_id":"2608.01946","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"LEAP predicts per-cycle toggle propagation with PR-AUC 0.99 and 7.6x speedup over PTPX, enabling fast per-cycle layout power prediction from post-synthesis netlists.","lead":"A new machine learning model predicts per-cycle signal toggling in chip netlists 7.6 times faster than a commercial EDA tool, with near-perfect accuracy. It also plugs into power estimators to predict layout power directly from early netlists, which could speed up chip design iterations.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Pre-training data split is unspecified; if test designs are included in self-supervised pre-training, the reported cross-design PR-AUC of 0.99 may reflect leakage rather than transfer.","rationale":"The reader's stated weakest assumption incorrectly claims that designs overlap between training and test sets under the 2-fold split. Reading the paper's Section 6.2, Setting 1 trains on D2/D4/D7/D9/D11 with Median and tests on all remaining designs with all three workloads; Setting 2 does the reverse. Thus each design is tested only when it is excluded from fine-tuning training. The reader's concern about identical design IDs appearing in both train and test is therefore factually mistaken. However, the reader's broader intuition about data leakage is on the right track, but the actual risky mechanism is in the pre-training stage. The paper never specifies whether the self-supervised pre-training (Section 5.1) uses all 12 designs or only the training fold. Since pre-training tasks involve predicting output pin values, switching probabilities, and reconstructing functional embeddings, the model could learn design-specific behaviors from the test designs before any fine-tuning. With only 12 designs, such leakage could plausibly produce the near-perfect PR-AUC. This is a load-bearing concern because the central claim is specifically about cross-design and cross-workload transferability. The paper should clarify the pre-training data split and, ideally, present results with a clean split. Because this is a verifiable and fixable issue, the conditional verdict remains appropriate; if the clean-split experiment fails, the verdict should be REJECT. I recommend UNCHANGED, meaning the verdict stays CONDITIONAL pending the additional experiment and clarification.","tokens_in":11745,"tokens_out":6844,"duration_ms":69864,"concrete_test":"Re-run the 2-fold evaluation with pre-training restricted to the fine-tuning training designs (Setting 1 pre-train on D2/D4/D7/D9/D11 with Median; Setting 2 pre-train on D1/D3/D5/D6/D8/D10/D12 with Median), then fine-tune and evaluate on the held-out designs. Compare the average PR-AUC to Table 2. If the PR-AUC drops materially below 0.99, the original results are unsupported by the transferability claim.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim is that LEAP generalizes across designs, achieving PR-AUC 0.99. The paper's 2-fold validation (Section 6.2) and the claim of transferability depend on test designs being completely unseen during training. However, the self-supervised pre-training stage (Section 5.1) is described without stating whether it uses all 12 designs or only the fine-tuning training fold. If pre-training uses all 12 designs, then for each fold the model has already seen the test designs' netlists, per-cycle output pin values (used in task L#1), and static switching characteristics during pre-training. The subsequent fine-tuning then only adapts to the toggle-prediction task on designs whose structure and behavior the model has already observed, which undermines the 'cross-design' generalization claim. Given that there are only 12 designs, this leakage could fully explain the near-perfect PR-AUC, making the claimed transferability unsubstantiated. The paper must explicitly describe the pre-training data split and, if necessary, re-run the evaluation with pre-training restricted to the training fold. Note: the reader's weakest assumption about same designs appearing in both train and test is a misreading; the fine-tuning test sets exclude the fine-tuning training designs, but the pre-training leakage concern is distinct and serious.","agreement_with_reader":"disagree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes LEAP, a per-cycle toggle propagation prediction model for gate-level netlists. LEAP uses a linear-complexity graph transformer with a novel linear-causal attention mechanism that restricts each node to information from earlier topological depths, mimicking signal propagation. A self-supervised pre-training stage (tasks for output-pin-value prediction, static switching-characteristic regression, and functional embedding reconstruction) is followed by supervised fine-tuning to predict per-node toggles. The authors report near-perfect PR-AUC (0.99) across 12 out-of-order CPU designs and 3 workloads, a 7.6x runtime speedup over the Synopsys PTPX tool, and integration with the ATLAS power model (LEAP-Power) to achieve 4.55% MAPE for per-cycle layout power. The paper claims this is the first approach to accurately predict per-cycle toggle propagation and to enable fast, transferable, early layout power analysis.","tokens_in":12125,"tokens_out":3464,"duration_ms":37375,"significance":"If the central claims hold, the contribution is significant: a linear-complexity graph transformer with a causal attention mechanism designed for directed netlists, combined with self-supervised pre-training, would address a real bottleneck in per-cycle power analysis. The evaluation uses realistic large-scale out-of-order CPU designs and compares against a commercial EDA tool, which strengthens practical relevance. The integration with ATLAS demonstrates a concrete downstream use case. However, the cross-design generalization claim, which is a central selling point, depends critically on the pre-training data split, and the paper currently does not specify it. The reported near-perfect PR-AUC values also lack any measure of variance, making it difficult to assess robustness. The architecture and pre-training ideas are novel and worth pursuing, but the current experimental validation is incomplete.","major_comments":[{"comment":"The pre-training data split is not specified. Section 5.1 describes the pre-training tasks but does not state which designs or cycles are used. Section 6.2 defines a 2-fold fine-tuning split, but if pre-training uses all 12 designs (including those later assigned to the test fold), then for each fold the test designs' netlists, per-cycle output pin values (Task #1), and static switching characteristics have already been observed during pre-training. Since the Value_MLP is frozen and its predictions are used as an input feature during fine-tuning (§5.2), the model can effectively access test-design behavior, undermining the cross-design generalization claim. Please specify the pre-training split; if it includes test designs, re-run the experiments with pre-training restricted to the fine-tuning training fold and report results for fully held-out designs.","section":"§5.1 and §6.2"},{"comment":"All PR-AUC and ROC-AUC values are reported as single numbers (e.g., 0.99, 1.00) with no variance over random seeds or multiple runs. Given the class imbalance (3-10% positive samples) and the small number of designs (12), the absence of error bars makes it impossible to assess statistical significance or the stability of the claimed 0.99 PR-AUC. Please report mean and standard deviation over at least five seeds, and state the number of seeds used.","section":"Table 2, §6.2"},{"comment":"The ablation that removes toggle-related features and observes a PR-AUC drop to 0.12 is expected and confirms the model relies on register toggles as initial conditions. However, this ablation does not address the core generalization question: whether the model can predict toggles for designs whose structure and behavior were never seen in either pre-training or fine-tuning. A proper cross-design evaluation must exclude entire designs from both stages; the current 2-fold scheme only excludes from fine-tuning but potentially not from pre-training.","section":"§6.5, Figure 4"}],"minor_comments":[{"comment":"The title contains a typo: 'Sel f-Supervised' should be 'Self-Supervised'. The abstract is otherwise clear.","section":"Title and abstract"},{"comment":"The sentence 'while its acceleration over Grannite (9.3×) is slightly lower' is misleading. Grannite is 9.3× faster than PTPX, not 'acceleration over Grannite'. Please rephrase.","section":"§6.3, Table 3"},{"comment":"The notation in Eq. (2) is dense. It would help to define the dimensions of Q, K, V and the summation indices explicitly, and to state that the sums in Eq. (3) run over all nodes at all depths before d, not just depth d-1.","section":"§4.2, Eq. (2)-(4)"},{"comment":"The paper does not mention the total number of cycles per workload beyond '300-cycle segments'. Is this the full workload length or a subsample? Please clarify whether the 300 cycles are consecutive and whether multiple segments per design were used.","section":"§6.1"},{"comment":"The description of the masked functional embedding reconstruction (Task #3) does not specify the masking ratio. Please state it, along with all pre-training hyperparameters (e.g., alpha coefficients, learning rate, batch size).","section":"§5.1"}],"recommendation":"major_revision","confidential_remarks":"The pre-training leakage concern is the most serious issue. If pre-training indeed uses all designs, the near-perfect PR-AUC could be an artifact of the model having seen the test designs' per-cycle output values during the value-prediction task. The authors must clarify the split and, if necessary, re-run the experiments. This is fixable within the scope of the paper, hence major_revision rather than reject. I also note the paper does not release code or data, which limits reproducibility, but that is not a blocker for the current decision."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Bottom line: this is the first paper I've seen that seriously targets per-cycle toggle propagation, and the architecture is a sensible adaptation of linear attention to the depth direction of a netlist. But the evaluation has a hole the authors haven't acknowledged. The pre-training section (5.1) never says which designs are used for the self-supervised tasks, and the 2-fold validation in Section 6.2 only defines the split for fine-tuning. If pre-training runs on all 12 designs, then for each fold the model has already seen the test designs' netlists and their per-cycle output pin values during task L#1. When you have a frozen Value_MLP that predicts those values and is then fed into the toggle classifier, near-perfect PR-AUC could simply mean the model memorized the test designs, not that it learned toggle propagation. This doesn't have to be a fatal problem, but the paper doesn't rule it out.\n\nWhat's genuinely good: the task itself is worth doing; prior work (Grannite, DeepSeq) only predicted average toggle rates. The depth-wise linear-causal attention is a clean way to respect directionality, and the paper is honest that it's a single attention layer. Pre-training with value prediction, static switching regression, and masked functional embedding is standard but applied here to a new domain. The evaluation on 12 out-of-order CPUs is more realistic than most ML-EDA papers. The ablations are informative: removing register toggle features collapses PR-AUC to 0.12, which shows the model is actually using the propagation source.\n\nSofter spots: no variance over seeds, which makes the 0.99 point estimates hard to judge; the Grannite baseline is not a real comparison since it wasn't designed for per-cycle toggles; only 12 designs, all out-of-order CPUs, so generalization to other microarchitectures is untested; power results are only for Setting 1.\n\nVerdict: the paper deserves a serious referee. The central claim of transferable per-cycle toggle propagation is plausible but not established. I'd want the authors to state the pre-training data split, rerun with pre-training restricted to the training fold if needed, and report seed variance. If that confirms the numbers, this is an accept; if not, the cross-design claim falls.\n\nRecommendation: send it out, with a request to address the split explicitly.","headline":"First serious per-cycle toggle propagation model, but unspecified pre-training split could invalidate the cross-design claim.","tokens_in":12533,"tokens_out":4389,"would_cite":false,"duration_ms":45308,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"LEAP sets out to prove that per-cycle toggle propagation through combinational logic can be learned by a linear-complexity graph transformer, replacing the slowest step in layout power analysis.","keywords":["per-cycle toggle propagation","graph transformer","linear-causal attention","self-supervised pre-training","layout power estimation","netlist analysis","VLSI power","transfer learning"],"falsifier":"Run a single experiment: train on designs D1–D8 and test exclusively on designs D9–D12 (design IDs never seen during training) across all three workloads, and report per-cycle PR-AUC. If PR-AUC drops below 0.9 while the same model still hits 0.99 on seen-design workloads, the cross-design claim is falsified and the true contribution is cross-workload generalization within a design family.","tokens_in":11698,"feed_emoji":"⚡","tokens_out":4953,"duration_ms":52013,"temperature":0.7,"pith_summary":"LEAP claims that per-cycle toggle propagation—the step that extends register activity through combinational logic in a netlist—can be replaced by a learned model without losing accuracy. The authors build a graph transformer whose attention is causal in topological depth, so each gate only sees signals from earlier logic stages, mirroring how toggles actually travel. With self-supervised pre-training on gate function and structure, the model reaches PR-AUC 0.99 for predicting which combinational gates toggle each cycle, 7.6x faster than the commercial EDA tool. Integrated with an existing ML power model, it yields per-cycle layout power from post-synthesis netlists at 4.55% MAPE and 5.3x lower total runtime. If these numbers hold, per-cycle power analysis no longer needs the layout and toggle-propagation bottleneck.","feed_headline":"7.6x speedup for per-cycle power toggles, at 0.99 PR-AUC","feed_subtitle":"A graph transformer skips the slowest EDA step, enabling early per-cycle layout power estimates from synthesis netlists.","key_machinery":"The load-bearing mechanism is LEAP-Former's linear-causal attention: each node's query attends only to keys and values accumulated from all nodes at strictly shallower topological depths, with cumulative sums S and Z updated depth-by-depth, so complexity stays linear rather than quadratic. A parallel Gated GCN branch applies learned gates to neighbor messages, so not all input signals are treated equally, and 128-dimensional text embeddings of each gate's Boolean expression give the model functional knowledge. These pieces let the model propagate register toggle status through combinational logic in one forward pass matching signal direction.","core_discovery":"On the paper's own terms, LEAP is the first per-cycle toggle propagation predictor. The model converts a post-synthesis netlist into a directed graph and uses a single-layer, multi-head attention where each node attends only to nodes at lower topological depths; cumulative sums keep the cost linear in graph size. Three pre-training tasks—predicting per-cycle combinational output values, regressing static switching probabilities, and reconstructing masked functional embeddings—teach the encoder circuit behavior before supervised fine-tuning on toggle labels. On twelve out-of-order CPUs with 240k–1.2M gates, LEAP attains near-perfect PR-AUC (0.99) and ROC-AUC (1.00) on three workloads, runs 7.","pith_inferences":["The reported 2-fold validation trains and tests on the same twelve design IDs—only the workload changes—so the near-perfect PR-AUC does not yet demonstrate transfer to completely new netlist architectures; a holdout of entire design IDs would tighten the claim.","If the functional embeddings capture gate behavior, the pre-training might transfer across standard-cell libraries with only light fine-tuning, since the Boolean expressions are library-agnostic text.","The self-supervised tasks are generic enough that the same LEAP-Former backbone could be repurposed for other per-cycle netlist phenomena, such as glitch rate or critical-path timing, where labels are equally expensive to obtain.","A testable extension: train on a subset of designs and report PR-AUC on completely unseen designs; if it stays near 0.99, the cross-design story is confirmed; if not, the real regime is cross-workload only."],"forward_implications":["If LEAP works as reported, designers can obtain per-cycle toggle information from post-synthesis netlists without running the full RTL-to-layout power simulation, cutting the most expensive step of power analysis.","The 7.6x toggle-propagation speedup and 5.3x end-to-end power-analysis speedup would allow many more power checks per day, making per-cycle power data practical for design-space exploration.","Because inputs are post-synthesis netlists plus RTL simulation, power estimates become available before physical design, enabling early power-driven optimization.","The same learned toggle propagation could feed dynamic timing analysis and glitch-power estimation, not just average-power models.","The linear attention plus gated-GCN structure suggests the approach can scale to larger netlists beyond the 1.2M-gate CPUs tested."],"fun_headline_variants":["LEAP: self-supervised toggle prediction hits 0.99 PR-AUC","7.6x faster per-cycle toggles with near-perfect PR-AUC","First per-cycle toggle predictor: 7.6x speedup, 0.99 PR-AUC","LEAP-Power: 4.55% MAPE, 5.3x runtime gain from netlist","Self-supervised graph transformer accelerates power analysis by 7.6x"],"cache_read_input_tokens":2304,"weakest_assumption_plain":"The load-bearing premise is that toggle behavior in a gate-level netlist is fully determined by local gate function, topology, and register activity, and that a model trained on 12 CPUs with design-overlapping validation generalizes to unseen designs; the 2-fold validation does not hold out whole design IDs, so this transfer is assumed, not yet demonstrated.","fun_headline_variants_meta":{"raw":{"variants":["LEAP: self-supervised toggle prediction hits 0.99 PR-AUC","7.6x faster per-cycle toggles with near-perfect PR-AUC","First per-cycle toggle predictor: 7.6x speedup, 0.99 PR-AUC","LEAP-Power: 4.55% MAPE, 5.3x runtime gain from netlist","Self-supervised graph transformer accelerates power analysis by 7.6x"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000348,"raw_usage":{"total_tokens":1762,"prompt_tokens":790,"completion_tokens":972,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":534,"completion_tokens_details":{"reasoning_tokens":855}},"tokens_in":534,"tokens_out":972,"duration_ms":10014,"temperature":1.0,"reasoning_tokens":855,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-04T17:51:02.779321+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run a single experiment: train on designs D1–D8 and test exclusively on designs D9–D12 (design IDs never seen during training) across all three workloads, and report per-cycle PR-AUC. If PR-AUC drops below 0.9 while the same model still hits 0.99 on seen-design workloads, the cross-design claim is falsified and the true contribution is cross-workload generalization within a design family.","supporting_citations":[],"review_version":1}