{"id":"93f056cd-0352-4c76-92ad-703cc84fba5c","arxiv_id":"2608.05339","paper_version":2,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"PowerScope is the first machine-learning framework that predicts intra-cycle power traces from RTL signals, matching commercial gate-level power estimates with about 9% mean error.","lead":"PowerScope uses machine learning to estimate a chip's power use at several moments inside each clock cycle, working from ordinary RTL simulation traces instead of slow post-layout gate-level simulation. Across five designs it reports about 9% average error versus a commercial power flow while running roughly 80 times faster.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"STA-guided feature selection keys each bin to gates' output windows, but gate input transitions dissipate internal power in earlier bins; for excluded gates the model lacks co-input states, so per-bin features may be missing information the claimed accuracy relies on.","rationale":"Reader's weakest assumption pointed at glitches and path-delay variation; I agree in spirit but the sharper mechanism is input-pin internal power, which is not tied to the gate's output window. Output transitions do stay within STA windows, so 'outside static windows' is not quite right; the gap is that a significant fraction of gate power is dissipated at input transitions that precede the output window. This makes the concern concrete and testable. The paper has real strengths: per-design training, stratified sampling, and downstream TVLA are sensible, and the effect sizes are plausible. If the ablation shows no gain, the method as described may still be correct. Given the unresolved gap and the Table 1 arithmetic mismatch, the reader's CONDITIONAL verdict is appropriate; I would keep it conditional and require the ablation and a corrected aggregate table before acceptance.","tokens_in":11786,"tokens_out":14471,"duration_ms":157967,"concrete_test":"On the AES design (largest, 10 bins), retrain the per-bin LightGBM models with one modification: for each bin b, augment F_b with the toggle/previous-state of all registers in the transitive fan-in of every gate whose input-pin arrival window overlaps b, in addition to the paper's output-window-based PSS. Keep hyperparameters and training data identical, and compare per-bin MAPE/MedAPE for bins b0-b2 against Table 1. If early-bin error improves by more than about 2 percentage points, the output-window-only selection is dropping information needed for the claimed accuracy. A complementary microbenchmark: build a 2-input AND with input A toggling at 100 ps, input B constant 0 but driven by a register whose value varies; confirm whether the current feature set predicts the 100-ps-bin internal power variation at all.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The load-bearing step is Algorithm 1's STA-guided feature selection (Sec. 4.1.2). A gate is added to bin b's potential switching subset only if the gate's output STA window [t_min, t_max] overlaps b; the bin's features are then the toggle and previous-cycle state of that gate's fan-in registers. This conflates the temporal location of a gate's power dissipation with the gate's output transition. In standard-cell power models, a gate's input-pin internal power (short-circuit and internal-node charge) is triggered by the input transition at the input-arrival time, which can precede the gate's output transition by the gate delay. Thus a gate whose output window lies in a later bin (or whose output never toggles, e.g., an AND with a controlling 0) can still dissipate internal power in an early bin, but it is absent from that bin's PSS. The missing information is more than the input's own toggle: the amount of internal power depends on the states of the gate's other inputs, and those other inputs' driving gates are also absent from the early bin's feature set. The model therefore cannot distinguish cycles that differ only in those co-input states. This is a completeness gap in the feature construction, not a model-capacity issue, and it affects exactly the early, high-activity bins that contribute most to intra-cycle power. The reported aggregate numbers (Sec. 5.2: 5.88% MedAPE, 9.05% MAPE) also do not follow from Table 1 under the stated 'average across designs' arithmetic, but the feature-selection gap is the deeper threat to the central claim.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"PowerScope proposes a per-design machine-learning flow for intra-cycle (bin-level) power estimation from RTL register traces. For each of B temporal bins, static timing analysis selects gates whose output switching windows overlap the bin, traces their fan-in registers, and uses per-cycle toggle and previous-state features to train a LightGBM model against PrimeTime PX post-layout power labels. Inference requires only RTL simulation, bypassing post-layout gate-level simulation and power analysis. The paper reports 5.88% median and 9.05% mean absolute percentage error relative to PrimeTime PX across five designs, a roughly 80x speedup, and a TVLA side-channel case study on an OpenTitan AES core.","tokens_in":12132,"tokens_out":7343,"duration_ms":78246,"significance":"If the reported accuracy holds, PowerScope is a useful step: it extends ML-based power estimation from average or per-cycle granularity to intra-cycle granularity, which matters for PDN design, droop analysis, and pre-silicon side-channel evaluation. The method is not circular: labels come from a commercial signoff tool, features come from RTL simulation, and the STA-based feature selection is independent of the power labels. The experimental protocol is clearly described and compares against a commercial post-layout flow, and the downstream TVLA validation is a constructive addition. However, the evidence base is narrow (five designs, no confidence intervals, no released artifacts), the headline accuracy numbers do not follow from the table as printed, and there is a conceptual gap in the STA-guided feature selection that needs quantitative justification. These issues are fixable, but they affect the strength of the central claim.","major_comments":[{"comment":"The bin-membership criterion in Algorithm 1 assigns a gate to a bin based on the gate's output switching window, but standard-cell power models dissipate input-pin internal power at the input arrival time, which can precede the output transition by the gate delay. A gate whose output window lies in a later bin, or whose output never toggles because of a controlling input, can therefore dissipate internal power in an earlier bin while being absent from that bin's potential switching subset. The model also lacks the states of the gate's other inputs, so it cannot distinguish cycles that differ only in those co-input states. This is a completeness gap in the feature construction, not a model-capacity issue, and it affects exactly the early, high-activity bins. Please quantify the fraction of per-bin energy attributable to such excluded gates, or extend the PSS to include gates whose input windows overlap each bin, or otherwise show empirically that the omitted component is negligible.","section":"Section 4.1.2 / Algorithm 1"},{"comment":"The headline claim of 'average MedAPE of 5.88% and average MAPE of 9.05%' is not reproduced by an unweighted average of the five per-design averages in Table 1, which gives 7.37% MedAPE and 10.98% MAPE. If a weighted average or a pooled-per-bin calculation is intended, the weighting must be stated explicitly; otherwise the numbers should be corrected. Similarly, the '~80x' speedup is consistent with the geometric mean of the five speedups in Figure 7 (the arithmetic mean is 120.7x), so the averaging convention should be stated wherever an aggregate speedup is reported.","section":"Section 5.2 / Table 1 / abstract"},{"comment":"The empirical evaluation is under-specified for the strength of the central claim. The manuscript does not state which specific workloads were used for testing, how many cycles each test workload contains, how the test workloads differ from the training micro-benchmarks, or any per-design or per-bin variance, confidence intervals, or repeated-run statistics. With only five designs and no released code, models, or data, the 5.88%/9.05% claim is not reproducible as presented. Please report the test workload details, per-design error bars, and consider releasing artifacts to support the quantitative claims.","section":"Section 5.1 / Section 5.2"}],"minor_comments":[{"comment":"The caption of Figure 1 states '~80x avg. speedup' without defining the average; since the per-design speedups range from 15.2x to 248.4x, please state explicitly whether the aggregate is an arithmetic or geometric mean.","section":"Figure 1 / Figure 7"},{"comment":"The description of stratified subsampling says that when a stratum has fewer cycles than requested, 'the shortfall is redistributed proportionally to denser strata'; the exact rounding and redistribution rule should be specified for reproducibility.","section":"Section 4.1.1"},{"comment":"The runtime comparison should state whether the reported PowerScope inference time includes RTL simulation plus model inference for the same 100k-cycle workload, and what parallelism assumptions are used, given that the server in Section 5.1 has 512 cores.","section":"Section 5.2.4"},{"comment":"Since the features are register toggles and states, Table 2 should also report the total number of registers in each design, not only the total number of RTL signals, to make the 'selected proxies' fractions more interpretable.","section":"Table 2"},{"comment":"The statement that the PowerScope-based TVLA t-statistic deviates by 'only 11.7% on average' needs a precise definition of the relative error; on a log-scale plot, small t-statistics can dominate such an average, so a per-bin table or an alternative error measure would be more informative.","section":"Section 6 / Figure 8"}],"recommendation":"major_revision","confidential_remarks":"The core idea is promising and the evaluation is transparent enough that the issues can be addressed in revision. I would not reject the paper on the feature-selection concern alone, because the empirical results may still hold on the tested designs, but the authors need to either close the temporal-membership gap or provide evidence that it is negligible. The arithmetic mismatch in the headline numbers and the missing test-workload specification are also important for a claims-heavy empirical paper. Given the strong reproducibility expectations for ML-based EDA work, I would encourage the editor to require, at minimum, a precise statement of the averaging conventions and per-design test details; artifact release would substantially strengthen the paper."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"I've read PowerScope and the stress-test note. My take: this is a real first, and the core idea is better than the reader's report makes it sound. The paper's main contribution is per-bin power modeling at intra-cycle granularity, which prior ML work largely ignores. The STA-guided feature selection is a nice, cheap way to pick bin-specific register features, and the stratified subsampling for imbalanced power distributions is sensible. The TVLA downstream validation is a good check. On the whole, the experimental setup is fair: held-out workloads, comparison against commercial PrimeTime PX, and a realistic speedup measurement.\n\nThe stress-test concern about internal power is legitimate and worth taking seriously. Algorithm 1 keys each bin to gates whose output switching window overlaps that bin. But gate internal power is triggered by input transitions, which can occur earlier than the output transition and can affect bins where the gate's output window does not fall. For gates excluded from a bin's PSS, the model does not see the co-input states, so cycles differing only in those states are indistinguishable. This is a completeness gap in the feature construction, not just a modeling issue. It could be a real source of error in the early, high-activity bins. However, I don't think it's fatal on its face: the reported accuracy suggests the captured register toggles carry most of the signal, and the paper's bin-0 proxy counts are high. The right response is to ask the authors to quantify the contribution of input-side internal power for excluded gates, or to add a feature set that includes all gates' input transitions in a window.\n\nThe more immediately concrete problem is the numbers. The abstract and Section 5.2 report 5.88% MedAPE and 9.05% MAPE 'across designs,' but the simple average of Table 1's per-design averages is 7.37% and 10.98%. The paper never explains the weighting. That's the kind of thing a referee will catch immediately, and it undermines trust in the headline. Also missing: confidence intervals, a detailed description of the test workloads, and any released code or artifacts.\n\nThe comparison to ML-Power is under-specified; adapting it with a 5-point MCP penalty search per bin may not be the strongest baseline, but it's a reasonable start. The benchmark suite is small and mostly arithmetic, but it covers combinational, multi-cycle, and pipelined designs, so it's okay for a first paper.\n\nOverall, PowerScope deserves a serious referee. I'd send it out. The main revision requests would be: clarify the averaging, add error bars and workload details, release at least the feature-selection code, and discuss or mitigate the input-side internal power gap. If those are addressed, this is a solid subfield-level contribution.","headline":"A genuinely new intra-cycle power estimation approach with a clever STA-guided feature selection, but the headline numbers don't add up and the feature set may miss input-side internal power.","tokens_in":12691,"tokens_out":3698,"would_cite":true,"duration_ms":36586,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"PowerScope claims to be the first ML framework that estimates post-layout intra-cycle power directly from RTL simulation traces, achieving 5.88% median and 9% mean absolute percentage error at roughly 80x speedup.","keywords":["Power estimation","Intra-cycle power","Machine learning","RTL simulation","STA-guided feature selection","LightGBM","TVLA","Side-channel analysis"],"falsifier":"Run PowerScope on a set of workloads for a design with known unbalanced path delays (e.g., a ripple-carry adder or a multiplier with a slow carry chain), then compare its per-bin predictions against post-layout PrimeTime PX power at a fine sampling period; if the median absolute error rises substantially above the reported 5.88% and the extra error concentrates in bins where glitches occur or where actual switching falls outside the STA-derived windows, the overlap-based feature assumption is the cause.","tokens_in":11583,"feed_emoji":"⚡","tokens_out":4431,"duration_ms":38510,"temperature":0.7,"pith_summary":"PowerScope claims to be the first machine-learning framework that estimates post-layout intra-cycle power—power at multiple time bins within each clock cycle—directly from RTL simulation traces. It argues that the expensive post-layout gate-level simulation and power analysis step only needs to be run once per design, during training, and that inference can then run entirely at the RTL level. Across five designs, PowerScope reports 5.88% median and 9% mean absolute percentage error against a commercial post-layout flow (Synopsys PrimeTime PX), at roughly 80x end-to-end speedup. It also reports that its bin-level power traces support TVLA side-channel leakage assessment with only 11.7% average deviation from the ground-truth t-statistics.","feed_headline":"PowerScope: 80x faster intra-cycle power from RTL traces","feed_subtitle":"ML predicts per-bin power from register toggles; TVLA side-channel screening matches commercial flow within 11.7%.","key_machinery":"The load-bearing mechanism is STA-guided, bin-specific feature selection. Static timing analysis assigns each gate a switching window $[t_{\\min}(g), t_{\\max}(g)]$ from the SDF file; a gate is considered to contribute to a bin's dynamic power only if that window overlaps the bin. Tracing each such gate's fan-in back to registers yields a per-bin register set, and from cycle-level RTL simulation each selected register contributes two binary features: whether it toggles in the current cycle and its state in the previous cycle. A per-bin LightGBM model then maps these features to that bin's power, trained on labels from post-layout PrimeTime PX analysis with quantile-based stratified subsampling to cover rare high-activity cycles in bimodal bins.","core_discovery":"PowerScope's central claim is that intra-cycle power, sampled into $B$ uniform time bins per clock cycle, can be predicted per bin by a small design-specific set of RTL signals: the toggle activity and previous-cycle state of the registers in the transitive fan-in of gates whose static-timing switching windows overlap that bin. Because those \"potential switching subsets\" are derived from the netlist and SDF file in a single pass, and because one LightGBM model is trained per bin with stratified subsampling to handle skewed power distributions, inference needs only RTL simulation. The paper reports that this yields per-bin power estimates whose median absolute error is 5.88% and mean absolute error 9% relative to post-layout gate-level power analysis, and that the predicted traces rank power samples well (Spearman $\\rho$ up to 0.96 for FMA), which is what TVLA-style side-channel screening needs.","pith_inferences":["The STA-window overlap criterion is a static proxy; input-dependent path delays and glitch energy can spill switching activity outside the computed windows or across bins. A stress test on a heavily glitching combinational design (e.g., a multiplier or carry-save adder) would reveal whether the reported 9% MAPE holds when the window assumption is violated.","Because the features are only binary register toggles and states, PowerScope's accuracy likely degrades for designs where combinational depth is large and intra-cycle power depends on the exact arrival time distribution rather than just which registers fired; extending features to cycle-relative timing or glitch counts might extend the method to finer $T_s$.","The downstream TVLA validation suggests a practical rule of thumb: ML-based intra-cycle power is good enough for rank-based side-channel screening (TVLA), but may not yet be sufficient for absolute-value tasks like IR-droop signoff, where the paper itself notes errors propagate into voltage droop and timing analysis."],"forward_implications":["Pre-silicon power side-channel evaluation can be run directly from RTL simulation, since PowerScope's bin-level traces track PrimeTime PX TVLA t-statistics within 11.7% average deviation.","Feature selection cost no longer scales with the number of bins: the STA-guided pass runs once over netlist and SDF, giving an average 12.5x faster proxy selection than MCP-based methods like ML-Power.","Finer sampling periods (smaller $T_s$) tend to raise error because bins near the switching edge become bimodal; coarser bins pool transitions and reduce MAPE, so users can trade temporal resolution against accuracy.","Stratified subsampling improves accuracy mainly for designs with bimodal per-bin power distributions (e.g., FMA and AES), where random sampling under-covers lower-probability high-activity cycles."],"supporting_citations":[{"why":"APOLLO, the prior per-cycle ML power estimation framework that PowerScope extends to intra-cycle granularity.","marker":"[33]"},{"why":"ML-Power, the MCP-based proxy selection baseline compared for feature-selection speedup.","marker":"[22]"},{"why":"GRANNITE, a neural-network power estimator representing approaches that require larger training datasets.","marker":"[37]"},{"why":"LightGBM, the gradient-boosting tree model used as the per-bin predictor.","marker":"[13]"},{"why":"PrimeTime PX, the commercial post-layout power analysis tool that supplies ground-truth labels.","marker":"[27]"},{"why":"TVLA methodology (Goodwill et al.) used to validate downstream side-channel leakage assessment.","marker":"[12]"},{"why":"OpenTitan, the source of the AES cipher core design used in the experiments.","marker":"[19]"}],"fun_headline_variants":["PowerScope: ML intra-cycle power, 80x faster from RTL","First ML intra-cycle power estimator: 80x faster","5.88% error intra-cycle power, 80x faster via ML","PowerScope: per-bin power from RTL, 80x speedup","ML predicts sub-clock power at 5.88% error, 80x faster"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"PowerScope assumes that a gate's contribution to a bin's power is determined by whether its static timing window overlaps the bin, and that the bin's dynamic power can be predicted from the toggle and previous-cycle state of the gate's fan-in registers, which ignores glitch energy and input-dependent delay variation.","fun_headline_variants_meta":{"raw":{"variants":["PowerScope: ML intra-cycle power, 80x faster from RTL","First ML intra-cycle power estimator: 80x faster","5.88% error intra-cycle power, 80x faster via ML","PowerScope: per-bin power from RTL, 80x speedup","ML predicts sub-clock power at 5.88% error, 80x faster"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.00022,"raw_usage":{"total_tokens":1432,"prompt_tokens":918,"completion_tokens":514,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":534,"completion_tokens_details":{"reasoning_tokens":415}},"tokens_in":534,"tokens_out":514,"duration_ms":4825,"temperature":1.0,"reasoning_tokens":415,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-10T04:25:41.024480+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run PowerScope on a set of workloads for a design with known unbalanced path delays (e.g., a ripple-carry adder or a multiplier with a slow carry chain), then compare its per-bin predictions against post-layout PrimeTime PX power at a fine sampling period; if the median absolute error rises substantially above the reported 5.88% and the extra error concentrates in bins where glitches occur or where actual switching falls outside the STA-derived windows, the overlap-based feature assumption is the cause.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"LightGBM, the gradient-boosting tree model used as the per-bin predictor."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"OpenTitan, the source of the AES cipher core design used in the experiments."}],"review_version":2}