{"id":"4a90fc7f-ec41-4421-a1be-e5616527265c","arxiv_id":"2608.06072","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":1,"one_line_summary":"On heavy-hex hardware, routing imbalance in symmetric quantum circuits is an assignment choice whenever the patch shape permits, and for four-part rings a simple closed-form assignment achieves zero spread.","lead":"This paper shows that for quantum circuits with cyclic symmetry, the uneven routing overhead across identical roles is caused by how logical roles are assigned to physical qubits, not by chip geometry alone. It proves that on a 57-qubit heavy-hex chip, most patches can host a balanced assignment at no extra depth, and that this balance can cut measured symmetry-breaking by over 90% in simulation.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Exhaustive counts are exact only for one unspecified Qiskit 2.5.1 routing invocation; no code, seeds, or independent cost model are supplied to show the free-lunch verdicts are robust.","rationale":"The paper's core structural insight is plausible and the two-level framing (shape decides whether balance is possible; assignment decides actual imbalance on patches that admit it) is coherent. The exhaustive search over all connected patches is a sound method for the stated chip sizes, and the explicit scoping limitations are honestly stated. The simulation results are reported with confidence intervals and a paired test, and the channel-resolved ablation is a reasonable attempt to separate routing spread from substrate heterogeneity. However, the proofs are not parameter-free or machine-checked: they depend on Qiskit's routing-cost output, and the paper even notes version-to-version variation. Without releasing the search code, the exact transpiler seeds, and a check against an independent cost model, a reader cannot tell whether the striking counts (108/124 free lunches, zero free lunches for C6, zero for S4) are properties of the routing problem or artifacts of one compiler invocation. This does not justify rejection: the concern is about robustness and reproducibility, not about an identified internal inconsistency. The recommended verdict is therefore unchanged from the reader's CONDITIONAL: accept only if the authors supply artifacts and the proposed robustness check passes; otherwise the strong 'proof' language should be softened to 'verified under Qiskit 2.5.1 with default settings.'","tokens_in":7326,"tokens_out":11028,"duration_ms":103089,"concrete_test":"Re-run the exhaustive search for all 124 C4 and 62 C6 patches with Qiskit 2.5.1 at optimization levels 0, 2, and 3 and with at least 50 transpiler seeds, and also with an independent deterministic router (e.g., greedy SWAP insertion on shortest paths). Record for each assignment the full vector of per-role gate counts. If any free-lunch classification, or the balanced/concentrated equal-depth pairing, changes across seeds or routers, the paper must qualify its claims as compiler-specific; if all classifications are stable, the conditional acceptance can be lifted.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim is conditional on Qiskit 2.5.1's heuristic routing pass as the definition of assignment cost. In Sec. V the exhaustive verdicts ('free lunch' and 'no free lunch') are obtained by transpiling every assignment and reading off two-qubit-gate counts; Table I itself reports that older Qiskit versions gave a different worst-case spread (12 vs 9), so the cost function is not stable across compiler versions. If the router is seed-dependent or not equivariant under the ring's rotations, a profile that scores zero spread once might not do so in other runs, and a patch counted as 'no free lunch' might admit a cheaper assignment under a different router. Since no code, seeds, or independent cost model are supplied, the 108/124 and 0/62 counts, and the 'at no extra depth' comparison, are established only with respect to one unspecified invocation of one compiler release. This is the load-bearing assumption because every headline number, including the 'impossibility' results, is a statement about those routing-cost counts.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper studies how compiling cyclic-symmetric circuits onto heavy-hex hardware induces routing imbalance. It distinguishes two levels: whether a patch of qubits can host a balanced assignment (shape-dependent) and whether the actual assignment realizes it (compiler choice). The authors characterize four-qubit rings: on path-shaped patches the assignment (1,2,1,2) gives zero spread of per-role two-qubit gate counts at no extra depth, while star-shaped patches fail. For six-qubit rings, no compact patch gives a free balanced assignment; for fully connected four-part symmetry, balance is claimed to be impossible at any depth. Simulations with realistic noise claim a 92.7% reduction in raw symmetry-breaking and 87.0% in a decoherence-corrected metric relative to the worst-case concentrated assignment, with a 10.8% upper bound on the substrate-heterogeneity contribution. A closed-form balancing rule for the four-part ring is given. The paper explicitly scopes the six-part no-free-lunch result to a 19-qubit chip.","tokens_in":7574,"tokens_out":7233,"duration_ms":62645,"significance":"If the exhaustive verdicts are correct, the paper makes a useful conceptual point: routing imbalance for cyclic blocks is a compiler assignment choice whenever the patch geometry permits, and generic depth-minimizing passes do not reliably fix it. The exhaustive enumeration over all connected patches of the stated sizes is a strength, as is the explicit separation of 'exists at extra depth' versus 'free lunch' and the use of paired statistics with confidence intervals. The paper also honestly lists its limitations in the Discussion. However, the headline numbers are tied to a single compiler release, and the proof methodology for the 'at any depth' claims is not fully described, so the significance is conditional on those being clarified.","major_comments":[{"comment":"The abstract states that 'Through exhaustive search on a 57-qubit “heavy-hex” lattice, we prove these topological constraints exactly. For a six-part ring, cost-free balance is impossible on compact patches.' However, Section V, under 'Plain statement of scope,' says the six-part no-free-lunch result is proved on the smaller 19-qubit chip (d=3), with extension to the 57-qubit layout explicitly left as a scoping limitation. As written, the abstract overstates the support for the six-part claim. Please either prove the six-part result on the full 57-qubit lattice (the paper estimates this as a half-hour computation) or qualify the abstract to match the stated scope.","section":"Abstract and Section V"},{"comment":"The 'Exists at any depth' verdicts are not backed by a described search over depth. The text explains that for each patch 'we generate every assignment up to the ring’s own rotations and reversals' and transpiles them; it does not describe how arbitrary extra SWAP insertions (that is, larger depths) are searched or bounded. The S4 conclusion that no patch balances at any depth is therefore stronger than the presented finite enumeration supports. The intuitive argument about four qubits not being at equal distance addresses direct interaction distances, not SWAP-sequence costs, which can in principle be modified by adding gates. Please specify the exact search space for the 'at any depth' verdicts, or provide a proof that suffices.","section":"Section V, Table II"},{"comment":"The free-lunch classifications are defined by two-qubit-gate counts from a single, unspecified invocation of Qiskit 2.5.1's routing pass. Table I itself reports that an older compiler version changed the worst-case spread from 12.0 to 9.0, showing that the cost model is version-dependent. No code, seeds, or independent routing-cost model are provided. Since the central exhaustive counts (108/124, 0/62, and the 27 vs 13 gate estimates) are statements about these counts, their robustness is not established. The sentence 'the exact number depends on the routing algorithm, but the effect does not' is an assertion; please either ship the search code with fixed seeds, test with an independent cost model, or explicitly delimit all headline claims as 'with respect to Qiskit 2.5.1.'","section":"Section V, Tables I and II"},{"comment":"The claim that substrate error heterogeneity 'accounts for at most 10.8% of the matched-mean baseline effect' is not assessable because the channel-resolved ablation is not described: there is no specification of how error rates were varied, how the matched-mean baseline is defined, or how the 95% confidence bound was computed. This number is used to attribute the simulated effect to routing imbalance rather than qubit-quality variation, so the method needs to be reported in detail.","section":"Section VI"}],"minor_comments":[{"comment":"The expectation operator E_x and the variable x are not defined; clarify that the expectation is over measurement shots.","section":"Section IV, Eq. (5)"},{"comment":"The resolution guard |\\bar\\mu| > 3\\sigma_{\\bar\\mu} is never defined; provide the formula for \\sigma_{\\bar\\mu}.","section":"Section IV"},{"comment":"The C6 row entry 'yes (d=5) no' is ambiguous; the column structure should make clear what the parenthetical refers to (chip size versus depth).","section":"Table II"},{"comment":"The axis label 'orbit routing asymmetry' is unexplained; please define 'orbit' in the caption.","section":"Figure 1"}],"recommendation":"major_revision","confidential_remarks":"The paper is within the journal's scope. Given that the exhaustive-search and simulation results are central, I would ask the authors to provide code and data or a detailed reproducible protocol; without these, the 'proof' claims are hard to audit. The abstract should also be reconciled with the scoping limitation for the six-part ring."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Good to talk. I've read the Punch paper and I think it's worth taking seriously, though the strongest claims need a caveat. The genuinely new thing is the classification: on heavy-hex, a four-part ring can be balanced for free on any path-shaped patch (108 out of 124), while the 16 star-shaped patches fail, and the six-part ring has no free lunch on compact patches. That's a concrete, non-obvious result about how assignment, not just topology, sets routing imbalance. The closed-form rule for C4 is clean and useful, and the duality lemma (rotating input equals relabeling placement) is a neat way to make the mechanism precise.\n\nThe paper does several things well. The exhaustive search is the right tool for this question, and the authors are honest about scope: they flag the 19-qubit versus 57-qubit gap, the simulated error model, and that the rule stops at four. The simulation is also sensibly designed: balanced versus concentrated on the same path, same qubits, same average gate count, so the difference is attributable to the spread of routing cost. The statistical reporting is solid, with CIs and a paired test.\n\nNow the soft spot, and it's the one the stress-test note puts its finger on. The \"proof\" of the counts is conditional on Qiskit 2.5.1's routing cost model. Table I itself reports a different worst-case spread for older versions (12 vs 9), so the exact numbers are version-specific. The balanced profile (1,2,1,2) might be zero-spread in one router but not another, and the \"no free lunch\" verdicts could change if a different router assigns costs differently. The paper asserts the effect doesn't depend on the routing algorithm, but that's a plausible claim, not a proven one. Because no code, seeds, or independent cost model are given, I can't check whether the 108/124 or the 0/62 are robust. That's a real reproducibility gap, not a nitpick.\n\nThe six-part result being only on the 19-qubit chip is minor since the paper labels it as a scoping limitation. The simulation is fine as a controlled comparison, though it's not live-device evidence.\n\nOverall, the mechanism and the topological classification are valuable to the compiler community, and the paper deserves a serious referee. My recommendation: send it to review, but with a strong request for shipped code and a robustness check across router versions (or at least a cleaner statement that the counts are router-dependent). I'd bring it to reading group; it will spark a good discussion about what \"proof\" means when the cost model is a heuristic.","headline":"Useful two-level picture of routing imbalance, with a genuinely new topological classification, but the 'proof' is pinned to one Qiskit version and no artifacts are shipped.","tokens_in":8022,"tokens_out":2475,"would_cite":true,"duration_ms":23248,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":["81P68"],"pacs":[],"model":"deepseek-v4-flash","headline":"For cyclic circuits on heavy-hex, routing imbalance is an assignment choice wherever the patch shape allows a balanced assignment.","keywords":["quantum circuit compilation","routing imbalance","symmetry-aware assignment","heavy-hex lattice","equivariant quantum circuits","SWAP routing","topological constraints","exhaustive search"],"falsifier":"Re-run the exhaustive assignment search with a different compiler's routing cost model over all 124 connected four-qubit patches: if any path-shaped patch shows a zero-spread assignment that costs more depth than its cheapest assignment, or any star-shaped patch admits a zero-spread assignment at any depth, the paper's central dichotomy is wrong. A live-device comparison with roughly uniform error rates would also settle it: the balanced assignment should reproduce the reported roughly 93 percent reduction in per-role spread; if it does not, the assignment-dependence claim fails.","tokens_in":7141,"feed_emoji":"⚛️","tokens_out":8260,"duration_ms":79555,"temperature":0.7,"pith_summary":"The paper claims that, for cyclic symmetric circuits compiled onto a heavy-hex quantum chip, routing imbalance is not fixed by hardware topology. Whether any balanced assignment exists is fixed by the shape of the qubit patch, but whenever balance is possible, the compiler's logical-to-physical assignment decides how uneven the routing cost is, and a balanced assignment can spread the cost perfectly evenly at no extra circuit depth. The claim is established by exhaustive search over all connected patches: for a four-part ring, 108 of 124 connected patches admit a cost-free balanced assignment, and the 16 failures are exactly star-shaped patches; for a six-part ring no compact patch does it for free; for a fully connected four-part symmetry no patch does it at any depth. Under realistic simulated noise, balanced assignments reduce measured symmetry-breaking by about 93 percent relative to the worst-case concentrated assignment, with most of that reduction coming from the routing spread itself rather than from uneven qubit error rates. A sympathetic reader would care because it turns an apparent hardware limitation into a compiler optimization that costs nothing in depth.","feed_headline":"Same-depth qubit assignment cuts symmetry-breaking ~93 percent","feed_subtitle":"A balanced placement spreads routing cost evenly at no extra depth on 108 of 124 heavy-hex patches.","key_machinery":"The load-bearing devices are the ring-distance profile and the duality lemma. The profile is the list of graph distances between consecutive logical roles on the physical patch, e.g. $(1,2,1,2)$ for a balanced four-part ring on a path; routing cost and its spread are read off this profile. The duality lemma equates measuring a rotated input on a fixed placement with measuring the unrotated input on a relabelled placement, turning symmetry-breaking into a property of the assignment. The exhaustive search enumerates every connected patch and every assignment up to rotation and reversal, using a graph-hash fingerprint only to count patch shapes, so each negative verdict is an impossibility proof. The closed-form balancing rule for the four-part ring assigns $\\pi(0)=p_0$, $\\pi(1)=p_1$, $\\pi(2)=p_3$, $\\pi(3)=p_2$ on a path and yields zero spread at the patch's cheapest depth.","core_discovery":"The central discovery is a two-level division of responsibility. For a cyclic symmetry, a ring of logical roles that should be interchangeable, the measured spread in per-role error is a statement about assignment: the paper's duality lemma shows that rotating the input is equivalent to relabelling which physical qubit plays which role, so the symmetry-breaking seen in experiments is literally the unevenness of routing across roles. The paper then proves, by exhaustive search over every connected patch of the 57-qubit heavy-hex lattice, that a patch's shape decides whether a balanced assignment exists and the assignment decides the actual imbalance when one exists. In concrete terms, on every path-shaped four-qubit patch the assignment that places the first two roles in order and swaps the last two yields ring-distance profile $(1,2,1,2)$, zero spread, and the patch's cheapest depth; star-shaped patches cannot host this profile; and fully connected four-part symmetry cannot be balanced on any compact patch at any depth because the sparse chip cannot place four qubits at equal distances.","pith_inferences":["If the patch-shape characterization carries over to other sparse topologies, such as square or triangular lattices, then balanced-assignment capacity becomes a design metric for chip geometry, not just for heavy-hex.","Because the paper isolates the effect from error heterogeneity, one testable extension is to run the balanced-versus-concentrated comparison on chips with deliberately skewed error maps; the claim predicts the roughly 93 percent reduction persists as long as routing-cost spread is the dominant per-role difference.","The six-part no-free-lunch result turns into an optimization problem a symmetry-aware compiler could solve: minimize additional depth subject to zero spread for a six-part ring, with the smaller-chip exhaustive search as a certified baseline.","For multi-block circuits containing many cyclic blocks, assigning each ring independently could create cross-block depth tradeoffs, so a scheduler-level extension is needed."],"forward_implications":["For any cyclic block on a patch that admits balance, a compiler can eliminate routing imbalance for free, so symmetry-aware assignment should be a first-class optimization target rather than an afterthought.","Chip layouts can be compared by a new metric: how many balanced assignments the patch hosts; star-shaped four-qubit patches score zero for a four-part ring.","Benchmarks of cyclic workloads should report the spread of per-role routing cost, because the average gate count is identical for the balanced and concentrated assignments and hides the breaking.","On heavy-hex, a fully connected four-part symmetry cannot be balanced on any compact patch at any depth, so that symmetry class needs different hardware or a different circuit structure.","A six-part ring can be balanced only by paying extra depth, and the paper leaves open the optimization of that depth-for-balance trade."],"supporting_citations":[{"why":"Supplies the prior noise-only account of symmetry breaking that this paper extends to compilation-level assignment effects.","marker":"[4]"},{"why":"Represents layout synthesis that minimizes depth or gate count without tracking per-role routing spread, the baseline the paper argues is insufficient.","marker":"[5]"},{"why":"Another topology-aware optimizer that ignores which physical qubit carries which logical role, providing the comparison target for the paper's claim.","marker":"[6]"},{"why":"Shows low-error qubit selection improves average error, a method that cannot fix cyclic imbalance by itself.","marker":"[7]"},{"why":"Noise-adaptive compiler mapping baseline for error-based qubit selection, which the paper contrasts with role-aware assignment.","marker":"[8]"},{"why":"Variability-aware qubit assignment baseline; the paper's ablation shows error heterogeneity explains at most 10.8 percent of the observed effect.","marker":"[9]"}],"fun_headline_variants":["Patch shape decides if balanced qubit routing is free","Compiler choice, not hardware, drives routing imbalance when geometry allows","Heavy-hex: 108 of 124 patches support cost-free balanced routing","Zero-depth balanced assignment reduces symmetry-breaking by 93%","Symmetry-aware assignment: routing imbalance is a choice when shape permits"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that the routing cost model used by the compiler in the exhaustive search is the ground truth for what an assignment costs; a different compiler or routing algorithm that changed relative assignment costs could shift the free-lunch and no-free-lunch verdicts.","fun_headline_variants_meta":{"raw":{"variants":["Patch shape decides if balanced qubit routing is free","Compiler choice, not hardware, drives routing imbalance when geometry allows","Heavy-hex: 108 of 124 patches support cost-free balanced routing","Zero-depth balanced assignment reduces symmetry-breaking by 93%","Symmetry-aware assignment: routing imbalance is a choice when shape permits"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000962,"raw_usage":{"total_tokens":4160,"prompt_tokens":1074,"completion_tokens":3086,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":690,"completion_tokens_details":{"reasoning_tokens":2998}},"tokens_in":690,"tokens_out":3086,"duration_ms":21963,"temperature":1.0,"reasoning_tokens":2998,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-07T15:28:15.100746+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Re-run the exhaustive assignment search with a different compiler's routing cost model over all 124 connected four-qubit patches: if any path-shaped patch shows a zero-spread assignment that costs more depth than its cheapest assignment, or any star-shaped patch admits a zero-spread assignment at any depth, the paper's central dichotomy is wrong. A live-device comparison with roughly uniform error rates would also settle it: the balanced assignment should reproduce the reported roughly 93 percent reduction in per-role spread; if it does not, the assignment-dependence claim fails.","supporting_citations":[{"cited_title":"Symmetry Breaking in Geomet- ric Quantum Machine Learning in the Presence of Noise,","cited_arxiv_id":null,"evidence_quote":"Supplies the prior noise-only account of symmetry breaking that this paper extends to compilation-level assignment effects."},{"cited_title":"TopGen: Topology-Aware Bottom-Up Generator for Variational Quantum Circuits","cited_arxiv_id":"2210.08190","evidence_quote":"Represents layout synthesis that minimizes depth or gate count without tracking per-role routing spread, the baseline the paper argues is insufficient."},{"cited_title":"Wide Quantum Circuit Optimization with Topology Aware Synthesis,","cited_arxiv_id":null,"evidence_quote":"Another topology-aware optimizer that ignores which physical qubit carries which logical role, providing the comparison target for the paper's claim."},{"cited_title":"Suppressing quantum cir- cuit errors due to system variability,","cited_arxiv_id":null,"evidence_quote":"Shows low-error qubit selection improves average error, a method that cannot fix cyclic imbalance by itself."},{"cited_title":"Noise-Adaptive Compiler Mappings for Noisy Intermediate-Scale Quantum Computers,","cited_arxiv_id":null,"evidence_quote":"Noise-adaptive compiler mapping baseline for error-based qubit selection, which the paper contrasts with role-aware assignment."},{"cited_title":"Not All Qubits Are Created Equal: A Case for Variability-Aware Policies for NISQ-Era Quantum Computers,","cited_arxiv_id":null,"evidence_quote":"Variability-aware qubit assignment baseline; the paper's ablation shows error heterogeneity explains at most 10.8 percent of the observed effect."}],"review_version":1}