{"id":"587a2bf2-1073-4ff0-bdc7-bec10b62f7a0","arxiv_id":"2608.07179","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":5,"one_line_summary":"Aneto predicts a workload's CPI under a new memory system from a single run's CPI, LLC miss rate, and miss penalty, via a cross-workload regression of the blocking factor.","lead":"This paper introduces Aneto, a model that predicts a program's speed under a new memory technology from a single short run on today's hardware, using three standard performance counters. It matters because architects could evaluate HBM, CXL, or faster DDR options per workload without expensive simulation or memory sweeps.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Constant-BF assumption at extrapolated MP is the load-bearing risk; ChampSim can directly measure BF drift at 8x to settle it.","rationale":"The reader's weakest_assumption and my concern coincide: the linear decomposition and BF constancy. I agree with the conditional verdict because the paper has real support — LOO over 100+ workloads, direct ChampSim ground truth, a genuine ARM DDR-to-HBM measurement, and a clear mechanistic model — but the headline extrapolation to 8x is not hardware-validated and the selection filter removes the workloads most likely to violate the assumption. The proposed ChampSim test is decisive because ground truth is available at every simulated latency, so it directly measures the quantity the model assumes rather than inferring it from aggregate CPI error. If the test shows small BF drift, the concern does not land and the paper's claims stand. If it shows large drift, the conditional verdict should harden into a requirement that all reported large-MP errors be labeled model-vs-model and the 'any workload' claim be narrowed to workloads satisfying linearity. I do not see an internal inconsistency or a reason to reject; the missing evidence is the BF drift distribution, which is obtainable from existing simulator data.","tokens_in":21033,"tokens_out":11930,"duration_ms":125876,"concrete_test":"On ChampSim, using all DPC-4 traces without the R2>=0.90 filter, fit BF and CPI0 for each workload in a local window around baseline (1x-2x MP) and again in a local window around 8x (6x-8x MP). Report the distribution of BF_8x - BF_baseline, split by R2>=0.90 vs R2<0.90. If median |BF_8x - BF_baseline| <= the Table 6 LOO |ΔBF| values (0.014-0.063), the constant-BF assumption is supported and the 8x model-vs-model agreement is meaningful; if drift is 2-3x larger, the single-run BF is the wrong coefficient at the target memory and the 8x hardware claim should be downgraded. The R2 split also quantifies how much the retention filter drives the headline accuracy.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Eq. 2 fits BF at a single baseline MP; Eq. 4 extrapolates to 3x/8x by asserting BF_B=BF_A and MPI_B=MPI_A (§3.5). On hardware, DVFS only moves MP to 0.4x-0.7x of baseline (Table 5), so per-workload ground-truth BF is identified from a narrow sub-baseline window. The sole hardware evidence at larger penalty is one ARM DDR-to-HBM experiment at ~3x (12.7% median, 35.9% P90); the 8x results are explicitly model-vs-model (§4.4.2). Further, the R2>=0.90 retention filter removes workloads whose CPI vs MPI*MP relationship is nonlinear, i.e., the very workloads where BF may drift with MP; even among retained workloads, the 19% with high memory fraction and imperfect linearity already show >25% error at 3x (§5.6, Fig. 9). So the central 'single run for any workload' claim is least secure exactly where it must be true: BF constancy at the target memory latency. This is a correctness risk, not a consensus disagreement: the paper discloses the limitation but does not quantify BF drift directly, which is the missing evidence.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes Aneto, a cross-workload regression model that predicts the blocking factor (BF) of a workload from a single native run using three standard performance counters: CPI, LLC misses per instruction (MPI), and miss penalty (MP). The key equations are Eq. (2), logit(BF) = beta0 + beta1 log(MPI*MP) + beta2 log(CPI), and Eq. (4), CPI_B = CPI_A + BF_hat * MPI_A * (MP_B - MP_A). The model is fitted once per platform on a small corpus of reference workloads whose ground-truth BF is obtained from Clapp et al.'s multi-point linear regression, and is then applied to held-out workloads via leave-one-out cross-validation. The evaluation spans five x86 platforms, one ARM server, and three simulator configurations; the headline results are a median 12.7% CPI error on the ARM DDR-to-HBM validation at ~3x penalty, a roughly 2x error reduction relative to PROFET on ChampSim, and median 8x errors of 11.6-18.2% across platforms. The manuscript discloses the constant-BF assumption, the R^2 retention gate, and the model-vs-model nature of the hardware 8x extrapolation.","tokens_in":21226,"tokens_out":12661,"duration_ms":118705,"significance":"If the central claim holds, Aneto is a practically valuable tool: it reduces per-workload memory-latency sensitivity characterization from a multi-point frequency sweep or full simulation to a single three-counter measurement, while retaining the mechanistic CPI structure. The paper's strengths include a principled leave-one-out protocol, direct hardware validation on a real DDR-to-HBM system at a CXL-like penalty, honest disclosure of the model-vs-model nature of the 8x numbers, and a systematic comparison against PROFET using a paired statistical test. The main open risk is the constancy of BF and MPI under large memory-penalty changes; the manuscript discloses this as a limitation but does not provide the direct ChampSim-based BF-drift measurement that would close the gap.","major_comments":[{"comment":"The correctness of the central prediction (Eq. 4) rests on BF_B = BF_A and MPI_B = MPI_A as MP varies, an assumption stated in §3.5 and acknowledged as the 'strongest limitation' in §5.8. The paper does not quantify how much of the reported error at 8x MP is due to drift in BF as opposed to error in the cross-workload regression. On ChampSim, direct simulation provides ground-truth CPI at up to 6.7-7.0x the baseline (Table 5), so the manuscript could compute, per workload, the BF implied at each simulated latency from CPI, MPI, and the baseline CPI0, and then report the distribution of BF_B - BF_A; this would directly test the load-bearing assumption. Without this, the 19% of high-memory-fraction workloads with errors above 25% at 3x (Fig. 9) are the cases where the assumption is most likely to break, and the cause is left unattributed.","section":"§3.5, §5.6, §5.8, Table 6"},{"comment":"The 8x 'CPI error' columns in Table 6 are not errors against hardware measurements; §4.4.2 states that beyond the DVFS range both Aneto and Clapp et al. rely on the same linear CPI model, so the numbers are model-vs-model agreement. The table labels the comparison 'ground-truth BF', but that ground-truth BF is itself the slope of a linear fit that assumes BF is constant across the fit range. The abstract's phrase 'agrees with a reference model' is honest, but the body should consistently label these results as model-vs-model, and claims about 8x accuracy on real hardware should be based on the ChampSim results, where ground truth comes from direct simulation.","section":"§4.4.2, Table 6, Abstract"},{"comment":"The R^2 >= 0.90 retention filter is applied to the per-workload linear fit before computing LOO errors and is disclosed in §4.2 and §5.6, but it conditions the central claim. Because a practitioner applying Aneto to a new workload does not know its R^2 without performing the multi-point sweep the method is meant to avoid, the 'single run for any workload' claim in the abstract and §1 is stronger than what is evaluated. Please report the number of workloads excluded by the R^2 gate separately from those excluded by the MPI threshold (Table 3 gives only the post-filter counts), and provide a single-run observable diagnostic, such as the LOO residual or a confidence interval from the regression, that indicates when a new workload is likely to fall outside the model's validity.","section":"§4.2, §5.6, §3.5"},{"comment":"The ARM DDR-to-HBM validation changes the execution configuration from the single-thread setup described in §4.2 to 16-copy rate runs in §5.4, but the paper does not state whether the Aneto coefficients and the 'single DDR run' used for prediction were obtained under the same 16-copy configuration or under the single-thread configuration. If the calibration used single-thread measurements and the prediction used rate measurements, the validation conflates a change in concurrency and bandwidth pressure with the memory-penalty change the model is designed to predict. Please specify the configuration for both the calibration sweep and the prediction run, and report the HBM errors for both configurations if possible.","section":"§5.4, §4.2"}],"minor_comments":[{"comment":"The values '3.2×10^-3 to 3.3×10^-3' for the Zen5 P90 are reported without units and are inconsistent with the percent-scale errors elsewhere; please state whether these are relative CPI errors, absolute BF errors, or something else.","section":"§5.5"},{"comment":"The text says the DVFS sweep covers only 1.5-2.3x, but Table 5 reports MP factors of 0.4x-0.7x, meaning the most distant point lies below the baseline; clarify whether the 1.5-2.3x refers to the total MP spread and reconcile the notation.","section":"§4.4.2, Table 5"},{"comment":"The W column in Table 7 (44 for all hardware platforms, 87 for all simulators) does not match the per-platform W counts in Table 3 (85/86/71/73/80/130/129/92); please explain which workload subset the subsampling and the 16-corpus comparison used, or recompute with the full qualifying sets.","section":"Table 7"},{"comment":"The assertion that BPI_B = BPI_A and MPI_B = MPI_A 'we observe no changes over measurement noise' is not backed by data in the manuscript; include the supporting measurement or a reference to a figure.","section":"§2, Step 3"},{"comment":"There are several typos, including 'an prohibitive amount of resources' and 'the the predictive power'; a careful proofread is needed.","section":"§5.4, §5.8"}],"recommendation":"major_revision","confidential_remarks":"The manuscript is notably transparent about the model-vs-model nature of the 8x hardware comparison and about the R^2 retention gate, which I view as a strength. The remaining issue is that the disclosed limitations are not quantified in a way that lets a reader bound the error for a new workload; in particular, the ChampSim infrastructure already exists to measure BF drift directly, and requiring that analysis would substantially raise the confidence in the central claim. The Table 7 W discrepancy should also be resolved during revision."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Read Aneto. The core idea is genuinely new: a cross-workload regression that recovers the blocking factor from a single native run. The empirical regularity in log(MPI*MP) vs log(CPI) space is not in the cited prior work, and replacing per-workload memory sweeps with a three-coefficient fit is a legitimate contribution. The ARM DDR-to-HBM measurement is the strongest piece of evidence — 12.7% median CPI error at ~3x penalty is a real hardware validation, not a simulation artifact.\n\nThe paper is also honest about its scope. It explicitly labels the 8x results as model-vs-model, discloses the R2 retention filter and the memory-inactive exclusions, and gives a fair comparison against PROFET on ChampSim. The LOO protocol is sound, and the paired Wilcoxon tests support the ~2x error reduction over PROFET. The cross-platform analysis (Zen family vs Comet Lake) is a useful sanity check, even if the negative result across vendors is expected.\n\nThe soft spots are mostly around the constant-BF assumption. On hardware, the DVFS sweep only moves MP to 0.4x–0.7x of baseline, so the only direct evidence at large penalty is that single ARM experiment at ~3x. The 8x extrapolation relies entirely on the linear CPI model being exact, and the paper never measures BF drift directly at 8x on ChampSim, where ground truth is available. I agree with the stress-test note: this is the missing experiment that would settle the main risk — not a fatal flaw, but a concrete gap. The R2>=0.90 gate removes exactly the workloads whose linear fit is weak, so the headline error numbers are conditional on the workloads that conform to the model. The 19% tail with >25% error at 3x is a reminder that the method's value is first-order screening, not precise prediction.\n\nOne clarity issue: qualifying workload counts differ between Table 3 and Table 7 (e.g., Zen5 73 vs 44). Presumably the latter is a stricter filter, but the paper never says. That should be fixed in revision.\n\nWho is this for? Architects doing early design-space exploration of memory technologies — DDR, HBM, CXL — who want a cheap per-workload sensitivity estimate from one run. It won't replace detailed simulation for critical decisions, but it fills a real gap. The paper deserves peer review; I'd accept it conditionally and ask for code/data release, the ChampSim BF-drift measurement, and the workload-count clarification. The central idea is solid enough that these are revision items, not grounds for rejection.","headline":"Single-run blocking-factor prediction with a real 3x hardware check, but the 8x story still rests on an unmeasured constant-BF assumption.","tokens_in":21840,"tokens_out":4336,"would_cite":true,"duration_ms":35694,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Single-run counters suffice to recover the stall fraction of any workload, so CPI under any memory technology is predictable without simulation.","keywords":["blocking factor","CPI prediction","memory latency","hardware performance counters","cross-workload regression","memory-level parallelism","HBM","performance modeling"],"falsifier":"Take a workload whose memory behavior is known to change with latency—for example, one that alternates between streaming and pointer-chasing phases, or whose prefetcher timeliness degrades when DRAM slows down—and run it at the baseline memory and at a target memory with about three times the penalty, measuring the actual CPI on both. Compute Aneto's prediction from the baseline counters and compare the CPI error against the paper's reported 12.7% median; if a substantial class of such workloads consistently shows errors well above the reported 90th percentile of 36%, the constant-blocking-factor regularity is not as general as claimed.","tokens_in":20751,"feed_emoji":"⚡","tokens_out":9528,"duration_ms":87035,"temperature":0.7,"pith_summary":"Aneto's central claim is that on a given CPU, the blocking factor—the fraction of each last-level-cache miss's latency that actually stalls the pipeline—can be recovered from three standard hardware counters collected in a single baseline run, with no simulation, no per-workload frequency sweeps, and no profiler. The paper shows that the blocking factor varies smoothly across more than 100 diverse workloads when plotted in log-transformed (misses-per-instruction times miss-penalty, CPI) space, and captures that regularity with a three-coefficient logistic regression. If this holds, an architect who has measured one workload on today's memory can predict its CPI under HBM, CXL, or any other memory technology whose latency-bandwidth supply curve is known, using only the counters from that one run. The paper validates the idea on five hardware platforms plus a separate ARM server for direct DDR-to-HBM validation, and on two simulators, reporting a median CPI error of 12.7% when predicting DDR-to-HBM changes at about three times the baseline memory penalty, and roughly two times lower error than the best prior one-shot predictor on simulator experiments.","feed_headline":"Three counters predict how any workload reacts to new memory","feed_subtitle":"Fit once per machine; one baseline run then gives CPI on HBM, CXL, or any memory latency","key_machinery":"The key object is the blocking factor $BF$, the fraction of an LLC miss's memory penalty that actually stalls the pipeline, introduced through the linear decomposition $CPI = CPI_0 + BF \\cdot MPI \\cdot MP$. Aneto's machinery is a cross-workload logit regression, fitted once per platform on a small reference corpus, which maps the log of the maximum memory stall per instruction ($MPI \\cdot MP$) and the log of CPI onto $BF$; the CPI term disambiguates workloads with equal memory exposure but different latency-hiding ability. The prediction step subtracts the baseline miss penalty and adds the $BF$-weighted miss-penalty difference, so it never needs to compute $CPI_0$ explicitly. The machinery inherits two assumptions from the linear model: $BF$ and $MPI$ stay constant as the memory penalty changes, and the regression fitted on reference workloads generalizes to any new workload on the same machine.","core_discovery":"On a fixed microarchitecture, the linear CPI decomposition $CPI = CPI_0 + BF \\cdot MPI \\cdot MP$ leaves the blocking factor $BF$ as the only quantity that must be inferred, and Aneto's discovery is that $BF$ is not arbitrary per workload: in the log-transformed plane of memory exposure ($MPI \\cdot MP$) against CPI, workloads of very different suites arrange themselves along a smooth $BF$ gradient, so the same regression coefficients assign a blocking factor to a held-out workload from its single baseline point. The estimator is $\\mathrm{logit}(BF) = \\beta_0 + \\beta_1 \\log(MPI \\cdot MP) + \\beta_2 \\log(CPI)$, with CPI doing the work of separating workloads that share the same memory exposure but hide latency differently. Substituting the predicted $BF$ into $CPI_B = CPI_A + BF \\cdot MPI_A \\cdot (MP_B - MP_A)$ yields first-order CPI prediction at any memory penalty without ever running the workload on the target memory. The paper's evidence is the regularity across 110 hardware workloads and 132 simulator traces, the direct DDR-to-HBM hardware validation at roughly three times the penalty with 12.7% median error, and the eight-times extrapolation where the model agrees with the reference linear model to within about 15% median on the newest tested AMD platform.","pith_inferences":["If the regularity reflects a structural co-evolution of programs and hardware rather than an artifact of the benchmark mix, the same regression may transfer to new workload classes with only per-platform intercept shifts; this is testable by fitting on one processor generation and predicting blocking factors on the next.","The model's success suggests a cheap screening layer before detailed cycle-level simulation: use a single-run blocking-factor estimate to shortlist latency-sensitive workloads, then simulate only those.","Aneto's demand-side blocking-factor estimate composes naturally with a measured supply curve for the target memory, potentially predicting performance for memory technologies that do not physically exist yet, subject only to the supply curve's validity.","A direct test of the mechanism would be to check whether $BF$ and $CPI_0$ are correlated because both trace back to one latent workload property; if so, the regression could be collapsed to one feature plus a platform offset."],"forward_implications":["On a machine already fitted with the three-coefficient regression, predicting a new workload's CPI under any memory latency costs one five-minute run instead of a full frequency sweep or a simulation.","The regression needs only a handful of reference workloads to fit: the paper measures the minimal corpus size at five to seven workloads, so fitting a new machine is a bounded one-time cost.","Workload ordering by memory sensitivity is preserved, with a rank-correlation coefficient of 0.86 to 0.93 at three times the penalty, so the model can drive placement decisions such as which workloads belong in a fast HBM tier.","The same equations apply in simulators, so design-space exploration can replace time-consuming re-simulation at each memory latency with a single baseline evaluation."],"supporting_citations":[{"why":"Supplies the linear CPI decomposition $CPI = CPI_0 + BF \\cdot MPI \\cdot MP$ and the per-workload multi-point regression used as ground truth.","marker":"[11]"},{"why":"Establishes the memory-level-parallelism decomposition that defines the blocking factor.","marker":"[9]"},{"why":"Provides the five-point frequency-sweep measurement methodology from which ground-truth BF and CPI0 are extracted.","marker":"[10]"},{"why":"Defines the interval-model framework that motivates the blocking factor as the overlap of miss latency with useful work, and whose assumptions bound Aneto's scope.","marker":"[15]"},{"why":"The one-shot predictor baseline that Aneto is compared against on simulator configurations.","marker":"[26]"},{"why":"Supplies the bandwidth-latency supply curves used in the motivating scenario to find the miss penalty at the supply-demand intersection.","marker":"[14]"},{"why":"Simulator used for the latency-sweep validation and the head-to-head comparison against the one-shot baseline.","marker":"[17]"},{"why":"Independent simulator used to extend validation to configurations not reachable on hardware.","marker":"[8]"}],"fun_headline_variants":["One run predicts CPI on HBM, CXL, any memory","Aneto: one baseline run, any memory penalty","Single-run stall fraction predictor for memory changes","From one run, predict CPI under any memory latency","Aneto: CPI from one run, any memory config"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that a workload's stall fraction and its LLC miss rate do not change when the memory latency changes, so the blocking factor measured or inferred at one memory configuration is the right coefficient for any other configuration.","fun_headline_variants_meta":{"raw":{"variants":["One run predicts CPI on HBM, CXL, any memory","Aneto: one baseline run, any memory penalty","Single-run stall fraction predictor for memory changes","From one run, predict CPI under any memory latency","Aneto: CPI from one run, any memory config"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000611,"raw_usage":{"total_tokens":2924,"prompt_tokens":1106,"completion_tokens":1818,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":722,"completion_tokens_details":{"reasoning_tokens":1740}},"tokens_in":722,"tokens_out":1818,"duration_ms":11785,"temperature":1.0,"reasoning_tokens":1740,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-10T13:25:26.297669+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Take a workload whose memory behavior is known to change with latency—for example, one that alternates between streaming and pointer-chasing phases, or whose prefetcher timeliness degrades when DRAM slows down—and run it at the baseline memory and at a target memory with about three times the penalty, measuring the actual CPI on both. Compute Aneto's prediction from the baseline counters and compare the CPI error against the paper's reported 12.7% median; if a substantial class of such workloads consistently shows errors well above the reported 90th percentile of 36%, the constant-blocking-factor regularity is not as general as claimed.","supporting_citations":[{"cited_title":"Quantifying the Performance Impact of Memory Latency and Bandwidth for Big Data Workloads","cited_arxiv_id":null,"evidence_quote":"Supplies the linear CPI decomposition $CPI = CPI_0 + BF \\cdot MPI \\cdot MP$ and the per-workload multi-point regression used as ground truth."},{"cited_title":"A Simple Model to Quantify the Impact of Memory Latency and Bandwidth on Performance","cited_arxiv_id":null,"evidence_quote":"Provides the five-point frequency-sweep measurement methodology from which ground-truth BF and CPI0 are extracted."},{"cited_title":"A mechanistic performance model for superscalar out-of-order processors","cited_arxiv_id":null,"evidence_quote":"Defines the interval-model framework that motivates the blocking factor as the overlap of miss latency with useful work, and whose assumptions bound Aneto's scope."},{"cited_title":"PROFET: Modeling System Performance and Energy Without Simulating the CPU","cited_arxiv_id":null,"evidence_quote":"The one-shot predictor baseline that Aneto is compared against on simulator configurations."}],"review_version":1}