{"id":"2bdfc492-9fce-4c5e-8595-3ea99ccea3cd","arxiv_id":"2608.09077","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"A RISC-V vector-optimized ANNS engine combines a mixed-precision vector encoding (MPMI) with traversal-aware graph reordering (ROrder) to cut memory traffic and improve cache locality.","lead":"RVANNS is a search engine that speeds up approximate nearest neighbor lookups on RISC-V chips by compressing vectors into a mixed 8-bit, 16-bit, and 32-bit form and by rearranging the search graph so memory reads flow mostly forward. On real RISC-V hardware it reports 3.4x to 4.9x speedups over plain scalar code and better energy per query than the GPU baselines tested.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"ROrder's Algorithm 3 does not compute the score S defined in Sec 5.1: in-degree seeding and a missing reverse-adjacency update mean the evaluated reordering is not the algorithm described, undermining reproducibility and the stated mechanism.","rationale":"The reader's weakest assumption concerned the external validity of ROrder's score as a proxy for traversal co-visitation and whether sorting adjacency lists changes search outcomes. That is a legitimate empirical question, but it does not point to a definite flaw in the reported measurements. In good faith, the more load-bearing concern is internal: the pseudocode of the central ROrder algorithm does not match its own formal definition. This is concrete and checkable. If Algorithm 3 does not compute the defined score, then the paper's explanation of why ROrder works is not what was actually implemented, and any independent implementation from Sec 5.1 would likely produce different permutations and performance. Such an inconsistency directly undermines reproducibility, which is already a stated condition for the reader's verdict, and it targets the same component (ROrder) as the reader's concern. Since the paper's headline speedups are still plausible and the inconsistency can be resolved by a correction or an artifact, the appropriate verdict remains conditional rather than reject or accept. The described reimplementation test would settle whether the evaluated algorithm differs from the published description and whether the missing in-degree/adjacency terms are material to the measured gains.","tokens_in":25844,"tokens_out":26994,"duration_ms":480369,"concrete_test":"Reimplement ROrder strictly from the prose: initialize all scores to 0; choose P[1] as the highest in-degree node; for each subsequently placed node v, add the full symmetric S(v,u) to the score of every unplaced u, including both adjacency directions; select each P[i] as the unplaced node with the current maximum score using a max-heap. Run the SIFT1M HNSW+MPMI pipeline with this corrected permutation and the same adjacency sorting, and compare the resulting QPS and permutation against the reported 3319.76 QPS and 18.77% gain. If the corrected greedy yields a materially different permutation or QPS, then Algorithm 3 is not the algorithm that produced the paper's results.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper defines a locality score S(u,v)=|N^-(u) ∩ N^-(v)| + 1[(u,v)∈E] + 1[(v,u)∈E] (Sec 5.1) and states that the greedy selects each next node by maximizing the window sum of S. However, Algorithm 3 initializes the priority-queue keys as s[v]=|N^-(v)| (line 5), so every selection is biased by in-degree throughout the run, not just for the first node. This in-degree term is never described as part of the objective. Moreover, IncrUpdate (lines 17-19) updates only out-neighbors of the entering node and out-neighbors of its in-neighbors. This adds the shared-in-neighbor term and the forward-adjacency term 1[(v,·)∈E], but it never adds the reverse-adjacency term 1[(·,v)∈E] for unplaced in-neighbors of the placed node. Consequently, the scores maximized by the greedy are not the S defined in Sec 5.1, and the pseudocode does not implement the described algorithm. Since the reported 18.77% QPS gain and the comparison against GOrder (Table 13) were obtained with this undocumented algorithm, a reader cannot reproduce ROrder from the description, and the paper's claim that ROrder optimizes traversal co-visitation through S is unsupported by the provided implementation. This is an internal inconsistency, not a question of measurement noise or platform effects.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"RVANNS targets approximate nearest neighbor search on RISC-V vector processors. It contributes two co-designed mechanisms: MPMI, a mixed-precision representation with a dense 8-bit affine base and sparse FP16/FP32 residuals aligned to RVV LMUL widening, and ROrder, a traversal-aware graph permutation plus adjacency-list sorting intended to create forward-moving payload streams. The paper reports within-platform speedups up to 3.39x and 4.94x over scalar on SG2044 and BPI-F3, 2.27-2.76x over SIMD+FP32 HNSW on RVV, cross-ISA transferability results on SVE/AVX-512, and a GPU energy-efficiency comparison on Cohere10M.","tokens_in":26181,"tokens_out":9985,"duration_ms":80921,"significance":"At a high level the paper makes a useful contribution: it is a serious, hardware-driven co-design of an ANNS engine for RVV, with unusually detailed PMU-based motivation and within-platform ablations that isolate VLA execution, LMUL sensitivity, MPMI versus conventional SQ8, and ROrder versus generic graph orderings. The same binary running on 128-bit and 256-bit RVV platforms is a nice demonstration of RVV VLA portability. If the mechanisms are as described, the results are of interest to both the ANNS and RISC-V systems communities.","major_comments":[{"comment":"Section 5.1 defines the objective S(u,v)=|N^-(u)∩N^-(v)| + 1[(u,v)∈E] + 1[(v,u)∈E] and states that the greedy selects each next node by maximizing the window sum of S. Algorithm 3, however, initializes s[v]=|N^-(v)| for every node (line 5), so every ExtractMax is biased by raw in-degree in addition to the windowed S terms. Moreover, IncrUpdate (lines 17-19) updates only out-neighbors of the entering node and out-neighbors of its in-neighbors; it adds the shared-in-neighbor term and the forward-adjacency term, but it never adds the reverse-adjacency term 1[(·,v)∈E] for unplaced in-neighbors of the node just placed. The pseudocode therefore does not implement the greedy described in the text, and the results in Table 13 (including the 18.77% gain over the unordered layout and the 9.97% gain over GOrder) were obtained with an undocumented scoring rule. Please correct the algorithm description or describe and analyze the actual score, and state which variant was used for the reported measurements.","section":"Sec. 5.1 / Algorithm 3"},{"comment":"Section 4.3 describes residual fusion as \"vluxei* loads the selected residuals, vrgather packs the corresponding base lanes, and vsuxei* writes the corrected values into a temporary buffer; the downstream distance kernel then reloads this buffer,\" which implies a materialized reconstructed tile. In contrast, Algorithm 2 (lines 24 and 26) applies a masked vfadd and then accumulates with vfmacc \"no store,\" and the text claims decoding \"without materializing a persistent full FP32 vector.\" This is an internal inconsistency in the description of the central MPMI fused-decode mechanism; the authors should clarify the actual data path, since the fused versus materializing distinction is exactly what MPMI's performance claims rely on.","section":"Sec. 4.3 / Algorithm 2"},{"comment":"The text states that MPMI delivers 1.35x higher QPS than HNSW and 3.43x higher than IVF on SIFT1M, and 1.20x and 9.12x on GIST1M, but Table 12 reports +91.38% (≈1.91x) and +230.14% (≈3.30x) for SIFT1M, and +124.14% (≈2.24x) and +751.02% (≈8.51x) for GIST1M. Please reconcile the table and the prose; as published, the text numbers are inconsistent with the data.","section":"Sec. 7.5 / Table 12"},{"comment":"The GPU comparison measures SG2044 platform power over PSU1+PSU2 with ipmitool, while the GPU baselines report NVIDIA device power. Comparing these numbers to compute QPS/W makes the 1.82-2.27x energy-efficiency claim not a like-for-like comparison, because platform power includes DRAM and other system components that device power excludes. Please either measure SG2044 device/package power, report both scopes transparently, or restrict the claim to the power scope actually measured.","section":"Sec. 7.10 / Table 16"},{"comment":"The claim that sorting each adjacency list by remapped IDs \"changes layout within each neighbor list, not the underlying graph, so recall remains unchanged under fixed HNSW parameters\" is not guaranteed: HNSW beam search visits neighbors in stored order, and reordering a neighbor list can change the order in which candidates are evaluated, which can alter the candidate set at a fixed ef_search. The paper provides no ablation showing recall invariance; please provide such a verification or qualify the claim.","section":"Sec. 5.2"}],"minor_comments":[{"comment":"The figure and Algorithm 2 label the base as \"FP8\" while the text and Equation (1) describe a dense 8-bit affine base with integer byte values; please use a consistent name to avoid confusion with IEEE FP8 formats.","section":"Fig. 2 / Algorithm 2"},{"comment":"The sequential LMUL=1 run (344.3M cycles) is slower than the irregular LMUL=1 run (289.7M cycles); please explain why the two microbenchmarks are not directly comparable or what accounts for the reversal.","section":"Table 4"},{"comment":"Line 11 applies IncrUpdate(P[i-w],-1) for the node leaving the window; please state whether leaving-node effects on scores of already-placed nodes are intentionally ignored, since the described windowed objective only sums over the current window.","section":"Algorithm 3"},{"comment":"Reference [4] is a survey on FPGAs but is cited to support graph processing on vector processors; this citation appears mismatched.","section":"References"},{"comment":"The paper mentions a released artifact with 58,082 SLOC but gives no repository or DOI; please include the artifact link.","section":"sec. 6.1 / Artifacts"},{"comment":"The axis label in Figure 8(a) renders the thresholds as \"Precision Threshold ( 32, 16)\" with missing Greek letters and units; please fix the formatting.","section":"Fig. 8"}],"recommendation":"major_revision","confidential_remarks":"This is a solid systems paper whose main risk is the gap between the described and implemented ROrder algorithm; that must be resolved before acceptance. The GPU power-scope comparison should also be corrected. The paper is otherwise within scope and likely publishable after major revision."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"RVANNS is a solid systems paper that deserves a careful read: it demonstrates a working ANNS backend on real RISC-V vector hardware, with the strongest gains from MPMI, a residual mixed-precision layout aligned to RVV's LMUL semantics. The within-platform ablations—VLA vs fixed-length, LMUL sweep, MPMI vs SQ8—are well designed and support the mechanisms. The authors are also unusually candid in Sec 7.11 about cross-ISA confounds, which is appreciated.\n\nThe soft spots are real but concentrated. The most serious is in ROrder. The stress-test note is correct: Algorithm 3 initializes s[v] to in-degree and never adds the reverse-adjacency term 1[(z,v)∈E] from the defined S(u,v). As a result, the greedy maximizes a different, undocumented objective—in-degree plus partial windowed scores—and the paper's mechanism claim for ROrder is not supported by the pseudocode it ships. This is an internal inconsistency, not a measurement artifact. Combined with the absence of a code link and no variance reporting, a reader cannot reproduce the 18.77% ROrder gain from the text. The cross-platform speedups (3.39x, 4.94x) are explicitly platform-level, not cycle-isolated; the authors say so, but readers should treat them as such.\n\nThe GPU comparison is coarse: device-only power, one dataset, no memory bandwidth analysis. Minor.\n\nOverall: this is a good engineering contribution with a load-bearing presentation bug in ROrder. It deserves peer review, but reviewers should be instructed to verify the actual reordering code against the described objective. I'd want to see the corrected pseudocode and ideally the artifact before trusting the ROrder numbers. For a reading group, it's worth a slot, mainly to discuss how a well-meaning systems paper can ship an algorithm mismatch. Who this is for: systems people working on CPU ANNS backends, especially anyone targeting RISC-V or thinking about mixed-precision decode paths. The methodology is transferable even if the ROrder fix changes the numbers.","headline":"Serious RVV ANNS engineering with a reproducible ROrder problem: Algorithm 3 does not implement the stated locality score.","tokens_in":26750,"tokens_out":5098,"would_cite":false,"duration_ms":43808,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A RISC-V ANNS engine claims 3.4–4.9x speedups by co-designing mixed-precision decoding and graph layout.","keywords":["approximate nearest neighbor search","RISC-V Vector Extension","mixed-precision indexing","graph reordering","memory-level parallelism","vector-length-agnostic execution","HNSW","SIMD decoding"],"falsifier":"Measure ROrder's QPS gain on a graph whose traversal order is decoupled from topology, e.g., random edge rewiring that preserves degrees, or compare traversal-log co-visitation against the S(u,v) score; if the proxy does not track actual co-visits, the gain should shrink or vanish, and if permuted sorting changes Recall@100 at fixed efSearch, the claim that reordering is outcome-neutral fails.","tokens_in":25659,"feed_emoji":"🔍","tokens_out":6310,"duration_ms":51703,"temperature":0.7,"pith_summary":"Approximate nearest neighbor search on CPUs is limited less by arithmetic speed than by moving and decoding candidate vectors, and the paper argues this is especially true on RISC-V vector processors. It claims that two co-designed mechanisms—MPMI, a mixed-precision index that stores each vector as a dense 8-bit affine base plus sparse FP16/FP32 residuals, and ROrder, a traversal-aware graph reordering—turn the RISC-V Vector Extension's register grouping and length-agnostic loops into large end-to-end speedups. On real 128-bit and 256-bit RISC-V vector hardware, the engine reports 3.39x and 4.94x speedups over scalar execution, and 2.27–2.76x over a SIMD+FP32 HNSW baseline at Recall@100=0.99. A sympathetic reader would care because it identifies the memory-side bottlenecks that remain after vectorization and offers a portable recipe for addressing them.","feed_headline":"RISC-V ANNS gains 3.4–4.9x via decode-layout co-design","feed_subtitle":"A mixed-precision index and traversal-aware reordering beat scalar and SIMD baselines on real vector CPUs.","key_machinery":"The load-bearing machinery is the pair (MPMI, ROrder) executed on an RVV kernel layer. MPMI is a mixed-precision multi-layer index: each vector is a dense 8-bit affine base $b$ plus sparse FP16 and FP32 residual pools selected by per-dimension error, and the decoder streams the base, gathers selected residuals via bitmap/prefix lookup, and fuses reconstruction with $vfmacc$ accumulation in LMUL-grouped tiles. ROrder is a locality transformation: it scores node pairs by $S(u,v)=|N^-(u)\\cap N^-(v)|+1[(u,v)\\in E]+1[(v,u)\\in E]$, builds a permutation with a windowed greedy algorithm, co-locates node payloads in 64-byte-aligned rows, and sorts adjacency lists by permuted IDs so traversals become address-monotone. The RVV kernel layer supplies vsetvl-based variable-length execution and LMUL grouping that translate these two mechanisms into throughput.","core_discovery":"The central discovery is that ANNS on RVV is memory-bound in two specific ways—the decode path for low-precision vectors dilutes RVV's register-group widening, and irregular graph traversal scatters payload accesses enough to neutralize LMUL scaling—and that both can be fixed by co-designing representation and layout. MPMI encodes each vector as a dense 8-bit affine base with sparse FP16/FP32 corrections, so reconstruction and distance accumulation fuse in one LMUL-aligned loop without materializing an FP32 vector. ROrder permutes graph nodes so that likely co-visited nodes get adjacent IDs and sorts each adjacency list by the new IDs, making payload probes predominantly forward-moving address streams. Together they deliver the speedups above, with the largest gains on RVV because vsetvl-based variable-length execution and LMUL register groups convert reduced memory traffic and better locality into sustained throughput.","pith_inferences":["The locality proxy could be checked directly: if one recorded actual co-visitation during beam search and compared it with the shared-in-neighbor score, ROrder's 18.77% gain would stand or fall on that match; the paper does not provide such a traversal-log validation.","ROrder's gains should shrink on workloads where beam search drifts from topology, e.g., query distributions that visit nodes adversarially; testing with adversarial or clustered query sets would reveal how general the reordering is.","The same fused-decode idea could be extended to learned compression or product quantization, but that would require gather-heavy codebook lookups that MPMI deliberately avoids, so the extension is not immediate."],"forward_implications":["If the central claim is right, a single RVV binary can get portable acceleration across 128-bit and 256-bit vector lengths, with MPMI+ROrder adding 2.76x–3.63x over each platform's SIMD+FP32 baseline.","The same memory-side mechanisms transfer partially to SVE and AVX-512, yielding 1.18x–1.59x over their SIMD+FP32 HNSW baselines, so the techniques are not RISC-V-exclusive.","Index memory footprint drops by roughly 58–72% versus NEON HNSW baselines because MPMI reduces per-candidate bytes, shifting the bottleneck away from DRAM traffic.","On a 10M-scale dataset, the engine reports higher QPS per watt than GPU baselines, suggesting CPU-resident vector search can be the more power-efficient operating point at high recall."],"supporting_citations":[{"why":"Supplies the HNSW graph index that RVANNS accelerates and whose beam-search traversal defines the co-visitation pattern ROrder targets.","marker":"[31]"},{"why":"Frames ANNS as memory-bound and provides the thread-affinity and recall-matching methodology used in the evaluation.","marker":"[22]"},{"why":"Establishes that scalar quantization suits CPU SIMD ANNS better than product quantization, motivating MPMI's dense 8-bit affine base.","marker":"[44]"},{"why":"Defines RVV's vsetvl and LMUL semantics that MPMI's register-group-aligned widening and VLA execution rely on.","marker":"[36]"},{"why":"Provides the strongest generic graph-ordering baseline, used to show ROrder's traversal-aware score adds throughput over generic ordering.","marker":"[46]"},{"why":"Classic bandwidth-reduction reordering baseline that ROrder is compared against.","marker":"[11]"},{"why":"Community-structure graph ordering baseline used in the reordering comparison.","marker":"[2]"},{"why":"Provides the SIMD ANNS library baseline, including the GPU path, that RVANNS is compared against.","marker":"[25]"}],"fun_headline_variants":["RISC-V ANNS speeds up 3.4–4.9x via mixed-precision and locality","Decode-layout co-design accelerates RISC-V ANNS 3.4-4.9x","Mixed-precision and locality-aware graph traversal speed up RISC-V ANNS","RVANNS: fusing decode and reordering boosts RISC-V vector ANNS","Co-designing vector representation and graph locality yields 3-5x on RVV"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that shared in-neighbors plus direct adjacency reliably predicts which HNSW nodes are actually visited together during beam search, and that permuting node IDs and sorting adjacency lists leaves the search outcome unchanged; the 18.77% QPS gain from ROrder rests on this proxy.","fun_headline_variants_meta":{"raw":{"variants":["RISC-V ANNS speeds up 3.4–4.9x via mixed-precision and locality","Decode-layout co-design accelerates RISC-V ANNS 3.4-4.9x","Mixed-precision and locality-aware graph traversal speed up RISC-V ANNS","RVANNS: fusing decode and reordering boosts RISC-V vector ANNS","Co-designing vector representation and graph locality yields 3-5x on RVV"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001471,"raw_usage":{"total_tokens":5949,"prompt_tokens":1017,"completion_tokens":4932,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":633,"completion_tokens_details":{"reasoning_tokens":4814}},"tokens_in":633,"tokens_out":4932,"duration_ms":29553,"temperature":1.0,"reasoning_tokens":4814,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T00:00:07.484749+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure ROrder's QPS gain on a graph whose traversal order is decoupled from topology, e.g., random edge rewiring that preserves degrees, or compare traversal-log co-visitation against the S(u,v) score; if the proxy does not track actual co-visits, the gain should shrink or vanish, and if permuted sorting changes Recall@100 at fixed efSearch, the claim that reordering is outcome-neutral fails.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Frames ANNS as memory-bound and provides the thread-affinity and recall-matching methodology used in the evaluation."},{"cited_title":"2021.RISC-V Vector Extension Specification","cited_arxiv_id":null,"evidence_quote":"Defines RVV's vsetvl and LMUL semantics that MPMI's register-group-aligned widening and VLA execution rely on."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Classic bandwidth-reduction reordering baseline that ROrder is compared against."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Community-structure graph ordering baseline used in the reordering comparison."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the SIMD ANNS library baseline, including the GPU path, that RVANNS is compared against."}],"review_version":1}