{"id":"eb66bf73-a4dc-4ad3-a041-39b9b48be353","arxiv_id":"2608.09421","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":5,"one_line_summary":"A fully convolutional HAR architecture, LITEWAY, matches state-of-the-art lightweight models in accuracy while reducing model size and energy consumption on embedded hardware.","lead":"This paper introduces LITEWAY, a fully convolutional neural network for recognizing human activities from wearable sensor data, designed to run on small, low-power devices. It reports competitive accuracy on 16 activity datasets while using far fewer parameters and less energy than existing lightweight models such as TinyHAR and TinierHAR.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Deployment table and text disagree on LITEWAY-L energy and CPU values, so the paper's headline energy-savings claim is not reproducible until the discrepancy is resolved.","rationale":"The reader's weakest assumption already identified the deployment-measurement inconsistency as the primary load-bearing issue, and my independent reading agrees. The energy claim is central to the paper's contribution, and the text versus Table 5 discrepancy is a concrete, checkable internal inconsistency rather than a matter of outside consensus. The MAC and parameter-count reductions are separately supported by architectural counts and are not undermined by this concern, so the paper is not fundamentally invalidated; however, the energy numbers need verification before the 'energy reductions' claim can be accepted. Because the reader's verdict is already CONDITIONAL on this issue, my stress-test does not move the verdict, hence UNCHANGED.","tokens_in":13371,"tokens_out":4436,"duration_ms":39187,"concrete_test":"Re-run the deployment benchmark on the same STM32L4S5 running at 120 MHz using the released LITEWAY-L and TinierHAR models and the X-NUCLEO-LPM01A shield, measuring per-inference energy and CPU load over at least 100 inferences and reporting raw measurements. Specifically, check whether LITEWAY-L energy is 2.90 mJ or 32.90 mJ and whether CPU load is 3% or 30.54%, then recompute all energy-reduction ratios in the abstract from the verified value. If the verified value is 32.90 mJ, the abstract's '2.29x-3.14x (Light)' range must be amended to reflect the actual 2.63x-3.61x range versus the reported baselines.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The strongest claim is that LITEWAY reduces energy by 2.29x-3.14x (Light) and 1.46x-2.01x (Full) versus TinierHAR and MLP-HAR. This rests entirely on the STM32L4S5 deployment measurements in Section 4.3.5 and Table 5. The paper contains two incompatible values for the same LITEWAY-L row: the text states that LITEWAY Light requires only 3% CPU load and 2.90 mJ per inference, while Table 5 lists CPU load 30.54% and energy 32.90 mJ/Inf for that same model. If 32.90 mJ is the correct value, the reduction ratios become 86.36/32.90 = 2.63x versus TinierHAR and 118.73/32.90 = 3.61x versus MLP-HAR, neither matching the abstract's 2.29x-3.14x range. The text also does not define how CPU load is computed, whether energy includes idle versus active CPU periods, or whether averaging over 16 inference cycles is sufficient for a stable measurement. Because the energy advantage is a central claimed contribution, an internal inconsistency in the only energy measurement makes the headline efficiency benefit unsupported until verified.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"LITEWAY is a fully convolutional, modality-agnostic architecture for wearable human activity recognition (HAR). It substitutes recurrent temporal modeling with a structured convolutional decomposition (SCTM), using depthwise convolutions, shared pointwise projections, gated/highway-inspired pathways, and attention-based temporal pooling. The paper evaluates LITEWAY-Light and LITEWAY-Full on 16 HAR datasets with subject-independent split, five seeds, and compares against TinyHAR, TinierHAR, MLP-HAR, and DeepConvLSTM. The authors report competitive macro-F1 (Light 0.808, Full 0.813 vs baselines 0.801–0.807), large parameter/MAC reductions (up to 9.5× and 146×), and energy reductions from deployment on an STM32L4S5 microcontroller (2.29×–3.14× for Light, 1.46×–2.01× for Full). The paper includes ablations of residual connections, attention pooling, activations, and a Bayesian signed-rank test with a ROPE of one F1 point.","tokens_in":13687,"tokens_out":4433,"duration_ms":42747,"significance":"If the results hold, LITEWAY is a useful contribution to lightweight HAR: the fully convolutional design avoids recurrent states, the parameter counts (6.5–6.7K) and MACs (0.99–1.8M) are remarkably low, and the evaluation spans 16 datasets with a careful subject-independent protocol and five seeds. The paper also provides public code, a detailed ablation study, and hardware measurements, which are strengths that facilitate reproducibility. The architectural ablations (residual placement, attention pooling, heterogeneous activations) give practical design insights. However, the significance is currently tempered by two load-bearing issues: an internal inconsistency in the deployment energy figures and an overstatement of the Bayesian comparison conclusions relative to the paper's own ROPE threshold.","major_comments":[{"comment":"The deployment section and Table 5 disagree on the LITEWAY-L row. The text states that LITEWAY Light requires \"only 37.44 ms per inference, 3% CPU load, and 2.90 mJ per inference,\" but Table 5 reports CPU load 30.54% and energy 32.90 mJ/Inf for the same model. The headline energy-reduction ratios in the abstract and §1 (2.29×–3.14× for Light, 1.46×–2.01× for Full) depend on these values. If the Table 5 value is correct, the ratios versus TinierHAR and MLP-HAR become 86.36/32.90 = 2.63× and 118.73/32.90 = 3.61×, neither falling within the stated range. Please reconcile the text and table, and recompute all efficiency claims (abstract, §1, §4.3.5, conclusion) with the corrected numbers. Also specify how CPU load is defined, whether energy includes idle/peripheral current, and how many inference cycles were averaged.","section":"§4.3.5 and Table 5"},{"comment":"The paper adopts a ROPE of one F1 point, then reports that the posterior probability of LITEWAY-F outperforming each baseline ranges from 0.59 to 0.86, and that no comparison crosses the 0.95 decision threshold. Yet the text concludes that the architecture is \"at least on par with, and most likely superior to, the SOTA baselines.\" Under the ROPE framework, a posterior probability of superiority below 0.95 does not justify claiming superiority; the correct conclusion is either practical equivalence (if substantial posterior mass lies inside the ROPE) or indecision. The aggregate differences (0.808–0.813 vs 0.801–0.807) are within the one-F1-point ROPE, so the claim \"LITEWAY Full achieves the highest macro F1-score\" and the abstract's wording require qualification. Please report the full posterior probabilities (superior, ROPE, inferior) for each baseline and adjust the conclusions and abstract accordingly.","section":"§4.4 Bayesian signed-rank test"},{"comment":"The paper states that all baselines are evaluated under the same training protocol (AdamW, initial learning rate 1e-3, up to 150 epochs, early stopping patience 15) to ensure a fair comparison, but it does not justify that this protocol is appropriate for each baseline. For example, TinierHAR and TinyHAR may have been originally tuned with different optimizers or schedules; applying a single protocol without per-dataset or per-model tuning can bias the accuracy comparison. Please provide evidence that the protocol is adequate for all models (e.g., report baseline performance under their originally recommended hyperparameters, or show sensitivity to learning rate/early stopping), or clearly state the protocol as a limitation.","section":"§4.1 Evaluation Protocol"}],"minor_comments":[{"comment":"The finding text contains a typo: \"divers datasets\" should be \"diverse datasets.\"","section":"§4.2.1"},{"comment":"The sentence \"we deploy them on the low-power STM32L4S5 microcontroller running at 120 MHz)\" has an unmatched closing parenthesis; please fix.","section":"§4.3.5"},{"comment":"The notation is inconsistent: the text and Table 5 use \"MLP-HAR,\" while Figure 3 uses \"MLPHAR.\" Please standardize.","section":"Figure 3 and Table 5"},{"comment":"The MAC and parameter reduction ratios (1.85×, 2.51×, 4.06×, etc.) do not state which baseline each ratio is relative to. Please clarify in the caption or legend.","section":"Figure 3 caption"},{"comment":"The column \"Cycles/MAC\" is not defined; specify whether it is cycles per multiply-accumulate measured on the STM32, and how it was obtained.","section":"Table 5"}],"recommendation":"major_revision","confidential_remarks":"The paper compares LITEWAY against several baselines, including TinierHAR and SPECTRA, which come from the same research group (and co-authors). This is not improper, but the manuscript would benefit from a sentence clarifying the relationship and any shared code/protocol. The deployment evaluation on a single STM32L4S5 board limits generality; the limitations section acknowledges this, but the abstract's energy claims should be reworded to reflect the single-platform measurement. The most urgent issue is the internal inconsistency between the text and Table 5; that must be resolved before the paper can be considered for publication."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short version: the architecture is real and the evaluation is broad, but the paper's central energy-savings claim is currently contradicted by its own deployment table, and the 'outperform' language is stronger than the Bayesian analysis supports.\n\nWhat's new: the SCTM block combines depthwise separable convolution, a shared pointwise projection with sigmoid/tanh gating, and a concatenated highway-style carry. The pieces are known, but the specific shared-gate formulation is a sensible parameter-saving move, and the fully convolutional design is a good fit for on-device HAR. The 16-dataset comparison with five seeds and released code is solid work; the per-dataset MAC/parameter breakdown is useful, and the size reductions (4-9x) are credible from the architecture.\n\nSoft spots: the stress-test note is on target. Section 4.3.5 says LITEWAY-L uses 3% CPU load and 2.90 mJ per inference; Table 5 lists 30.54% and 32.90 mJ for the same model. That is a 10x discrepancy. Neither value matches the abstract's 2.29x-3.14x energy reduction ratios. Because energy is a headline contribution, this inconsistency has to be resolved before the efficiency claim is repeatable. Second, the accuracy story is over-stated. The Bayesian test with a one-F1-point ROPE gives posterior probabilities of 0.59-0.86 for 'better than baseline,' which supports 'on par, likely ahead,' not 'outperform' as written in the abstract and Section 4.2.2. The authors deserve credit for running the Bayesian test, but they should let its conclusion drive their wording. Minor: CPU load is never defined, and the single-MCU limitation is acknowledged but not discussed in the conclusion.\n\nBottom line: this is a useful incremental paper for the HAR community. The architecture is interesting enough to referee, and the evaluation is reproducible enough to justify the work. Send it to review, but ask the reviewers to verify the deployment measurements and to recommend a softer accuracy claim.","headline":"Solid incremental architecture and a wide evaluation, but the energy-savings headline is unsupported by the paper's own deployment table.","tokens_in":14208,"tokens_out":3119,"would_cite":true,"duration_ms":30233,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A fully convolutional architecture for wearable HAR matches recurrent models while shrinking model size 4–9.5x and cutting measured energy on a low-power microcontroller.","keywords":["human activity recognition","wearable sensors","fully convolutional network","structured temporal modeling","edge AI","model efficiency","time series classification","microcontroller deployment"],"falsifier":"Re-measure LITEWAY Light on the same STM32L4S5 board at 120 MHz with the X-NUCLEO-LPM01A power shield, averaging energy over the same 16 inference cycles; if per-inference energy is 32.90 mJ rather than 2.90 mJ, the claimed 2.29x–3.14x energy reduction over TinierHAR and MLP-HAR does not hold.","tokens_in":13196,"feed_emoji":"⚡","tokens_out":5444,"duration_ms":44179,"temperature":0.7,"pith_summary":"The paper proposes LITEWAY, a fully convolutional framework for wearable human activity recognition that replaces recurrent layers with a structured convolutional temporal modeling block. Across 16 datasets it reports macro F1 of 0.808 for the Light variant and 0.813 for the Full variant, slightly above the compared baselines, while cutting model size by a factor of 4.06x–9.52x and energy per inference by up to about 3x on a low-power microcontroller. The claim matters because it suggests that efficient on-device HAR does not require recurrent networks, whose sequential computation limits parallelism on wearable hardware. The paper also reports a Bayesian signed-rank test indicating LITEWAY is at least on par with, and likely better than, the lightweight baselines while being substantially smaller.","feed_headline":"Convolution-only HAR shrinks model 9.5x and stays accurate","feed_subtitle":"Replacing RNNs with shared-projection gated convolutions keeps macro F1 while using far less energy.","key_machinery":"The load-bearing component is the Structured Convolutional Temporal Modeling (SCTM) block, a parameter-efficient module for long-range temporal dependencies that contains no recurrence. SCTM first applies a depthwise temporal convolution followed by a pointwise activation, then a single shared pointwise projection $Z=W_p(H)$. From $Z$ it builds two complementary signals: a collapsed Gated Tanh Unit, $\\sigma(Z)\\odot\\tanh(Z)$, and a highway-style carry gate, $(1-\\sigma(Z))\\odot W_p(X)$, where $X$ is the block input. The two streams are concatenated rather than added, following the split-transform-merge idea. Sharing one projection across both gating pathways is what keeps parameters low compared with standard gated or recurrent blocks.","core_discovery":"On the paper's own terms, the central discovery is that a fully convolutional architecture with a dedicated structured temporal modeling module can match or slightly exceed the recognition accuracy of recurrent and hybrid HAR models while using far fewer parameters and multiply-accumulate operations. The evidence is a 16-dataset comparison against TinyHAR, TinierHAR, MLP-HAR, and DeepConvLSTM, plus deployment measurements on an STM32L4S5 microcontroller. LITEWAY Light averages 0.808 macro F1 with 6.5K parameters and 988.8K MACs; LITEWAY Full averages 0.813 with 6.7K parameters and 1.8M MACs, placing both in a lower-cost regime than the baselines on the accuracy–efficiency frontier.","pith_inferences":["The paper's own deployment numbers are inconsistent: the text reports 2.90 mJ and 3% CPU for LITEWAY-L while Table 5 lists 32.90 mJ and 30.54%; the energy-reduction factors should be treated as provisional until this is resolved.","Because all efficiency numbers come from a single STM32L4S5 board and toolchain, the 2–3x energy advantage may not transfer to other microcontrollers; LITEWAY's cycles/MAC is actually higher than some baselines, so the advantage rests entirely on its low MAC count.","The same training protocol without per-dataset tuning is asserted to be fair to all baselines; a testable extension is to sweep key hyperparameters per baseline on a subset of datasets and re-check the accuracy rankings."],"forward_implications":["If LITEWAY's results hold, recurrent layers are not necessary for competitive wearable HAR accuracy; convolution-only temporal modeling suffices.","The reported parameter reductions (4.06x–9.52x vs TinyHAR and TinierHAR) would make on-device deployment feasible on microcontrollers with only a few tens of KiB of memory.","The energy reductions (2.29x–3.14x for Light, 1.46x–2.01x for Full vs TinierHAR and MLP-HAR) point to longer battery life for continuous sensing, if replicated on other hardware.","The method is modality-agnostic, so the same architecture applies to accelerometer, gyroscope, magnetometer, or fused sensor streams without per-sensor redesign."],"supporting_citations":[{"why":"TinierHAR is one of the primary lightweight baselines that LITEWAY is compared against for accuracy, size, and energy.","marker":"[9]"},{"why":"TinyHAR provides the other main lightweight baseline and the recurrent-style efficiency target LITEWAY aims to beat.","marker":"[43]"},{"why":"MLP-HAR is a fully connected baseline whose accuracy and deployment efficiency LITEWAY claims to match or improve while using fewer resources.","marker":"[42]"},{"why":"DeepConvLSTM supplies the standard CNN-RNN hybrid baseline that motivates the shift away from recurrent temporal modeling.","marker":"[22]"},{"why":"MobileNets is the source of depthwise separable convolutions, the core parameter-efficiency principle underlying SCTM.","marker":"[17]"},{"why":"Highway networks provide the carry-gate formulation that SCTM adapts into its complementary pathway.","marker":"[30]"},{"why":"Gated convolutional networks supply the gated linear unit and gated tanh concepts that SCTM collapses into a single shared projection.","marker":"[14]"},{"why":"The Bayesian classifier-comparison tutorial grounds the signed-rank test that the paper uses to claim LITEWAY is on par with or better than baselines.","marker":"[7]"}],"fun_headline_variants":["LITEWAY: convolutional HAR cuts model size up to 9.5x","Fully convolutional HAR matches RNN accuracy at 9x less size","No RNNs: LITEWAY HAR is 9.5x smaller with equal F1","Convolution-only wearable HAR: 9x smaller, same accuracy","LITEWAY: efficient HAR via convolutional temporal modeling"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The energy and CPU savings are taken from a single deployment measurement on one microcontroller, and the paper reports two conflicting values for the same LITEWAY-L run: 2.90 mJ and 3% CPU in the text versus 32.90 mJ and 30.54% in Table 5.","fun_headline_variants_meta":{"raw":{"variants":["LITEWAY: convolutional HAR cuts model size up to 9.5x","Fully convolutional HAR matches RNN accuracy at 9x less size","No RNNs: LITEWAY HAR is 9.5x smaller with equal F1","Convolution-only wearable HAR: 9x smaller, same accuracy","LITEWAY: efficient HAR via convolutional temporal modeling"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.00062,"raw_usage":{"total_tokens":2880,"prompt_tokens":955,"completion_tokens":1925,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":571,"completion_tokens_details":{"reasoning_tokens":1823}},"tokens_in":571,"tokens_out":1925,"duration_ms":16232,"temperature":1.0,"reasoning_tokens":1823,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-11T17:38:03.321071+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Re-measure LITEWAY Light on the same STM32L4S5 board at 120 MHz with the X-NUCLEO-LPM01A power shield, averaging energy over the same 16 inference cycles; if per-inference energy is 32.90 mJ rather than 2.90 mJ, the claimed 2.29x–3.14x energy reduction over TinierHAR and MLP-HAR does not hold.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"TinierHAR is one of the primary lightweight baselines that LITEWAY is compared against for accuracy, size, and energy."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"MLP-HAR is a fully connected baseline whose accuracy and deployment efficiency LITEWAY claims to match or improve while using fewer resources."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Highway networks provide the carry-gate formulation that SCTM adapts into its complementary pathway."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Gated convolutional networks supply the gated linear unit and gated tanh concepts that SCTM collapses into a single shared projection."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"The Bayesian classifier-comparison tutorial grounds the signed-rank test that the paper uses to claim LITEWAY is on par with or better than baselines."}],"review_version":1}