{"id":"d7e35db3-70a8-4392-8070-71589a6be164","arxiv_id":"2608.09508","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"Wafer-scale three-tier monolithic 3D integration of ALD indium oxide transistors (Fe-FET, E-mode, D-mode) is demonstrated on 200 mm wafers, plus a simulated four-tier CIM design that projects 1.4x to 2.9x speedup over a 2D baseline.","lead":"Engineers stacked three tiers of atomic layer deposited indium oxide transistors on 200 mm silicon wafers and showed the layers work together in cross-tier logic and memory circuits. The work is a step toward building compute and memory vertically, a path that could give AI hardware a speed and energy boost without relying only on transistor shrinking.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The four-tier CIM speedup rests on an unreleased in-house simulator and a same-footprint 2D baseline that may not be resource-matched; the experimental M3D claim itself survives.","rationale":"The paper's strongest claims—wafer-scale three-tier ALD InOx integration, low threshold-voltage variation, and functional cross-tier circuits—are backed by large sample statistics and direct measurements, so the central fabrication result appears solid. The reader's conditional verdict correctly locates the primary risk in the four-tier CIM accelerator speedup. My concern overlaps with the reader's weakest_assumption but sharpens it: the 2D baseline defined in the Methods section makes the speedup hard to interpret because the same-footprint constraint gives the four-tier 3D design much more active area, and the simulator and PDK are not independently checkable. The paper itself acknowledges the projected nature of the CIM results in the Conclusions, which supports a conditional rather than an acceptance or rejection verdict. No fabrication-level inconsistency was identified, and the reader's conditional verdict should stand unchanged.","tokens_in":13027,"tokens_out":5103,"duration_ms":50736,"concrete_test":"Release the calibrated OS-PDK and 3D-CIMlet framework, or independently rebuild the benchmark with an open-source circuit/architecture simulator, and rerun the GPT-2 and BERT-small workloads under two 2D baselines: (A) same footprint as the 3D design, as in the paper; (B) same total logic-gate count and FeFET/eDRAM capacity as the 3D design, allowing a larger planar footprint. If the speedup over baseline (B) falls below the claimed 1.4x–2.9x range, the headline advantage is an artifact of the unequal-resource baseline rather than a verified M3D benefit.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The experimental core—three tiers of ALD InOx FETs and Fe-FETs on 200 mm wafers with more than 100,000 devices and cross-tier circuits—is statistically supported and is not the weak point. The load-bearing weakness is the system-level claim in the abstract: 'A four-tier 3D computing-in-memory (CIM) accelerator ... delivering 1.4x to 2.9x speedup...' This is not a fabricated chip. The Methods section, 'System simulation and benchmarking,' states that the 2D baseline is 'a planar oxide-semiconductor implementation constrained to the same chip footprint, FeFET/eDRAM composition ratio, and workload-mapping strategy as the 3D design.' Because the 3D macro stacks four tiers, the same-footprint constraint gives the 3D design roughly four times the active area; the 1.4–2.9x speedup may therefore reflect added capacity and density rather than an intrinsic performance-per-resource advantage. The framework (3D-CIMlet, ref. 55) and the custom OS-PDK are not released for independent checking, and the paper itself concedes in the Conclusions that 'Larger hardware demonstrations are also needed to validate the projected computing-in-memory performance and energy efficiency.' Thus the abstract's unqualified 'delivering' overstates what is a projected, unverified simulation result. This does not invalidate the wafer-scale integration claim, but it underdetermines the 'next-generation artificial intelligence hardware' conclusion.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"This paper reports wafer-scale monolithic 3D (M3D) integration of three tiers of atomic-layer-deposited (ALD) InOx-based devices on 200 mm silicon wafers, including ferroelectric (Fe-FET), enhancement-mode (E-mode), and depletion-mode (D-mode) field-effect transistors. The authors present statistical characterization of over 100,000 fabricated devices, achieving threshold-voltage standard deviation as low as 0.04 V, average mobility up to 91.6 cm2/V·s, and fully functional cross-tier circuits including multi-level ferroelectric nonvolatile memories (MLFe-NVMs), inverters, and 2T0C eDRAMs. The paper also describes a four-tier 3D computing-in-memory (CIM) accelerator design for large-language-model workloads, implemented with a custom InOx process design kit and evaluated with an in-house simulation framework, with a claimed 1.4x to 2.9x speedup and comparable energy-delay-product improvements over a same-footprint 2D baseline.","tokens_in":13382,"tokens_out":7431,"duration_ms":62774,"significance":"If the experimental claims are confirmed, this work represents a notable advance in BEOL-compatible M3D integration. The paper's main strength is the substantial statistical data: more than 300 devices per tier across 52 dies, wafer-scale Vth maps, and functional cross-tier circuits, which support the scalability and uniformity claims. The CIM accelerator projection is forward-looking but is a simulation-based case study rather than a fabricated chip; its credibility rests on the calibration of the custom PDK and the fairness of the baseline, both of which require more transparency. The explicit limitation statement in the Conclusions is a positive sign, but the abstract's unqualified 'delivering' overstates the evidence.","major_comments":[{"comment":"The 1.4–2.9x speedup claim is a projected simulation result from an in-house framework (3D-CIMlet, ref. 55) and a custom OS-PDK, not a measurement of a fabricated four-tier chip. The abstract's wording 'delivering' should be qualified as 'projected' or 'simulated' to avoid overstating the evidence. Furthermore, the Methods define the 2D baseline as 'a planar oxide-semiconductor implementation constrained to the same chip footprint, FeFET/eDRAM composition ratio, and workload-mapping strategy.' Because the 3D macro stacks four tiers, this same-footprint constraint gives the 3D design roughly four times the active device area; the speedup therefore reflects at least in part increased resource density rather than an intrinsic per-device performance advantage. Please present a resource-matched comparison (e.g., equal total device area or equal memory capacity) or explicitly discuss the sensitivity of the speedup to this baseline definition.","section":"Abstract; 'Indium oxide multi tier computing in memory accelerator'"},{"comment":"The OS-PDK is calibrated from measured devices with channel lengths of 5 um (Fig. 2e) and 100 nm (Fig. 2a), yet the CIM design is implemented at the 40 nm technology node. The scaling methodology used to extrapolate the Verilog-A models from the measured devices to 40 nm (e.g., constant-field scaling, adjustment of mobility, Vth, and parasitic capacitances) is not described. Since the projected speedup and EDP depend on these scaled parameters, please provide the scaling rules or perform a sensitivity analysis over the assumed 40 nm device parameters.","section":"Methods, 'System simulation and benchmarking'"},{"comment":"The statement that 'the devices fabricated on the top tiers exhibit no performance degradation compared to those on the lower tiers' is not supported by a controlled comparison. The Tier-1 devices are Fe-FETs with HZO dielectric and 400°C annealing, Tier-2 devices are E-mode FETs, and Tier-3 devices are D-mode FETs with a thicker InOx channel; these differ in device type, dielectric, and channel thickness, so the observed differences in Vth and mobility cannot isolate the effect of tier level. A direct comparison of the same device type fabricated at Tier 1 and Tier 3 would substantiate the thermal-budget compatibility claim; otherwise the claim should be softened to 'remain functional.'","section":"Device characterizations of multi-tier ALD InOx transistors (Fig. 3)"},{"comment":"The eDRAM is described as 'refresh-free' with 'ultra-long retention,' but no quantitative retention time is reported in the main text. The retention characteristic in Fig. 4j shows a large on/off ratio, but the time scale and the criterion for a valid logic '1' are not stated. Please report the measured retention time (e.g., the time for the read current to degrade to a specified sense margin) and specify the refresh-free condition used in the CIM design.","section":"Cross tier integrated circuits and memory; 'Indium oxide multi tier computing in memory accelerator'"}],"minor_comments":[{"comment":"The list of sample sizes (n = 19, 19, 21, 20, ...) would be clearer if the corresponding channel lengths were explicitly mapped in the caption, as the current list is ambiguous without the figure.","section":"Fig. 2c caption"},{"comment":"The terms 'E-mode' and 'D-mode' are used without definition; please define them as enhancement-mode (normally off) and depletion-mode (normally on) at first use.","section":"Abstract and introduction"},{"comment":"The paper notes that heat transport cannot be inferred directly from two-dimensional circuits, yet the system-level simulation does not include thermal effects; please state the thermal assumptions (e.g., uniform temperature, no inter-tier thermal coupling) in the simulation section.","section":"Conclusions; Methods, 'System simulation and benchmarking'"},{"comment":"The MLFe-NVM description mentions 'n x m storage levels' but does not specify the demonstrated n and m values for the multi-level operation in Figs. 4b-4c; please clarify the number of distinct levels achieved.","section":"Cross tier integrated circuits and memory"},{"comment":"Some references have inconsistent formatting (e.g., conference series names and years); please check for consistency (e.g., refs. 35, 38, 40).","section":"References"}],"recommendation":"major_revision","confidential_remarks":"The experimental M3D integration part is strong and likely publishable in an applied-physics venue. The main reservation is the system-level CIM claim, which is a simulation projection based on an unreleased framework and an unvalidated 40 nm extrapolation; the abstract overstates this as 'delivering.' The authors should either temper the claim or add sensitivity/resource-matched analyses. The journal may also consider whether the paper's scope fits: it is primarily a device/integration demonstration with a system-level case study, which is acceptable but the system part needs more rigor. The paper would benefit from releasing the framework or providing detailed benchmark parameters for reproducibility."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"This paper deserves a serious referee. The experimental core is the real contribution: wafer-scale 200 mm monolithic 3D integration of ALD InOx, with three tiers of Fe-FET, E-mode, and D-mode devices, over 100,000 fabricated, tight Vth distributions (sigma down to 0.04 V), and functional cross-tier circuits (MLFe-NVMs, inverters, eDRAMs) across 52 dies. That is a genuine step beyond prior single-device or small-scale demos, and the statistical characterization is unusually thorough for a process paper. The TEM/EDS cross-section corroborates the stacked architecture. I buy the fabrication claims.\n\nThe soft spot is exactly where the stress-test note lands: the 1.4x–2.9x speedup for the four-tier CIM accelerator comes from the authors' in-house 3D-CIMlet framework and a custom PDK, not from a fabricated chip. The Methods section defines the 2D baseline as a planar implementation 'constrained to the same chip footprint, FeFET/eDRAM composition ratio, and workload-mapping strategy' as the 3D design. Because the 3D macro stacks four tiers, that same-footprint constraint gives it about four times the active area. The speedup may therefore reflect added capacity/density rather than an intrinsic performance-per-resource advantage. The paper's own Conclusions concede that larger hardware demonstrations are needed to validate the projected CIM performance. So the abstract's 'delivering' overstates; it should read 'projected' or 'simulated'. This is addressable framing, not a fatal flaw.\n\nMinor point: the overlay curves in Fig. 2 exclude outliers 'to facilitate visualization.' That is fine, but the text should confirm the statistics include those points. Sample sizes are given, so the effect is cosmetic.\n\nThe citation pattern is reasonable: prior InOx and Fe-FET work, recent BEOL-compatible channels, and M3D integration of other materials are covered. The self-cited simulation framework is flagged as in-house and not released, which is a limitation, not a concealment.\n\nThis paper is for the oxide-semiconductor and 3D-integration community. The experimental result is the contribution; the simulation is a bonus that needs qualification. I would send it to peer review with a request to fix the CIM claims and clarify the baseline. Not a desk reject.","headline":"Solid wafer-scale M3D experimental core; the CIM speedup is an unverified simulation that needs qualified language.","tokens_in":13892,"tokens_out":2361,"would_cite":true,"duration_ms":18678,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":["85.30.Tv","81.15.Gh","85.50.-n"],"model":"deepseek-v4-flash","headline":"This paper reports wafer-scale monolithic 3D integration of three tiers of ALD InOx transistors on 200 mm silicon, with cross-tier circuits and a simulated four-tier LLM accelerator projecting 1.4x to 2.9x speedup.","keywords":["monolithic 3D integration","atomic layer deposition","indium oxide transistors","ferroelectric FET","BEOL compatibility","computing-in-memory","LLM accelerator","200 mm wafer"],"falsifier":"Fabricate a four-tier InOx stack using the same process flow and run the LLM inference benchmark against the same-footprint 2D baseline; if the measured speedup falls below 1.4x or the energy-delay product is worse than the planar design, the central system-level projection fails. A simpler check is to measure whether the Tier 1 Fe-FET memory window and the Tier 2 and Tier 3 mobility survive processing of a fourth tier, since any degradation would invalidate the repeatable-stacking claim.","tokens_in":12856,"feed_emoji":"🧩","tokens_out":10219,"duration_ms":674970,"temperature":0.7,"pith_summary":"The paper's aim is to establish that atomic-layer-deposited (ALD) indium oxide ($\\mathrm{InO_x}$) transistors can serve as the building block of monolithic 3D integrated circuits: devices are grown directly on top of one another on a 200 mm silicon wafer at temperatures low enough to be back-end-of-line (BEOL) compatible, and the lower tiers keep working after each new tier is added. It reports more than 100,000 devices in three stacked tiers—ferroelectric Fe-FETs, enhancement-mode FETs, and depletion-mode FETs—with threshold-voltage standard deviation as low as $0.04$ V and average electron mobility up to $91.6\\ \\mathrm{cm^2\\,V^{-1}s^{-1}}$. Using those devices it builds cross-tier circuits: multi-level ferroelectric nonvolatile memory, inverters, and two-transistor zero-capacitor eDRAM cells. It also projects a four-tier computing-in-memory accelerator for large language models with $1.4\\times$ to $2.9\\times$ speedup over a planar baseline of the same footprint. If these results hold, they establish a scalable route to vertical transistor stacking, one of the main options for continuing performance gains after planar CMOS scaling slows.","feed_headline":"Oxide transistors stack in three functional layers on 200 mm wafers","feed_subtitle":"ALD-grown InOx delivers Fe-FETs, logic, and eDRAM across tiers with threshold spread down to 0.04 V.","key_machinery":"The load-bearing element is the ALD $\\mathrm{InO_x}$ transistor: a roughly 225 $^\\circ$C deposited amorphous oxide channel whose threshold voltage can be placed wherever the designer needs it—enhancement or depletion—by choosing channel thickness and oxygen annealing. This one tunable device type replaces both pull-up and pull-down elements in an NMOS-only logic style, with depletion-mode loads and enhancement-mode switches. The same channel, paired with ferroelectric $\\mathrm{HfZrO_2}$ (HZO), forms the Fe-FETs that provide nonvolatile memory. The measured device data feed a custom process design kit and an in-house model-to-chip mapping framework, which is what turns the three-tier fabrication result into the four-tier CIM accelerator projection.","core_discovery":"The paper's central claim is that wafer-scale monolithic 3D integration works with ALD-grown amorphous indium oxide channels. The authors show three tiers—Fe-FETs at the bottom, enhancement-mode FETs in the middle, and depletion-mode FETs on top—all fabricated on the same 200 mm wafer, and they quantify uniformity across the wafer: threshold-voltage spreads down to $0.04$ V, memory windows averaging $2.18$ V, and mobilities of $63.5$ to $91.6\\ \\mathrm{cm^2\\,V^{-1}s^{-1}}$ depending on tier and thickness. The top-tier devices show no degradation relative to the bottom tier, which is the prerequisite for stacking more tiers. With the same three tiers, the paper demonstrates fully functional cross-tier circuits, so that logic and memory are not just co-located vertically but actually connected through inter-layer vias. The final claim is system-level: using a custom InOx process design kit and a three-dimensional design flow, a four-tier computing-in-memory accelerator for transformer-based LLMs partitions static weights into ferroelectric NVM and dynamic attention computations into eDRAM, and is projected to deliver $1.4\\times$ to $2.9\\times$ speedup and comparable energy-delay-product improvement over a same-footprint planar implementation.","pith_inferences":["The four-tier CIM speedup is a simulation result, not a measured chip; until a four-tier part is fabricated and benchmarked, the 1.4x to 2.9x range should be treated as a calibrated projection rather than a demonstrated speedup.","If the wafer-level uniformity and cross-tier yields reproduce in a commercial fab, ALD InOx M3D could lower the cost of 3D integration relative to wafer bonding, because it avoids high-temperature epitaxy and transfer steps.","The multi-level Fe-NVM cell stores n voltage levels times m polarization states; testing whether these levels stay separable under cycling, retention, and read disturb would directly probe whether that extra dimension is practical for analog in-memory computing.","Because the authors note the layout is not yet optimized for parasitic capacitance and coupling, reducing those parasitics should improve cross-tier circuit margins and may push the projected speedup beyond the lower bound."],"forward_implications":["The 200 mm process establishes ALD InOx as a candidate BEOL channel with the uniformity ($V_{th}$ sigma down to 0.04 V) and yield needed for wafer-scale manufacturing.","Cross-tier inverters, Fe-NVMs, and eDRAMs show that logic and memory can be interconnected vertically, not just stacked, so dense 3D systems-on-wafer become possible.","Because the top-tier devices show no degradation, the same process can in principle be repeated to add a fourth, fifth, or more tiers.","The CIM accelerator projection implies that splitting LLM workloads between static Fe-NVM and dynamic eDRAM tiers could cut inference latency by 1.4x to 2.9x relative to a planar implementation of the same footprint.","NMOS-only logic built from E-mode and D-mode InOx FETs gives a complete standard-cell library, so existing 2D physical-design tools can be reused for a tier-by-tier 3D flow."],"supporting_citations":[{"why":"Supplies the ALD InOx transistor platform—scaled, high-performance devices—that every tier of the stack is built from.","marker":"[21]"},{"why":"Explains why ultrathin In2O3 maintains transistor action, supporting the use of 1.8 nm channels for low threshold-voltage spread.","marker":"[20]"},{"why":"Prior demonstration of BEOL all-ALD channel FETs that this work extends to a three-tier 200 mm platform.","marker":"[11]"},{"why":"Establishes amorphous oxide semiconductors as a monolithic 3D integration channel, the framework within which the paper positions itself.","marker":"[5]"},{"why":"Provides the BEOL-compatible ALD In2O3 Fe-FET baseline with large memory window that the Tier 1 devices build on.","marker":"[30]"},{"why":"Provides the model-to-chip mapping framework used to evaluate the 3D LLM accelerator and produce the 1.4x to 2.9x speedup numbers.","marker":"[55]"},{"why":"Benchmark showing a 300 mm fab achieving sub-40 mV threshold-voltage sigma for IGZO, against which the paper's 0.04 V sigma is compared.","marker":"[40]"}],"fun_headline_variants":["Oxide transistors stack in 3 tiers on 200 mm","Wafer-scale 3D oxide chips: logic + memory stacked","Atomic-layer oxide transistors go monolithic 3D","3D oxide transistors: 0.04 V spread, 2.9x AI speedup","Stacked oxide transistors enable 3D computing-in-memory"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that the custom simulation framework and process design kit, calibrated to measured single-tier devices, faithfully predict the performance of a four-tier chip that was never fabricated.","fun_headline_variants_meta":{"raw":{"variants":["Oxide transistors stack in 3 tiers on 200 mm","Wafer-scale 3D oxide chips: logic + memory stacked","Atomic-layer oxide transistors go monolithic 3D","3D oxide transistors: 0.04 V spread, 2.9x AI speedup","Stacked oxide transistors enable 3D computing-in-memory"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000296,"raw_usage":{"total_tokens":1765,"prompt_tokens":1041,"completion_tokens":724,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":657,"completion_tokens_details":{"reasoning_tokens":632}},"tokens_in":657,"tokens_out":724,"duration_ms":7001,"temperature":1.0,"reasoning_tokens":632,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-11T15:57:01.513479+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Fabricate a four-tier InOx stack using the same process flow and run the LLM inference benchmark against the same-footprint 2D baseline; if the measured speedup falls below 1.4x or the energy-delay product is worse than the planar design, the central system-level projection fails. A simpler check is to measure whether the Tier 1 Fe-FET memory window and the Tier 2 and Tier 3 mobility survive processing of a fourth tier, since any degradation would invalidate the repeatable-stacking claim.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the ALD InOx transistor platform—scaled, high-performance devices—that every tier of the stack is built from."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Explains why ultrathin In2O3 maintains transistor action, supporting the use of 1.8 nm channels for low threshold-voltage spread."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Establishes amorphous oxide semiconductors as a monolithic 3D integration channel, the framework within which the paper positions itself."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the BEOL-compatible ALD In2O3 Fe-FET baseline with large memory window that the Tier 1 devices build on."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the model-to-chip mapping framework used to evaluate the 3D LLM accelerator and produce the 1.4x to 2.9x speedup numbers."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Benchmark showing a 300 mm fab achieving sub-40 mV threshold-voltage sigma for IGZO, against which the paper's 0.04 V sigma is compared."}],"review_version":1}