{"id":"3d711f0f-5ec7-45f0-ad87-a025e3acade6","arxiv_id":"2608.09733","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"Aicir is a full-stack quantum circuit simulator with a native Huawei Ascend NPU backend, using paired real tensors and fixed-rank gate views, validated with CPU fallback disabled.","lead":"Aicir is a new full-stack quantum circuit simulator that runs natively on Huawei Ascend NPUs, using paired real tensors and fixed-rank gate views to work around missing complex-number kernels. The paper validates this NPU path with CPU fallback disabled and reports CPU performance comparable to Qiskit Aer and Cirq on fused layered circuits.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Native-execution validation depends on the completeness of an unverified interception list; device-level profiling would settle it.","rationale":"The reader's weakest assumption identifies exactly this: the completeness of the interception list is internal and not independently auditable. I agree that this is the most load-bearing concern because it directly threatens the truth of the central claim, not just its reproducibility. The paper is unusually careful: it explicitly distinguishes validated paths from capabilities without such records, and it avoids overclaiming speedup or scaling. It even documents a real silent host fallback that the interception mechanism was designed to catch. That honesty makes the concern precise rather than speculative: the validation protocol is only as strong as the manually curated list of host-only paths, and no evidence in the preprint shows that the list is exhaustive for the tested workloads. A device-level profiling test would settle the matter definitively. If every operation in the reported runs is confirmed to execute on the NPU, the native-execution claim holds for those workloads; if any host kernel appears, the claim is false for that path. The same test would confirm that the interception list is complete enough to catch injected counterexamples. The reader's CONDITIONAL verdict already captures this: conditional on independent audit of the native-execution mechanism and on exact version reproducibility. My analysis does not change that verdict, so I recommend UNCHANGED.","tokens_in":29905,"tokens_out":5333,"duration_ms":42177,"concrete_test":"Run the reported sparse-Pauli workload (n=20) and a representative distributed gradient run under CANN's device-side profiler (e.g., msprof or torch_npu profiling), and enumerate all executed kernels. Verify that every tensor operation (matmul, elementwise, reduce, cast, scatter/gather, SVD, etc.) is issued to an NPU kernel (AICore) and that no operation is dispatched to a host-side CPU kernel (e.g., MKL, Eigen, or libc++ routines). Separately, inject an unsupported operation that is not on the interception list (for instance, a complex-valued torch.linalg.cholesky or a Python-level bit shift) into the same workload and confirm that the validation correctly fails; if the run passes, the interception mechanism is incomplete and the native-execution claim is not established.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim that the experiments establish native NPU execution rests on the validation protocol in Sections 5.3 and 9.3: run with fallback_to_cpu=false and intercept operations so that a run fails if it requests a known host-only path. This is only sound if the interception list covers every operation used in the tested workloads. The paper itself provides a concrete counterexample: the earlier Pauli implementation used a bitwise shift that silently executed on the host, produced a correct output tensor, and was caught only after the authors knew to look (Section 5.3). That demonstrates that checking the returned tensor is insufficient and that the interception list is a manually curated set. Any operation outside this list—e.g., an index table computation, a reduction, a dtype cast, or a complex op emulated by the runtime without raising—would make the native claim false for that path while the validation still passes. The paper honestly narrows the claim to the 'validated backend surface' and says a workflow is covered only when each numerical operation belongs to that surface, but the completeness of the list is not independently audited in the preprint, and no commit hash is provided to audit it. Thus the strongest claim is only as strong as this unverified assumption.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents Aicir, a quantum circuit simulator with a native Huawei Ascend NPU backend. It spans circuit construction, state-vector, density-matrix, tensor-network, and MPS engines, measurement, differentiation, variational algorithms, quantum machine learning, quantum architecture search, and distributed state simulation. The NPU backend uses paired real tensors, fixed-rank gate views, and hardware-specific formulas to keep state operations on the device, and the paper validates native execution by disabling CPU fallback and intercepting operations. CPU benchmarks against Qiskit Aer, Cirq, Qiskit referenceStatevector, and PennyLane are reported, along with NPU correctness runs and distributed gradient/communication checks on 2, 4, and 8 NPUs. The abstract and conclusion state that Aicir's CPU runtime is within 0.97--1.28x of Aer and 0.76--1.10x of Cirq for the tested fused layered circuits, and that the NPU tests establish correct native execution without claiming CPU-to-NPU speedup.","tokens_in":30155,"tokens_out":8110,"duration_ms":58686,"significance":"If the claims hold, Aicir fills a real gap: a full-stack simulator with a native Ascend NPU backend, validated with a machine-checkable protocol rather than mere tensor placement checks. Strengths include the explicit scoping of validated paths, independent gradient oracles (parameter-shift and finite difference), a machine-checked communication contract for distributed runs, and honest reporting of both favorable and unfavorable benchmark results. The paper also contributes a detailed account of NPU-specific numerical constraints and their design response. The main risk is that the native-execution validation relies on the completeness of a manually curated interception list, which is a limitation made explicit in the text but not independently audited; this is a methodological concern rather than an internal inconsistency.","major_comments":[{"comment":"The native-execution claim rests on the completeness of the host-only path interception list. The paper's own bitwise-shift Pauli incident (Section 5.3) shows that an operation can silently execute on the host, produce a correct output tensor, and evade checks based on tensor placement; the interception list is therefore a manually curated set whose completeness is assumed. Since Section 11 states that the experiments 'establish native NPU execution,' I recommend either (i) adding device-level profiling evidence (e.g., Ascend profiling traces showing kernel execution on the device for the representative workloads) or (ii) softening the conclusion to say that the experiments validate native execution for the interception-covered operations, with the completeness assumption explicitly listed as a limitation.","section":"Section 5.3 and Section 11"}],"minor_comments":[{"comment":"Please provide a commit hash or exact version identifier for the Aicir release that was measured; the open-source URL alone does not pin the code state and prevents independent reproduction of the reported numbers.","section":"Appendix B"},{"comment":"The 'Qiskit' column in Table 9 corresponds to Qiskit's referenceStatevector path, not the Aer simulator; the table caption should state this explicitly to avoid confusion with the Aer column.","section":"Section 9.2, Table 9"},{"comment":"The first row of Table 13 reports '0.0 (at most 2.4×10^-7)', which is ambiguous; please clarify whether the maximum observed error is exactly 0.0 or up to 2.4×10^-7, and state how the two values were obtained.","section":"Section 9.4, Table 13"},{"comment":"The claim that constructing gate matrices at the widest precision 'reduced the norm deviation of a nominally double-precision path from about 10^-8 to 10^-16' would benefit from a brief description of the test circuit and measurement procedure so that the reader can assess the relevance of this improvement.","section":"Section 5.2"}],"recommendation":"minor_revision","confidential_remarks":"The paper is within the journal's scope as a quantum software and simulation contribution. The central contribution is sound and the reporting is unusually transparent about scope and limitations. The native-execution validation concern is real but the paper already scopes its claim; the requested clarification or profiling evidence is a local fix. The lack of a versioned code snapshot in Appendix B is a reproducibility gap that should be addressed before publication."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short version: this is an honest, well-scoped systems paper. The genuinely new thing is a full-stack simulator with a native Ascend NPU backend, validated with CPU fallback disabled on real hardware. The authors don't oversell it: they explicitly say the NPU tests establish correct execution, not speedup, and they keep CPU numbers separate.\n\nWhat it does well: the backend design is sensible. Paired real tensors and fixed-rank gate views are adaptations of known ideas, but the integration is real and the validation is more careful than most. They check endianness and gate-count conventions before timing, separate construction from execution, pin threads, report BLAS, and retain unfavorable results (Aicir is 3.9x slower than Aer on random circuits). The distributed differentiation checks against parameter-shift and finite differences are the right kind of evidence. The paper also ships a detailed API appendix and reproducibility records, though no commit hash.\n\nSoft spots: the central \"native NPU execution\" claim rests on the completeness of the interception list in Section 5.3. The paper itself gives the strongest counterexample: an earlier Pauli implementation silently executed a bitwise shift on the host, returned a correct tensor, and was caught only because the authors knew to look. That means the validation protocol is necessary but not sufficient unless the interception list is exhaustive, and that list is not independently auditable from the preprint. No commit hash or attached benchmark logs are provided, so the exact measured version isn't reproducible from the arXiv alone. These are addressable conditions, not evidence of a flawed result. The QAS weights are hand-chosen, but they aren't used to support the central claim. Also the CPU comparison only covers one workload family for the sweep; that's fine given the scope.\n\nWho it's for: people working on quantum simulator infrastructure or the Ascend/NPU ecosystem. It won't change anyone's view of quantum algorithms. I'd send it to a serious referee—it deserves a real review rather than a desk reject. If the authors add a commit hash and an audited fallback-detection test, the native-execution claim becomes much stronger.","headline":"A careful, honestly scoped systems paper: native Ascend NPU simulation that doesn't oversell speedups, with a validation hole around fallback-detection completeness that the authors themselves document.","tokens_in":30656,"tokens_out":2045,"would_cite":true,"duration_ms":17097,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":["81P68"],"pacs":["03.67.Lx"],"model":"deepseek-v4-flash","headline":"Aicir claims to be the first full-stack quantum circuit simulator with a native Ascend NPU backend, validated without CPU fallback on up to eight NPUs.","keywords":["quantum circuit simulator","Ascend NPU","native backend validation","paired-real tensors","distributed quantum simulation","reverse-mode differentiation","variational quantum algorithms","quantum architecture search"],"falsifier":"With CPU fallback disabled, run one of the claimed-native paths (for example, an $n=14$ Pauli expectation) under device-side tracing that records every host-device transfer and every CPU kernel; if the state tensor is copied to host memory or any operation executes on the CPU during that run, the native-execution claim for that path is false.","tokens_in":29710,"feed_emoji":"⚛️","tokens_out":8759,"duration_ms":67530,"temperature":0.7,"pith_summary":"The paper sets out to show that a full-stack quantum circuit simulator can run natively on Ascend NPUs, not merely on CPUs or GPUs with the NPU as an afterthought. It claims Aicir is the first framework to span circuit construction, multiple state representations, measurement, differentiation, variational algorithms, quantum machine learning, and quantum architecture search with a validated native Ascend backend. The key move is to represent complex amplitudes as paired real tensors and apply gates through fixed-rank views, so the operations the NPU actually supports do the work. The authors validate the native-execution claim by disabling CPU fallback and intercepting issued operations, and they check distributed communication and gradients on 2, 4, and 8 NPUs. On CPU, the same simulator lands within the same runtime range as established simulators for the fused layered workloads tested.","feed_headline":"Quantum simulator runs natively on Ascend NPUs, start to finish","feed_subtitle":"Circuit construction, measurement, gradients, and distributed runs stay on the accelerator with no CPU fallback.","key_machinery":"The load-bearing machinery is the paired-real tensor representation: every complex value $z=x+iy$ is stored as two float32 tensors $(x,y)$, and state updates, inner products, probabilities, partial traces, and SVDs are evaluated with real arithmetic. Gates are applied through fixed-rank views—an index table gathers the affected amplitudes, a local matrix multiplication updates them, and scatter writes them back—with the flat path chosen above eight qubits so the working tensor rank no longer grows with qubit count. Custom backward rules keep gate and state gradients in real tensors, avoid complex gradient accumulation, and let the same representation carry distributed sharding and reverse-mode differentiation. The backend contract of 19 methods keeps this hardware-specific machinery below a boundary that circuit construction and algorithm modules do not cross.","core_discovery":"The central claim is that Aicir achieves native Ascend NPU execution across the full simulator stack, and that this is possible because complex numbers are carried as pairs of real tensors and gates are applied through fixed-rank, gather-multiply-scatter views rather than high-rank complex operations. This representation also lets a state vector or density matrix be partitioned across $2^p$ NPUs while reverse-mode differentiation is retained, since the trainable leaves stay real and all collective payloads are real. The paper's experiments establish native execution for the tested paths, check gradients and communication on 2, 4, and 8 NPUs, and explicitly do not claim CPU-to-NPU speedup or multi-NPU scaling.","pith_inferences":["An extension the paper does not pursue: the paired-real design should transfer to other accelerators whose software stacks lack full complex-tensor kernels.","The interception-based validation protocol could be reused as a general test for silent CPU fallback in any accelerator backend.","The row-sharded distributed state with real collectives suggests a hybrid CPU/NPU mode, where part of the state lives in host memory, as a natural next step.","Readers should treat any workflow outside the paper's validated backend surface as potentially host-assisted until separately checked."],"forward_implications":["A researcher on Ascend NPUs can run a complete quantum workflow—circuit construction, state evolution, measurement, expectation values, and gradients—without writing accelerator kernels by hand.","The paired-real representation lets a state be split across $2^p$ NPUs while gradients still flow, so exact simulation can reach states larger than one device holds.","Algorithm modules such as variational eigensolvers, quantum machine learning, and architecture search can all reuse the same native backend rather than each needing a separate accelerator port.","CPU execution remains competitive with established simulators for fused layered circuits, so the NPU capability does not come at a runaway CPU cost."],"supporting_citations":[{"why":"Provides the strongest measured CPU execution baseline against which Aicir reports its fused-layered runtime ratios.","marker":"[2]"},{"why":"Supplies the Cirq simulator baseline and the split_untangled_states execution path discussed as an alternative design.","marker":"[11]"},{"why":"Gives the distributed state-vector simulation context that motivates Aicir's sharded-state design.","marker":"[4]"},{"why":"Context for distributed HPC simulation that supports the paper's narrower claim about retaining differentiation through a partition.","marker":"[13]"},{"why":"Closest system in backend choice and differentiation; its contract with established machine-learning runtimes motivates Aicir's own backend contract.","marker":"[6]"},{"why":"Documents the closest ecosystem's documented simulator backends and supports the paper's claim that no Ascend backend is listed there.","marker":"[7]"},{"why":"Recent Ascend NPU contraction work that does not provide a full-stack simulator, used to delimit the paper's novelty.","marker":"[9]"},{"why":"Supplies the benchmark methodology of timing circuit construction separately from execution, which the paper adopts.","marker":"[23]"},{"why":"Provides the analytic parameter-shift rule used as an independent gradient oracle in the distributed validation.","marker":"[27]"}],"fun_headline_variants":["Full-stack quantum simulation stays on Ascend NPUs","Aicir: native Ascend NPU execution, no CPU fallback","Quantum circuit simulator goes full-stack on Ascend NPUs","Run, measure, and differentiate all on Ascend NPUs","Ascend NPU native quantum simulation with distributed and gradients"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The claim that the validated paths are truly native rests on the assumption that disabling the explicit CPU fallback and intercepting issued operations catches every hidden host-side path; a silent fallback outside the intercepted surface would not show up in the returned tensor.","fun_headline_variants_meta":{"raw":{"variants":["Full-stack quantum simulation stays on Ascend NPUs","Aicir: native Ascend NPU execution, no CPU fallback","Quantum circuit simulator goes full-stack on Ascend NPUs","Run, measure, and differentiate all on Ascend NPUs","Ascend NPU native quantum simulation with distributed and gradients"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000373,"raw_usage":{"total_tokens":2022,"prompt_tokens":1001,"completion_tokens":1021,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":617,"completion_tokens_details":{"reasoning_tokens":934}},"tokens_in":617,"tokens_out":1021,"duration_ms":8552,"temperature":1.0,"reasoning_tokens":934,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-11T11:47:47.606132+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"With CPU fallback disabled, run one of the claimed-native paths (for example, an $n=14$ Pauli expectation) under device-side tracing that records every host-device transfer and every CPU kernel; if the state tensor is copied to host memory or any operation executes on the CPU during that run, the native-execution claim for that path is false.","supporting_citations":[{"cited_title":"Qiskit Aer,","cited_arxiv_id":null,"evidence_quote":"Provides the strongest measured CPU execution baseline against which Aicir reports its fused-layered runtime ratios."},{"cited_title":"[Online]","cited_arxiv_id":null,"evidence_quote":"Supplies the Cirq simulator baseline and the split_untangled_states execution path discussed as an alternative design."},{"cited_title":"TensorCircuit: a quantum software framework for the NISQ era,","cited_arxiv_id":null,"evidence_quote":"Closest system in backend choice and differentiation; its contract with established machine-learning runtimes motivates Aicir's own backend contract."},{"cited_title":"mindquantum.simulator.Simulator,","cited_arxiv_id":null,"evidence_quote":"Documents the closest ecosystem's documented simulator backends and supports the paper's claim that no Ascend backend is listed there."},{"cited_title":"Realified tensor networks: quantum circuit simulation on real-valued matrix accelerators","cited_arxiv_id":"2608.03987","evidence_quote":"Recent Ascend NPU contraction work that does not provide a full-stack simulator, used to delimit the paper's novelty."}],"review_version":1}