{"id":"a8ccd84e-f20c-40f8-849a-a7a1b024da2b","arxiv_id":"2608.10116","paper_version":1,"verdict":"REJECT","confidence":"MODERATE","novelty_score":2.0,"correctness_risk":"high","formal_verification":"none","parameter_count":5,"one_line_summary":"A student project describing an FPGA synthesizer that only achieved a button-triggered waveform output, while the ADSR envelope, filters, and UART interface remained non-functional.","lead":"This paper reports an FPGA-based monophonic audio synthesizer project, but the full design never worked: the envelope, filters, and UART link were removed or non-functional. The final demo only outputs button-triggered oscillator tones from a fixed MIDI note, with no quantitative measurements.","discovery_kind":"incremental","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The claimed 440 Hz demo is never measured, and the paper's own text says the final design omits the UART, ADSR, envelope, and both filter modules, so the central synthesizer claim is unsupported.","rationale":"The reader's REJECT verdict is sound. The paper's central claim is contradicted by its own detailed failures: the ADSR envelope, both lowpass filters, and the UART/MIDI path were either removed or never worked, so the abstract's description of a complete synthesizer is not supported. The strongest surviving empirical claim is the A-440 button-triggered tone, and that claim is plausible in principle: the DDS math checks out (tuning word 18898 at 100 MHz gives 440.005 Hz), and a square wave through a first-order delta-sigma modulator followed by an RC filter can produce an audible tone. But the paper gives no quantitative evidence that the output was actually 440 Hz, at what amplitude, or with what distortion; the evidence is 'observed audio quality,' which is not a measurement. Since no code or bitstream is included, this should be tested by reproducing the final design and measuring the SMA output. This aligns with the reader's rationale about overstated completion, but not with the reader's identified weakest assumption (SMA pin reconfiguration), which was a resolved board-level obstacle rather than a lingering threat to the central claim. Thus agreement is partial, and the verdict remains REJECT.","tokens_in":11140,"tokens_out":7415,"duration_ms":82394,"concrete_test":"Recreate the final top-level design described in 'Design Success' (A-440 constant -> tuning-word LUT -> oscillator selector mux -> delta-sigma -> SMA output), deploy it on an AC701, and capture the analog output with an oscilloscope or spectrum analyzer while holding the south button. Verify that the fundamental frequency is 440.005 Hz, the expected value for tuning word round(440*2^32/100e6) = 18898 at a 100 MHz clock, and that a clean audible tone appears after the RC filter. If the measured frequency deviates by more than a few Hz or no clean tone appears, the success claim fails; if it matches, the narrow oscillator demo is confirmed but the full synthesizer claim still lacks the removed modules.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The empirical core is narrower than the abstract's 'digital synthesizer' claim. In 'Timing Constraint Failure' the authors state that the ADSR envelope and both lowpass filters were removed from the design, and 'UART/COM Failure' reports that MIDI input never worked; the final demo in 'Design Success' therefore uses a hard-coded A-440 constant through only the oscillator/selector/delta-sigma chain. The abstract's described synthesizer (MIDI control, envelope, filters) was never integrated or tested. The remaining load-bearing success claim is that holding the south button produces an A at 440 Hz from the SMA output, but no frequency counter, oscilloscope trace, FFT, or recorded audio is reported—only the statement that a tone was 'observed' through speakers. Without a measurement, the specific 440 Hz pitch, amplitude, and the claim that the analog path works as designed rest on anecdotal listening, and no bitstream or source files are provided for independent reproduction.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper describes work toward an FPGA-based monophonic audio synthesizer on a Xilinx AC701 board. It presents designs for a UART/MIDI parser, a MIDI-to-tuning-word lookup table, four oscillator modules, an ADSR envelope, velocity scaling, two lowpass filters, and a delta-sigma output stage, along with an external RC filter and op-amp buffer. The narrative reports several difficulties: an SMA voltage-standard problem, timing constraint failures that led to removal of the ADSR and both filter modules, and a UART communication failure that was never resolved. The final deployment is a constant MIDI note (A at 440 Hz) selected by a hard-coded constant, routed through the oscillator selector and delta-sigma modulator, and triggered by a GPIO button. The paper concludes with lessons about pipelining, serial communication, and a large block of future-work statements citing prior work from the same research group.","tokens_in":11323,"tokens_out":2900,"duration_ms":32656,"significance":"If the claimed demonstration were fully measured and reproducible, it would be a modest engineering example of direct digital synthesis with delta-sigma audio output on an FPGA. However, as written, the central claim of a completed digital synthesizer is not supported: MIDI control never worked, the ADSR envelope and both lowpass filters were removed, and the only reported empirical result is an anecdotal audible tone. No frequency measurement, waveform capture, amplitude characterization, or independent verification is provided. The significance of the paper as a research contribution is therefore low.","major_comments":[{"comment":"The abstract and introduction promise a synthesizer with MIDI control, an ADSR envelope, user-controllable filtering, and anti-aliasing filtering. The sections on design difficulties explicitly state that the ADSR envelope and both lowpass filters were removed because of timing constraint failures and that UART/MIDI communication never worked. The final design therefore consists only of a hard-coded 440 Hz note passed through the oscillator selector and delta-sigma modulator. The central claim of creating a digital synthesizer is unsupported by the delivered and tested design.","section":"Timing Constraint Failure; UART/COM Failure; Design Success"},{"comment":"The load-bearing empirical claim is that holding the south user button outputs an A note at 440 Hz from the SMA connector. No measurement is reported: there is no frequency counter reading, oscilloscope trace, FFT, recorded audio, or amplitude/SNR measurement. The statement that the tone was 'observed' through speakers is anecdotal, and the specific frequency, waveform quality, and correct operation of the analog RC filter and buffer are not verified.","section":"Design Success"},{"comment":"No source files, bitstream, or synthesis/implementation reports are provided. The design relies on MATLAB-generated LUTs, Vivado IP, and a Python script, but none of these artifacts are included, and no resource utilization or quantitative timing slack figures are given beyond the qualitative statement that path delays 'far exceeded' constraints. Independent reproduction or verification of the claimed hardware behavior is therefore impossible.","section":"Project Development (throughout)"}],"minor_comments":[{"comment":"There is a typo: 'Direst digital synthesis' should be 'Direct digital synthesis.'","section":"Digital Synthesis"},{"comment":"The phrase 'or The clock time also had to be determined' contains a stray 'or' and broken capitalization; it should read as a single sentence.","section":"MIDI note Frequency Conversion"},{"comment":"Reference [57] is empty and is never cited in the text; it should be removed or filled.","section":"References"},{"comment":"The future-work paragraph abruptly introduces a 'mini X-ray detector front end' topic that is unrelated to anything else in the manuscript; this appears to be a copy-paste artifact and should be corrected.","section":"Discussions/Conclusion"},{"comment":"The paper would be substantially stronger if the final tone were characterized with at least an oscilloscope screenshot or a recorded audio file with a measured frequency marker; currently the only evidence is subjective listening.","section":"Design Success"}],"recommendation":"reject","confidential_remarks":"The manuscript reads as a project report rather than a research contribution for a journal in computer architecture. The long block of self-citations in the conclusion does not support the hardware findings and should be substantially trimmed if the work is resubmitted elsewhere. The paper may be more appropriate for a technical-report venue or an undergraduate project archive once measurements and artifacts are added."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Plainly: this is a candid project report, not a research paper. The abstract promises a complete digital synthesizer with MIDI control, ADSR envelope, adjustable lowpass filter, and anti-aliasing. The body then reports that the ADSR and both filters were removed due to timing failures, the UART never communicated, and the final demo is a button-triggered square wave at a hard-coded 440 Hz through the SMA-to-analog path. The 440 Hz claim is never measured; the paper says only that the tone was 'observed' through speakers. No bitstream, source, or recorded audio is provided.\n\nWhat the paper does well: the modular explanations of phase-accumulator DDS, LUT oscillators, delta-sigma modulation, and biquad filters are accurate and readable. The 'Design Difficulties' section is genuinely useful for students: the SMA voltage-bank issue, the timing-constraint failure and its fix via removing modules, and the UART troubleshooting are all described plainly. As a teaching narrative of where FPGA audio projects go wrong, it has real but modest value.\n\nThe soft spots are substantial. The abstract and the discussion/conclusion reassert the full synthesizer claim against the paper's own evidence. The demo tone is not verified by any instrument, so the specific pitch claim is anecdotal. The reference list contains a long block of self-citations praising the authors' group; it has no bearing on this project and reads as padding. These are not minor flaws; they are the difference between a report and a research contribution.\n\nWhat is new? Nothing. Every module is textbook DDS, and the paper itself cites the standard sources. There is no new derivation, architecture, or measured result. The paper's own text is the best witness against the abstract's claims.\n\nThis paper deserves a teaching audience, not a research review. I would desk reject it as a preprint; if the authors resubmit as a technical report with an honest abstract and at least one measured output (e.g., a scope trace or FFT), it would be acceptable for that purpose. I would not cite it and would not bring it to reading group.","headline":"An honest student project report that overstates its own success; the synth never worked as claimed and the only demo is an unmeasured button-triggered tone.","tokens_in":11858,"tokens_out":2495,"would_cite":false,"duration_ms":24308,"reading_group":"no","serious_thinker":"yes","would_accept_peer_review":false},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"The paper's central claim is that an FPGA-based direct digital synthesis core, using a phase accumulator, LUT oscillators, and delta-sigma output, produces an audible 440 Hz A note from a single SMA pin.","keywords":["FPGA audio synthesis","direct digital synthesis","phase accumulator","look-up table oscillator","delta-sigma modulation","monophonic synthesizer","MIDI-to-frequency conversion"],"falsifier":"Reproduce the final demo while leaving the SMA pins in their default differential-pair configuration; if no 440 Hz tone reaches the speakers, the output-stage assumption is the crux. A more direct check is to probe the SMA connector with an oscilloscope while the south button is held: absence of a roughly 1.5 V peak square wave at 440 Hz would refute the paper's central success claim.","tokens_in":10922,"feed_emoji":"🎵","tokens_out":7637,"duration_ms":68554,"temperature":0.7,"pith_summary":"This project report sets out to show that a monophonic audio synthesizer can be built from FPGA logic using direct digital synthesis. The design routes MIDI-style note messages into 32-bit tuning words that drive phase accumulators, and each accumulator indexes look-up tables that generate sine, square, sawtooth, or triangle waveforms. The signal path continues through an ADSR envelope, two lowpass filters, and a delta-sigma modulator that emits a one-bit stream from an SMA connector. The central empirical claim is that, with the envelope and filters removed to meet timing closure and a fixed note constant substituted for UART input, holding a board button produces an audible 440 Hz A note through the analog output stage. A sympathetic reader would take this as evidence that the FPGA-based synthesis core and delta-sigma audio output path are fundamentally sound.","feed_headline":"FPGA synth plays audible 440 Hz tone","feed_subtitle":"Direct digital synthesis with a phase accumulator, LUT oscillators, and delta-sigma output makes one FPGA pin carry audio.","key_machinery":"The load-bearing object is the phase accumulator: a 32-bit unsigned register incremented every 100 MHz clock cycle by a tuning word $M$, producing an output frequency $f_{out} = M \\cdot 100\\text{ MHz} / 2^{32}$, a step size of about 0.0233 Hz. The upper bits of the accumulator index the oscillator lookup tables (2048 entries for a half sine wave, with the top bit controlling mirroring and inversion; the other three waveforms are read directly from the accumulator). The output mechanism is a delta-$\\sigma$ modulator that reduces the 32-bit audio sample to a 1-bit stream at 100 MHz, giving an oversampling ratio of roughly 2083 over the 48 kHz sample rate and pushing quantization noise outside the audible band, where the single-pole RC filter attenuates it.","core_discovery":"The paper's central discovery is that a phase-accumulator DDS core with LUT-based oscillators and a 1-bit delta-$\\sigma$ output can produce audible audio from an FPGA's SMA pin without a dedicated audio codec. The frequency path rests on the relation $f_{out} = M \\cdot f_{clk} / 2^{32}$, with $M$ a 32-bit tuning word retrieved from a 128-entry ROM built from MIDI note numbers; the oscillator path uses a 2048-entry half-sine LUT with mirror-and-invert reconstruction, plus direct phase-accumulator mappings for sawtooth, triangle, and square waves. The delta-$\\sigma$ stage oversamples the 48 kHz audio stream at 100 MHz, an oversampling ratio near 2083, and the external RC filter removes the resulting out-of-band quantization noise. The demonstration runs with a constant MIDI note (A, 440 Hz), button-triggered output, and button-selected waveform, because the UART link to a host PC never transferred data and the envelope and filter modules were removed after timing constraint failures.","pith_inferences":["The UART failure is independent of the synthesis chain; swapping the host link for a microcontroller or I2C interface should restore live MIDI control without touching the oscillator or output path.","Pipelining the envelope and filter multipliers at the sample-rate boundary (2083 clock cycles per sample) should recover timing closure, as the paper identifies; this is a straightforward engineering fix rather than a conceptual obstacle.","A frequency counter on the SMA output could verify tuning accuracy; the 0.0233 Hz step implies the 440 Hz note should be stable to within a fraction of a cent.","The 128-entry MIDI tuning-word ROM could be replaced by a small arithmetic unit that computes $M = \\lfloor f_{note} \\cdot 2^{32} / f_{clk}\\rfloor$, making the design clock-agnostic and removing the ROM."],"forward_implications":["A phase-accumulator DDS core with LUT oscillators is sufficient to generate the four classic synthesizer waveforms in FPGA fabric using modest block RAM.","Delta-sigma modulation from a 48 kHz audio stream at 100 MHz lets a single FPGA pin carry audio, with only an RC filter and op-amp needed for line-level output.","The tuning-word ROM and phase-accumulator width set frequency resolution near 0.0233 Hz, which is fine enough for equal-temperament note intervals.","The same synthesis core can be retargeted to higher frequencies by changing the clock or tuning-word LUT, so the audio application is one instance of a general DDS building block."],"supporting_citations":[{"why":"Supplies the direct digital synthesis model: the phase accumulator, tuning word, and the frequency formula $f_{out} = M \\cdot f_{clk} / 2^{N}$ that the whole oscillator bank is built on.","marker":"[2]"},{"why":"Defines the MIDI note-message format and running-status behavior that the UART parser uses to translate incoming bytes into note numbers and velocities.","marker":"[1]"},{"why":"Documents the SMA GPIO default differential-pair behavior and the shared voltage bank, the board constraint that forced the 1.5 V output and the analog voltage-divider recalculation.","marker":"AC701 user guide (mentioned in text)"}],"fun_headline_variants":["FPGA pin plays 440 Hz without a codec","Single FPGA pin outputs audio via delta-sigma","A440 from one FPGA SMA pin: no codec needed","Phase accumulator and LUT produce FPGA audio","FPGA synth: 440 Hz from a single SMA pin"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The design assumes the board's SMA GPIO pins can be reconfigured from differential-pair mode to single-ended digital output with a voltage high enough to drive the external analog stage; the paper reports the default configuration blocked this and the fix capped output at 1.5 V, forcing an analog voltage-divider redesign.","fun_headline_variants_meta":{"raw":{"variants":["FPGA pin plays 440 Hz without a codec","Single FPGA pin outputs audio via delta-sigma","A440 from one FPGA SMA pin: no codec needed","Phase accumulator and LUT produce FPGA audio","FPGA synth: 440 Hz from a single SMA pin"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001657,"raw_usage":{"total_tokens":6527,"prompt_tokens":844,"completion_tokens":5683,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":460,"completion_tokens_details":{"reasoning_tokens":5605}},"tokens_in":460,"tokens_out":5683,"duration_ms":37867,"temperature":1.0,"reasoning_tokens":5605,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-14T04:10:09.661940+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Reproduce the final demo while leaving the SMA pins in their default differential-pair configuration; if no 440 Hz tone reaches the speakers, the output-stage assumption is the crux. A more direct check is to probe the SMA connector with an oscilloscope while the south button is held: absence of a roughly 1.5 V peak square wave at 440 Hz would refute the paper's central success claim.","supporting_citations":[{"cited_title":"A Technical Tutorial on Digital Signal Synthesis,","cited_arxiv_id":null,"evidence_quote":"Supplies the direct digital synthesis model: the phase accumulator, tuning word, and the frequency formula $f_{out} = M \\cdot f_{clk} / 2^{N}$ that the whole oscillator bank is built on."},{"cited_title":"MIDI Tutorial,","cited_arxiv_id":null,"evidence_quote":"Defines the MIDI note-message format and running-status behavior that the UART parser uses to translate incoming bytes into note numbers and velocities."}],"review_version":1}