{"id":"40534303-2067-463b-b2b5-0a5f36e6c993","arxiv_id":"2608.11116","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"Charge-CIM reuses switched capacitors as combined DAC, analog MAC, shift-add, and SAR ADC to reduce ADC-related energy by 91.7 percent in simulation.","lead":"This paper proposes Charge-CIM, an analog compute-in-memory chip architecture that reuses the same switched capacitors for computation and digitization, removing much of the separate ADC hardware that dominates energy use. It is worth reading because the ADC wall is a recognized bottleneck for this class of AI accelerators, and the design claims 2.7x better energy efficiency and 2.0x higher throughput than a state-of-the-art charge-domain CIM accelerator.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Phase 5's binary-weighted shift-add is not physically realizable as described: after Phase 4 each column has P equal unit capacitors, and the paper specifies no switch topology that selects 1,2,...,2^{M-1} of them while isolating the rest; without this, Eq.","rationale":"The reader's verdict is CONDITIONAL, and my stress-test confirms that the main missing link is the Phase 5 S_SA topology. The paper's own text states that Phase 4 shorts all P unit capacitors per column, so every bit-column presents the same total capacitance. Eq. (4), however, assumes the columns contribute charges in ratios 1:2:...:2^{M-1}. The only way to reconcile these is a switch network that selects 2^m capacitors from column m and connects them to a shared summing node, leaving the others disconnected. The manuscript gives no schematic or textual description of such a network, and the per-capacitor switching cost is absent from the area/power tables. This is not merely a missing implementation detail: without it, the central contribution (slice-free multi-bit VMM in the analog domain) has no hardware instantiation. The secondary DAC capacitance concern is related: Eq. (1) needs 2^N=256 unit caps per 8-bit row, but the stated 128-column macro would provide only 128 unless each MCC has two caps or the DAC spans rows. Both concerns are checkable from the layout and netlist. I do not see a self-contradiction in the equations; the conditional verdict is appropriate. I agree with the reader's identification of the same weakest assumption. No change to the verdict is needed.","tokens_in":17481,"tokens_out":8702,"duration_ms":77242,"concrete_test":"Run a SPICE simulation of the six-phase operation using the exact S_SA switch netlist the authors intend, with a compute-bar of P=128 rows and 8 bit-columns. Verify that the Phase 5 shared-node voltage matches Eq. (4) to within the reported 0.46 LSB settling error for a full INT8 weight set (0x01 through 0x80) and for all-zero and all-one input patterns, and confirm that the unselected P-2^m capacitors do not perturb the result when disconnected. Also report the number of unit capacitors per row accessible to the Phase 2 DAC and check against the 128-column macro layout.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim that Charge-CIM performs slice-free 8-bit VMM rests on Phase 5's weighted shift-and-add (Eq. 4). In Phase 4, all P unit capacitors in a column are shorted together (S_ACC closed, S_SA open), leaving each column with P equal capacitors at voltage V_acc[m]. For Eq. (4) to hold, the S_SA network must then connect exactly 1, 2, ..., 2^{M-1} capacitors from successive bit-columns to a common node and isolate the remaining P-2^m capacitors. The paper describes S_SA only as 'switches' that 'configure the shared capacitance ratio between columns,' but never specifies whether these are per-capacitor switches, per-column switches, or a capacitive ladder. If S_SA simply shorts whole columns, the result is the unweighted average of V_acc[m], not the binary-weighted sum; if per-capacitor switches are assumed, the layout area and control overhead are not accounted for in Table III, and the charge on the disconnected P-2^m capacitors is discarded without a described reset or reuse mechanism. Additionally, the row-wise embedded DAC of Phase 2 (Eq. 1) requires C_tot = 2^N C_u, i.e., 256 unit capacitors per row for 8-bit input, while the 256x128 macro gives only 128 columns per row unless each MCC contains multiple capacitors; no such detail is provided. Without a concrete S_SA topology showing binary-ratio regrouping from equal per-column caps, Eq. (4) is an ungrounded mathematical identity, and the fully analog multi-bit claim is not established.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"Charge-CIM is a proposed charge-domain analog computing-in-memory (ACiM) macro architecture that reuses a switched-capacitor network for input digital-to-analog conversion, 1-bit multiplication, column-wise accumulation, binary-weighted shift-and-add across weight-bit columns, and in-situ SAR-ADC quantization. The paper derives an end-to-end VMM expression (Eq. 5), presents a differential readout with 'inverse coding' to accumulate paired partial sums, and evaluates the design with SPICE-based circuit simulation plus Timeloop/Accelergy architecture simulation. Against RAELLA and Cambricon-CIM, it reports 91.7% ADC energy reduction, 2.71x energy efficiency, and 2.01x throughput improvements across nine DNN/LLM benchmarks.","tokens_in":17764,"tokens_out":9697,"duration_ms":74139,"significance":"If the architectural feasibility were fully established, Charge-CIM would be a meaningful step toward eliminating the ADC wall in ACiM by replacing bit-sliced execution with a single charge-processing path. The paper's ideal-equation derivation is internally consistent, the offset-encoding treatment of signed arithmetic is correct, and the evaluation methodology (SPICE extraction, Monte Carlo mismatch, architecture-level simulation, ablation) is appropriate for the field. The claims are falsifiable and the paper provides a clear quantitative comparison. However, the central contribution depends on a physical reconfiguration that is not specified at the switch level; until that is resolved, the results should be treated as conditional.","major_comments":[{"comment":"The paper never specifies the switch topology that realizes the binary-weighted regrouping in Phase 5. After Phase 4, all P unit capacitors in a given column are shorted by S_ACC, so each column contains P identical capacitors at V_acc[j][m]. Equation (4) requires the S_SA network to connect exactly 1, 2, ..., 2^{M-1} capacitors from successive bit columns to a common output node and to isolate the remaining P - 2^m capacitors. The text only states that 'S_SA switches configure the shared capacitance ratio between columns'; it does not say whether these are per-capacitor switches, per-column switches, or a ladder network. If S_SA simply shorts whole columns, the output is an unweighted average. If per-capacitor switches are assumed, their area and control overhead are absent from Table III, and the charge on the disconnected capacitors is discarded without a described reset. This is load-bearing: without a concrete S_SA topology, Eq. (4) is an ungrounded mathematical identity and the central slice-free multi-bit claim is not established.","section":"III.A, Phase 5, Eq. (4)"},{"comment":"The embedded DAC requires C_tot = 2^N C_u per row; for N=8 this is 256 unit capacitors per row. The macro is specified as 256×128 in Table III, giving only 128 columns (and hence 128 MCCs) per row, and Section III.A describes each MCC as containing 'a unit switched capacitor'. No explanation is given for how 256 unit capacitors fit in a 128-column row while also accommodating the weight-bit mapping. If each row truly contains only 128 unit capacitors, the maximum input precision is 7 bits, which would contradict the INT8 VMM claim. The paper should provide a concrete row layout (e.g., multiple unit capacitors per MCC, or a different macro dimension) or revise the precision claims.","section":"III.A, Phase 2, Eq. (1) and Table III"},{"comment":"The inverse-coding scheme states that 'the V_N-side array is driven by pre-inverted inputs (I_inv = -I_N), generating a negative partial sum V_N = -I_N·W_N.' In the charge-domain implementation described in Section III, voltages are inherently non-negative (between 0 and V_DD), so a literal negative partial sum cannot appear on a single-ended capacitor node. The paper should clarify the physical mechanism: e.g., bitwise inversion combined with offset compensation, differential plate swapping, or a negative reference. As written, Eq. (8) is a mathematical identity rather than a demonstrated circuit behavior, and the claim of in-ADC partial-sum addition rests on this mechanism.","section":"IV-B, Eq. (8)"}],"minor_comments":[{"comment":"The text says '2N MCCs are grouped via N SDAC switches in a binary ratio (1 : 1 : 2 : ... : 2^{N-1})'; this should be '2^N' (or '2^N - 1 unit capacitors'), since the binary ratio sums to 2^N - 1, not 2N.","section":"III.A(1)"},{"comment":"The caption states 'Cambricon-CIM achieves geometric means of 2.26× and 3.69×, respectively' without specifying what those numbers refer to; the text reports 2.71× and 2.01× improvements for Charge-CIM. Please clarify the comparison direction and the meaning of the geometric means.","section":"Fig. 13 caption"},{"comment":"The MCC row lists '2.66 fF 2.15fJ/act 1.74µm^2' with mixed units; please separate capacitance, energy per activation, and area into distinct columns with clear headers.","section":"Table III"},{"comment":"The statement that the 256×128 macro is split into two 128×128 subarrays operating differentially should be reconciled with the embedded-DAC capacitance requirement per row; as written, it reinforces the concern in Major Comment 2.","section":"V.A"}],"recommendation":"major_revision","confidential_remarks":"The reader's conditional verdict is appropriate. The main risk is that the Phase 5 S_SA network may be infeasible as described; this is not a question of tuning but of missing circuit-level detail. If the authors can provide a transistor-level schematic and layout of the reconfiguration network and clarify the per-row DAC capacitance, the paper could be acceptable. I also note that the paper cites its own prior work (YOCO) as background; that is not a problem per se, but the novelty claim relative to YOCO should be sharpened. The journal should consider whether the current level of circuit detail meets its standards for architecture papers."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"At its core this is a clever paper. The idea of reusing the same switched-capacitor network for input DAC, multiplication, column accumulation, weighted shift-add, and SAR quantization is exactly the kind of integration that could make the ADC wall smaller, and the differential inverse-coding trick for in-ADC addition is neat. The equations are internally consistent under ideal ratios, and the evaluation is more thorough than most: SPICE for the analog bits, Timeloop/Accelergy for the architecture, nine models, PVT and Monte Carlo corners. The accuracy-loss numbers are plausible.\n\nBut the paper has a load-bearing gap. The Phase 5 weighted shift-add (Eq. 4) assumes that after Phase 4 shorts every unit capacitor in a column, the S_SA network can regroup those identical capacitors into binary ratios 1:2:...:2^{M-1} and connect them to a common node. The text never says how. If S_SA just shorts whole columns, you get an unweighted average, not the weighted sum. If it uses per-capacitor switches, the area and control overhead are missing from the tables, and the charge on the unselected caps is not accounted for. Same on the input side: Eq. (1) needs a total row capacitance of 2^N*C_u, but a 128-column subarray doesn't obviously supply 256 unit caps for 8-bit input unless each MCC has multiple caps or the DAC is a C-2C ladder. The paper says '2N MCCs' which only adds to the confusion. These aren't cosmetic issues; the whole 'slice-free multi-bit VMM' claim rests on them.\n\nThe rest of the paper reads like a solid architecture paper. The baselines are reconstructed without artifacts, which is common in this field but worth remembering when weighing the 2.7x energy claim. The reliance on YOCO (same first author) is fine as background; the cited result is plausible.\n\nBottom line: this deserves a serious referee, but it is not acceptable in current form. The authors need to draw the S_SA switch topology at the schematic level, show the per-column capacitance budget, and ideally provide a netlist of a small array demonstrating Phase 5. I'd engage with this as a reviewer, and I'd ask those questions.","headline":"Clever slice-free charge-domain CIM that unifies DAC/MAC/SA/ADC in one capacitor network, but Phase 5's weighted shift-add lacks a specified switch topology and the input DAC capacitance budget doesn't obviously fit the array.","tokens_in":18386,"tokens_out":6408,"would_cite":true,"duration_ms":53746,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Charge-CIM claims one reconfigurable switched-capacitor fabric can carry an INT8 vector–matrix multiply from input to quantized output in the analog domain, cutting ADC energy by 91.7% in simulation.","keywords":["analog computing-in-memory","charge-domain computing","switched-capacitor circuits","ADC wall","successive-approximation register","INT8 quantization","DNN accelerator","charge redistribution"],"falsifier":"Fabricate the 256×128 macro in 28\\,nm with $2.66\\,\\mathrm{fF}$ unit capacitors and measure the end-to-end transfer curve while sweeping all 8-bit input and weight codes; if the $S_{SA}$ regrouping cannot produce the $1:2:\\dots:2^{M-1}$ capacitance ratios, the measured INL/DNL and end-to-end RMSE should exceed the reported $+1.12/-1.14$ LSB and $1.6\\%$, falsifying the central claim.","tokens_in":17218,"feed_emoji":"⚡","tokens_out":16777,"duration_ms":118426,"temperature":0.7,"pith_summary":"Charge-CIM is an attempt to remove the 'ADC wall' that dominates the energy and area of analog computing-in-memory (ACiM) accelerators. The paper argues that bit-sliced execution—splitting inputs and weights into bits and converting each partial sum—is the root cause, and that a single reconfigurable switched-capacitor network can instead carry an INT8 vector–matrix multiply (VMM) from input conversion through analog accumulation and shift-add to quantized readout. The same capacitors are reused as the input DAC, the multiplier storage, the column accumulator, the binary-weighted adder, and the capacitive DAC of an embedded SAR ADC, so charge is injected once and only digitized once. In simulation, this cuts ADC energy by 91.7% and improves energy efficiency by 2.71x and throughput by 2.01x over the Cambricon-CIM baseline. If correct, the design would make analog inference accelerators cheaper and more energy-efficient for CNN, Transformer, and LLM workloads.","feed_headline":"One charge does the whole AI multiply: ADC energy down 91.7%","feed_subtitle":"The same capacitors convert input, multiply, accumulate, and quantize, so converter energy drops 91.7%.","key_machinery":"The load-bearing object is a reconfigurable switched-capacitor fabric: every memory-and-compute cell (MCC) contains SRAM weight bits and a unit capacitor $C_u = 2.66\\,\\mathrm{fF}$, and three switch networks ($S_{DAC}$, $S_{ACC}$, $S_{SA}$) rewire those capacitors between phases. In Phases 1–2 the row capacitors form an $N$-bit embedded DAC; in Phase 3 each capacitor conditionally stores $V_{\\mathrm{in}}\\cdot W$; in Phase 4 column switches average the partial products; in Phase 5 the $S_{SA}$ network regroups columns into binary ratios $1:2:\\dots:2^{M-1}$; and in Phase 6 the same groups serve as the capacitive DAC (C-DAC) of a monotonic successive-approximation-register (SAR) ADC. This one-fabric reuse is what lets the design 'charge once' and convert only at the end, avoiding the repeated ADC invocations that follow from bit-slicing.","core_discovery":"The central claim is that fully analog multi-bit computation is possible without arithmetic slicing: a 256×128 macro of memory-and-compute cells, each holding a unit capacitor and weight bit, can execute an 8-bit-input by 8-bit-weight VMM in six charge-sharing phases. Input bits charge binary-sized capacitor groups ($C_n = 2^n C_u$) that are then shorted row-wise to produce an analog input voltage; a NAND-like switch conditionally retains or discharges that charge according to each weight bit; column-wise charge sharing averages the partial products; reconfigurable $S_{SA}$ switches regroup the same unit capacitors into $1:2:\\dots:2^{M-1}$ ratios to implement bit-weighted shift-add; and the same array becomes the capacitive DAC of a monotonic SAR ADC that quantizes in place. The paper derives the end-to-end expression $V_{out,j} = \\frac{\\sum_{m=0}^{M-1}\\sum_{i=0}^{P-1}\\sum_{n=0}^{N-1} 2^n X_i[n] \\cdot 2^m W_{ij}[m]}{(2^M-1)P \\cdot 2^N} V_{DD}$ and reports that the differential readout with inverse coding turns the ADC's natural subtraction into partial-sum addition, halving conversions and reaching pseudo-9-bit resolution. This is the 'You Only Charge Once' path: charge is injected once at the supply in Phase 1 and only leaves during ADC discharge. The paper claims this eliminates the standalone-DAC and intermediate-ADC costs that make up more than half of energy in prior charge-domain CIM.","pith_inferences":["The same one-charge principle, if it holds in silicon, should extend to higher bit widths (e.g., 16-bit) by adding more binary-weighted groups, though the $2^N$ unit-capacitance growth would eventually dominate area; the paper only demonstrates up to 8-bit configurations.","The differential in-ADC accumulation could in principle merge partial sums from multiple spatially partitioned arrays, removing digital accumulation trees for large models; the paper applies it only within a macro's paired arrays.","Because the arithmetic is fixed by capacitor ratios rather than by a fixed codebook, the fabric could be reprogrammed to non-binary bases (such as the coding-base reformation used by Cambricon-CIM) by reordering input bits; the paper gives one 3:4 example but does not search this design space.","A silicon measurement of the Phase 5 regrouping would be the decisive test: if switch parasitics discard charge from unselected capacitors, the reported 1.6% end-to-end RMSE and 4.46 mV peak quantization error would not survive, independent of the architecture-level simulations."],"forward_implications":["Bit-slicing disappears: an 8-bit input and an 8-bit weight contribute in one analog pass, so the number of ADC conversions per output drops from the product of slice counts to one per compute-bar read.","The reused capacitor array removes the standalone C-DAC of a conventional ADC, shrinking converter area to 3% of total chip area and reducing ADC energy by 91.7% in the paper's simulation.","Differential inverse coding folds partial-sum addition into the SAR comparison, halving the number of readout conversions and lifting the effective readout resolution to pseudo-9-bit.","Configurable bit-width and base reformation let the same fabric switch between 8-bit, 4-bit, 2-bit, 1-bit, and non-binary coding without hardware changes.","Across nine CNN, Transformer, and LLM benchmarks, the claimed average gains are 2.71x energy efficiency and 2.01x throughput over Cambricon-CIM, with end-to-end VMM RMSE of 1.6% and accuracy loss at most 1.9 percentage points."],"supporting_citations":[{"why":"RAELLA is the arithmetic-reformation baseline; its slicing-overhead analysis motivates the ADC wall and it is one of the two comparison targets.","marker":"[1]"},{"why":"Cambricon-CIM is the main charge-domain SRAM baseline; it supplies the 51% ADC energy breakdown, the coding-base reformation method, and the primary efficiency/throughput comparison.","marker":"[11]"},{"why":"C2C-CIM contributes the C-2C ladder 8-bit MAC technique that Charge-CIM supersedes with reconfigurable unit capacitors.","marker":"[42]"},{"why":"PICO-RAM demonstrates PVT-insensitive in-situ multi-bit charge computing in an SRAM macro, the prior art for capacitor-based computation.","marker":"[4]"},{"why":"CR-CIM shows capacitor reconfiguration to reduce ADC overhead but still relies on bit-slicing, the limitation the paper targets.","marker":"[50]"},{"why":"YOCO reuses local capacitors for in-situ multiply and shift-add, a direct precursor of the unified capacitor reuse idea.","marker":"[49]"},{"why":"Monotonic SAR switching procedure supplies the low-energy successive-approximation algorithm used by the embedded ADC.","marker":"[23]"},{"why":"ISAAC establishes the in-situ analog arithmetic and pipelined dataflow that the hierarchical design builds on.","marker":"[29]"},{"why":"Defines the arithmetic slicing paradigm and its accuracy implications, which the paper targets by eliminating intermediate digitization.","marker":"[46]"}],"fun_headline_variants":["Charge-CIM: one capacitor fabric does MAC and ADC, ADC energy -91.7%","Same capacitors compute and convert: ADC energy drops 91.7%","Analog CIM without the ADC wall: 91.7% less converter energy","You only charge once: switched capacitors slash ADC energy by 91.7%","One charge does the whole multiply: no separate ADC, 91.7% energy saved"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The design assumes that after column-wise charge sharing, the same unit capacitors can be rewired into exact $1:2:4:\\dots$ binary groups for the shift-add step with no charge lost, and that the row has enough room to host both the $2^N$ unit capacitors for input conversion and the 8-bit weight mapping.","fun_headline_variants_meta":{"raw":{"variants":["Charge-CIM: one capacitor fabric does MAC and ADC, ADC energy -91.7%","Same capacitors compute and convert: ADC energy drops 91.7%","Analog CIM without the ADC wall: 91.7% less converter energy","You only charge once: switched capacitors slash ADC energy by 91.7%","One charge does the whole multiply: no separate ADC, 91.7% energy saved"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000411,"raw_usage":{"total_tokens":2224,"prompt_tokens":1134,"completion_tokens":1090,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":750,"completion_tokens_details":{"reasoning_tokens":981}},"tokens_in":750,"tokens_out":1090,"duration_ms":8464,"temperature":1.0,"reasoning_tokens":981,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T05:55:36.415702+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Fabricate the 256×128 macro in 28\\,nm with $2.66\\,\\mathrm{fF}$ unit capacitors and measure the end-to-end transfer curve while sweeping all 8-bit input and weight codes; if the $S_{SA}$ regrouping cannot produce the $1:2:\\dots:2^{M-1}$ capacitance ratios, the measured INL/DNL and end-to-end RMSE should exceed the reported $+1.12/-1.14$ LSB and $1.6\\%$, falsifying the central claim.","supporting_citations":[{"cited_title":"Raella: Reforming the arithmetic for efficient, low-resolution, and low-loss analog pim: No retraining required!","cited_arxiv_id":null,"evidence_quote":"RAELLA is the arithmetic-reformation baseline; its slicing-overhead analysis motivates the ADC wall and it is one of the two comparison targets."},{"cited_title":"Cambricon-cim: Enabling energy-efficient and error-resilient analog cim acceleration via reformation of coding bases,","cited_arxiv_id":null,"evidence_quote":"Cambricon-CIM is the main charge-domain SRAM baseline; it supplies the 51% ADC energy breakdown, the coding-base reformation method, and the primary efficiency/throughput comparison."},{"cited_title":"A charge domain sram compute-in-memory macro with c-2c ladder- based 8-bit mac unit in 22-nm finfet process for edge inference,","cited_arxiv_id":null,"evidence_quote":"C2C-CIM contributes the C-2C ladder 8-bit MAC technique that Charge-CIM supersedes with reconfigurable unit capacitors."},{"cited_title":"Pico-ram: A pvt-insensitive analog compute-in- memory sram macro with in situ multi-bit charge computing and 6t thin- cell-compatible layout,","cited_arxiv_id":null,"evidence_quote":"PICO-RAM demonstrates PVT-insensitive in-situ multi-bit charge computing in an SRAM macro, the prior art for capacitor-based computation."},{"cited_title":"A 818–4094 tops/w capacitor-reconfigured analog cim for unified acceleration of cnns and transformers,","cited_arxiv_id":null,"evidence_quote":"CR-CIM shows capacitor reconfiguration to reduce ADC overhead but still relies on bit-slicing, the limitation the paper targets."},{"cited_title":"Yoco: A hybrid in-memory computing architecture with 8-bit sub-petaops/w in- situ multiply arithmetic for large-scale ai,","cited_arxiv_id":null,"evidence_quote":"YOCO reuses local capacitors for in-situ multiply and shift-add, a direct precursor of the unified capacitor reuse idea."},{"cited_title":"A 10-bit 50-ms/s sar adc with a monotonic capacitor switching procedure,","cited_arxiv_id":null,"evidence_quote":"Monotonic SAR switching procedure supplies the low-energy successive-approximation algorithm used by the embedded ADC."}],"review_version":1}