{"id":"5aab9710-92ff-43dc-b93f-44b69cd5943b","arxiv_id":"2608.12934","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"Dryas is a low-resource, runtime-reconfigurable NFA filtering engine for high-speed interconnects, demonstrated on the 30 GiB/s Enzian coherent link.","lead":"Dryas is a small FPGA filter engine that watches messages on a 30 GiB/s CPU-FPGA connection while the system keeps running, and can change its filter pattern without a reset. It matters because debugging and tuning fast, complex interconnects is expensive, and Dryas shows a low-resource way to do it in real time.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Sub-second reconfiguration claim rests on unmeasured IP solver runtime; resource numbers are synthesized, not measured line-rate throughput.","rationale":"The reader's weakest assumption is exactly the unverified sub-second mapping/reconfiguration time connecting Section 3.1 to Section 5. I agree and identify the same spot as most load-bearing, because the strongest claim includes 'switch filters in under a second' and that claim is both headline and unsupported. I also note that the line-rate claim is similarly asserted from synthesis feasibility rather than measured, which compounds the uncertainty. These are addressable measurement gaps, not internal contradictions; the resource usage numbers are concrete and support the low-overhead integration claim, and the two case studies demonstrate real functionality. Given the paper's claimed status as a working open-source tool, measuring reconfiguration and line rate is feasible and would settle the concern. I therefore keep the reader's CONDITIONAL verdict rather than moving to ACCEPT or REJECT.","tokens_in":14196,"tokens_out":1314,"duration_ms":11960,"concrete_test":"Add to Section 5 a reconfiguration timing experiment: instantiate the IP for the Section 5.3 NFA (7 states, fan-in 6) onto the reported 8-STE/32-stream overlay, time IP solve-to-optimality with the cited solver, count configuration bits, measure the actual configuration shift time on hardware, and report end-to-end wall-clock time while the benchmark application is running. Separately, for line rate, rerun the Section 5.2 benchmark with Dryas counting both input blocks/VC messages and emitted trace records at the 30 GiB/s link rate; if input count equals output-plus-dropped count over a 1-second window, line rate is verified.","verdict_should_be":"CONDITIONAL","load_bearing_attack":"The paper's headline claims are (a) 30 GiB/s line-rate filtering and (b) sub-second filter reconfiguration without disturbing the application. Section 5 never measures end-to-end reconfiguration time. The only support is Section 3.1: 'mapping can easily be performed as a standard IP formulation' with no solver data. For each new filter, the IP must be instantiated, solved, and the resulting configuration shifted through CFGLUT5 and routing registers; none of these steps is timed. True line rate is also asserted rather than measured: Section 5.1 reports only synthesis resource usage (LUTs/FFs), and neither Section 5.2 nor 5.3 reports achieved throughput, dropped-message counts, or a comparison of input versus output message counts. Overlay graphs like (C=2, L=302) could create routing congestion that changes timing closure per configuration, so synthesizing one maximal configuration does not establish per-filter line-rate operation. The cache-miss NFA uses 8 STEs and 32 substreams while only 24 substreams are needed, and the claim that runtime register changes (accepting states) preserve the rest of the configuration is not documented in terms of reconfiguration time either.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents Dryas, an FPGA overlay-based engine for tracing and filtering messages on Enzian's 30 GiB/s cache-coherent ECI interconnect. The engine extracts protocol-specific predicates from message headers, feeds them into a runtime-reconfigurable NFA built from state transition elements (STEs) arranged in a rings-of-cliques overlay graph, and emits only messages that lead to accepting states. The authors claim line-rate filtering on their test system, sub-second filter reconfiguration without stopping the application, and low resource usage. The evaluation reports synthesis-based resource scaling for various overlay sizes, then demonstrates two use cases: cross-socket memory latency analysis at block and VC layers, and cache-miss classification of a binary-tree workload using multiple CL-partitioned substreams.","tokens_in":14417,"tokens_out":5507,"duration_ms":55631,"significance":"If the headline claims hold, Dryas would be a genuinely useful open-source tool for live debugging and analysis of high-speed cache-coherent interconnects, with a rare combination of low hardware overhead, complex pattern matching, and runtime reconfigurability. The paper has several strengths: the rings-of-cliques overlay is a clear and parametrizable design; the mapping problem is honestly formulated as an NP-complete subgraph isomorphism and solved via standard IP solvers without fitted parameters; the two use cases are nontrivial and produce plausible traces; and the claimed resource usage is small enough to coexist with real applications. However, the two most important claims—sustained 30 GiB/s line rate and sub-second end-to-end reconfiguration—are never directly measured. The paper therefore, as written, provides a convincing architecture description but not a convincing experimental validation of its central performance promises.","major_comments":[{"comment":"The claim that Dryas filters data at 30 GiB/s line rate is not supported by direct measurement. Section 5.1 reports only synthesis resource usage (LUTs and FFs) and timing-closure of maximal configurations; Sections 5.2 and 5.3 show traces but report no achieved throughput, no input-versus-output message counts, no dropped-message counters, and no comparison showing that filtering preserves all messages that should be preserved. Please add an explicit line-rate experiment (for example, count blocks/messages at the input and at the filter output over a sustained run, and report equality or loss rates) or weaken the abstract and introduction to claim only that the design is intended for line rate.","section":"§5.1, Abstract, §1"},{"comment":"The sub-second reconfiguration claim rests on the IP-based subgraph mapping completing quickly, but no mapping time is ever reported. Section 3.1 states that 'mapping can easily be performed as a standard IP formulation,' but Section 5 never times the IP solve, the CFGLUT5 configuration shifting, or the register updates for any of the filters used in the evaluation. Since the abstract and introduction promise filter changes 'in less than a second,' please provide end-to-end reconfiguration measurements for realistic filters and overlay sizes, and report the solver used and the observed solve times.","section":"§3.1, Abstract, §1"},{"comment":"The latency analysis reports averages of 0.135 μs at the VC layer and 5.2 μs at the block layer, and infers a '40x difference' and congestion effects, but no variance, distribution, sample count, or measurement method is given. Averages without spread are insufficient to support the conclusion that most of the latency is due to FPGA VC-layer serialization. Please report the latency distributions (e.g., percentiles or histograms) and the number of request-response pairs used.","section":"§5.2"},{"comment":"No false-negative or false-positive rate is reported for the filter engine. For a tool whose purpose is to find rare and transient events, silent message loss would invalidate both use cases. The paper shows that the filter reduces trace volume by over 10^5 in Section 5.2, but that reduction is not evidence that no interesting messages were dropped. Please quantify filter accuracy—for example, by comparing filtered output against a full trace in a short experiment, or by injecting known marker messages and confirming they are always emitted.","section":"§5.2, §5.3"}],"minor_comments":[{"comment":"The sentence 'Dryas has a fixed base cost of Dryas accounts for about 20k LUTs and 29k FFs' is grammatically broken and should be rewritten.","section":"§5.1"},{"comment":"In the text describing Figure 8, the phrases 'increasing' and 'increasing' are missing the RoC parameter symbols (C, L, R, or N) that are being varied; please insert the actual parameter names.","section":"§5.1, Figure 8"},{"comment":"In the final paragraph of Section 3.2, the substream count appears as an empty symbol in phrases like 'activations are received' and 'some of the signals are now -bit buses'; the symbol (likely K) is missing.","section":"§3.2"},{"comment":"There are typos in Section 2.1: 'indentified' should be 'identified', and in Section 1 'gigabyes' should be 'gigabytes'.","section":"§2.1"},{"comment":"The overlay is synthesized to trace 32 substreams, while the stated requirement is 24 substreams for the 24 CLs of the binary search tree; please explain the choice of 32 (e.g., power-of-two alignment) and confirm that the 8 unused substreams are disabled.","section":"§5.3"},{"comment":"The paper says Dryas is open source, but no repository URL or artifact availability statement is provided; please add one.","section":"Abstract and §5.2"}],"recommendation":"major_revision","confidential_remarks":"The core architecture is plausible and the paper is likely honest, but the two headline promises (line-rate throughput and sub-second reconfiguration) are asserted rather than demonstrated. The missing measurements are the main barrier to acceptance; they are obtainable with reasonable additional experiments. The paper also needs a careful proofread; the garbled sentence in §5.1 and the missing symbols in §3.2/§5.1 suggest the manuscript was not fully polished."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The short version: Dryas is a solid systems paper that deserves serious refereeing, but you should treat it as a conditional accept until the authors actually measure the two headline claims.\n\nWhat's genuinely new: applying runtime-reconfigurable NFA overlays to coherent interconnect tracing, and specifically the rings-of-cliques graph with protocol-header predicates and multi-substream replication. The prior work (Napoly, Skeleton automata) points in this direction, and the paper's contribution over that is real, even if it's not paradigm-shifting. The two use cases—cross-socket latency and cache-miss classification—are well chosen and produce plausible, interpretable traces. The resource scaling numbers are interesting and show a small footprint: a few percent of LUTs/FFs for reasonable configurations.\n\nWhere the soft spots are, in order of severity:\n\n1. Sub-second reconfiguration is never measured. Section 3.1 says the mapping 'can easily be performed as a standard IP formulation' but Section 5 ships no solver timings, no end-to-end reconfiguration time, and no discussion of how CFGLUT5 shifting scales. That's a load-bearing claim for the paper's narrative, and it's currently just an assertion.\n\n2. Line rate is asserted, not demonstrated. We get synthesis results and the fact that the trace contains millions of cycles, but no measured throughput, no input-vs-output message counts, no dropped-message counters. Given that the whole point is to filter at full 30 GiB/s without interfering, this is a gap.\n\n3. Latency figures in Section 5.2 report averages (0.135 µs VC, 5.2 µs block) with no variance, sample counts, or confidence intervals. Minor but worth flagging.\n\n4. No false-negative analysis. The block-layer filter relies on VC-based inference, and the paper acknowledges false positives are cleaned up in postprocessing, but there's no estimate of what percentage of relevant messages are actually captured. That matters for anyone relying on this as a debugging tool.\n\n5. The 'open source' statement is not backed by a link or artifact. For a tool paper, that is an easy requirement.\n\nOn the stress-test note: it holds up. The mapping-time concern is real and is the most important thing to fix. Don't ask for a redesign—ask for measurements.\n\nWho this is for: FPGA and systems researchers working on tightly coupled CPU-FPGA platforms, especially with coherent interconnects. They will get concrete design knowledge from the RoC overlay and the STE structure.\n\nMy recommendation: send it to peer review. It's a well-constructed artifact with reproducible engineering claims, and the missing numbers are measurable. Require a reconfiguration-time experiment and a throughput/drop experiment before accepting.","headline":"Dryas is a credible, genuinely useful FPGA tracing engine with a new overlay-NFA design, but its headline claims about line rate and sub-second reconfiguration are supported only by synthesis numbers and untimed assumptions, so the paper should be accepted conditionally after the authors measure what they assert.","tokens_in":14933,"tokens_out":1475,"would_cite":true,"duration_ms":16463,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Dryas claims that a small, runtime-reprogrammable NFA overlay can trace and filter a 30 GiB/s cache-coherent interconnect at line rate using only a few percent of the FPGA's logic, and can swap filters in under a second without stopping…","keywords":["FPGA tracing","interconnect analysis","NFA filtering","overlay architecture","runtime reconfiguration","cache coherence","line-rate filtering","state transition elements"],"falsifier":"Measure the end-to-end reconfiguration time on the test platform — from issuing a new filter over PCIe to the moment the new NFA is active — including the integer-program mapping time, for the largest filter described (the 7-state, fan-in-6 cache-miss classifier with 24 or 32 substreams); if that time reaches one second or more, the sub-second reconfiguration claim fails. A complementary test is to toggle filters repeatedly while the interconnect is running at full rate and check that no message is dropped or stalled during the switch.","tokens_in":14026,"feed_emoji":"⚡","tokens_out":10644,"duration_ms":93312,"temperature":0.7,"pith_summary":"This paper presents Dryas, a runtime-reprogrammable filter engine that taps into a 30 GiB/s cache-coherent CPU-FPGA interconnect and extracts specific message sequences at cache-line granularity, at full line rate. The central claim is that an NFA implemented as an overlay of state transition elements can express complex, protocol-level filters while consuming only a few percent of the FPGA's logic, and that the filters can be swapped in under a second without stopping the running application or resynthesizing the design. Such a tool matters because debugging and analyzing modern high-speed interconnects usually means capturing hundreds of gigabytes of traces or using limited hardware debuggers; Dryas aims to provide live, fine-grained visibility into protocol behavior and application memory patterns with negligible overhead. The paper evaluates scalability and shows two case studies: tracing cross-socket latency through the block and virtual-channel layers, and characterizing cache misses by type for a tree-walking workload.","feed_headline":"Dryas filters a 30 GiB/s coherent interconnect at line rate","feed_subtitle":"A tiny NFA-based overlay inspects cache-coherent traffic in real time and swaps filters in under a second.","key_machinery":"The central object is the rings-of-cliques (RoC) overlay graph: a static, parameterized network of state transition elements (STEs) defined by clique size, ring length, ring count, and neighbor-ring count, which at synthesis time trades off the number of NFA states against the connectivity available for transitions. Each STE implements one state of a homogeneous NFA and is runtime-configurable through its input-decoding lookup tables, its start/accept registers, and the enabled links to neighboring STEs, so a new filter is loaded by shifting a configuration bitstream through the overlay rather than by rebuilding the FPGA design. The input decoding computes arbitrary logic functions on the small set of predicates extracted from message headers, and a separate integer-program formulation maps NFA states to STEs, with the mapping solved by a standard IP solver.","core_discovery":"Dryas claims that a non-deterministic finite automaton (NFA) built from runtime-configurable state transition elements (STEs), wired in a static rings-of-cliques overlay graph on an FPGA, can filter a 30 GiB/s cache-coherent interconnect at full line rate while consuming only a few percent of the device's logic. The engine works by reducing each incoming or outgoing message to a small set of predicates over its header (type, virtual channel, opcode, address, direction), feeding those predicates to the NFA, and emitting only messages that trigger an accepting state. Because the STEs' lookup tables, start/accept registers, and inter-STE routing are all runtime-configurable, a new filter can be loaded in under a second by shifting a configuration bitstream through the overlay, with no FPGA re-synthesis and no interruption to the running application. The paper demonstrates this on a real coherent CPU-FPGA system with two uses: measuring cross-socket memory latency at the protocol layer, and classifying cache misses into compulsory, capacity/conflict, and coherence misses per cache line.","pith_inferences":["The 'under a second' reconfiguration claim is only as strong as the integer-program solver that maps an NFA onto the overlay; the paper does not report this mapping time, so a full filter-swap time budget for larger filters remains an open measurement (the weakest point of the paper).","The predicate-extraction front end is the only protocol-specific part, so the same overlay engine could plausibly filter other high-speed serial links (PCIe, CXL, Ethernet) by changing the header-reduction logic; this is an extension the paper does not itself demonstrate.","The engine's ability to observe interleaved substreams suggests a natural next use as a live coherence-protocol verifier, flagging protocol violations or deadlock conditions the moment they occur, rather than only filtering known patterns offline."],"forward_implications":["Dryas can be deployed alongside a large FPGA application and still trace the interconnect at full rate, since a 600-state configuration uses under 2.2% of the LUTs and 3.7% of the flip-flops of the target device.","Filters can be changed in under a second at runtime, without reprogramming the FPGA or stopping the running application, enabling interactive debugging of a live system.","The same overlay engine can be specialized to different protocol layers or different interconnects by changing only the synthesis-time predicate extraction, leaving the NFA engine itself protocol-agnostic.","In the evaluated scenarios Dryas reduces trace volume by a factor of over 10^5 (1.2 TiB of raw blocks down to a manageable filtered trace), cutting post-processing time correspondingly.","Because the overlay can be replicated or de-multiplexed onto substreams, Dryas can track per-cache-line state independently, as used to classify compulsory, capacity/conflict, and coherence misses."],"supporting_citations":[{"why":"Identifies the 48-core CPU/FPGA platform whose coherent interconnect is the target of Dryas.","marker":"[6]"},{"why":"Specifies the ECI protocol stack (block and virtual-channel layers) that Dryas taps into.","marker":"[21]"},{"why":"Defines the VC-layer message headers and message types from which Dryas's predicates are derived.","marker":"[17]"},{"why":"Introduces run-time parameterizable regex operators on FPGA overlays, the basis for the STE approach.","marker":"[12]"},{"why":"Presents a dynamically reconfigurable STE overlay for NFAs, from which Dryas adapts homogeneous-NFA mapping.","marker":"[14]"},{"why":"Describes a large-scale STE overlay for pattern matching, used to motivate Dryas's different trade-off of fewer states with richer input decoding.","marker":"[13]"},{"why":"Shows reconfiguring NFA overlays without resynthesis, the direct inspiration for sub-second filter changes.","marker":"[24]"},{"why":"Supplies the integer-program solver used to map NFA states to overlay STEs.","marker":"[11]"},{"why":"Documents the configurable lookup-table primitive used in each STE's input decoding.","marker":"[25]"}],"fun_headline_variants":["Sub-second filter swaps while tracing 30 GiB/s cache-coherent links","Tiny NFA overlay gives full-speed interconnect visibility","Run-time reprogrammable tracing engine for high-speed interconnects","Full-bandwidth trace debugging with instant filter changes","Rewrite filters in under a second without stopping traffic"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The claim that filters can be swapped in under a second rests on the unmeasured assumption that the integer-program mapping from a filter's NFA to the rings-of-cliques overlay completes in well under a second for every practical filter size and connectivity.","fun_headline_variants_meta":{"raw":{"variants":["Sub-second filter swaps while tracing 30 GiB/s cache-coherent links","Tiny NFA overlay gives full-speed interconnect visibility","Run-time reprogrammable tracing engine for high-speed interconnects","Full-bandwidth trace debugging with instant filter changes","Rewrite filters in under a second without stopping traffic"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000736,"raw_usage":{"total_tokens":3338,"prompt_tokens":1041,"completion_tokens":2297,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":657,"completion_tokens_details":{"reasoning_tokens":2216}},"tokens_in":657,"tokens_out":2297,"duration_ms":16530,"temperature":1.0,"reasoning_tokens":2216,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T20:17:32.348841+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the end-to-end reconfiguration time on the test platform — from issuing a new filter over PCIe to the moment the new NFA is active — including the integer-program mapping time, for the largest filter described (the 7-state, fan-in-6 cache-miss classifier with 24 or 32 substreams); if that time reaches one second or more, the sub-second reconfiguration claim fails. A complementary test is to toggle filters repeatedly while the interconnect is running at full rate and check that no message is dropped or stalled during the switch.","supporting_citations":[{"cited_title":"Enzian: an open, general, CPU /FPGA platform for systems software research","cited_arxiv_id":null,"evidence_quote":"Identifies the 48-core CPU/FPGA platform whose coherent interconnect is the target of Dryas."},{"cited_title":"CCKit: An open-source toolkit for cache coherent accelera- tors","cited_arxiv_id":null,"evidence_quote":"Specifies the ECI protocol stack (block and virtual-channel layers) that Dryas taps into."},{"cited_title":"Tools for Cache Coherence Protocol Inter- operability","cited_arxiv_id":null,"evidence_quote":"Defines the VC-layer message headers and message types from which Dryas's predicates are derived."},{"cited_title":"Run- time parameterizable regular expression operators for databases","cited_arxiv_id":null,"evidence_quote":"Introduces run-time parameterizable regex operators on FPGA overlays, the basis for the STE approach."},{"cited_title":"A dynamically reconfigurable automata pro- cessor overlay","cited_arxiv_id":null,"evidence_quote":"Presents a dynamically reconfigurable STE overlay for NFAs, from which Dryas adapts homogeneous-NFA mapping."},{"cited_title":"An Overlay Architecture for Pattern Matching","cited_arxiv_id":null,"evidence_quote":"Describes a large-scale STE overlay for pattern matching, used to motivate Dryas's different trade-off of fewer states with richer input decoding."},{"cited_title":"Skele- ton automata for FPGAs: reconfiguring without recon- structing","cited_arxiv_id":null,"evidence_quote":"Shows reconfiguring NFA overlays without resynthesis, the direct inspiration for sub-second filter changes."},{"cited_title":"Gurobi Optimizer Refer- ence Manual","cited_arxiv_id":null,"evidence_quote":"Supplies the integer-program solver used to map NFA states to overlay STEs."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Documents the configurable lookup-table primitive used in each STE's input decoding."}],"review_version":1}