{"id":"6e2f35fb-83f8-4243-a7bd-d76a6c36d921","arxiv_id":"2608.13143","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"A compute-in-memory inverter array is shown to independently program Gaussian mean and variance, and its simulated energy and rendering quality are reported for Gaussian splatting at the edge.","lead":"ProbSplat maps Gaussian mixtures onto programmable floating-gate inverter columns so that both the mean and variance of each Gaussian can be set by threshold voltages. The hardware is simulated to log-likelihood inference at 18 pJ and renders 3D scenes at around 22 dB PSNR at 8-bit, targeting edge AR/VR and robotics.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The reported 21.99 dB PSNR is computed from ideal Gaussian kernels constrained to the hardware's programming range, not from the simulated inverter-column currents, so the hardware's actual analog behavior never enters the fidelity check.","rationale":"The reader's conditional verdict identifies the same gap: the rendering evaluation uses re-parameterized Gaussians rather than actual inverter-column currents. I agree this is the least secure link in the central claim. The energy figures rest on explicitly stated \"ideal energy scaling\" assumptions, but even a conservative rescaling by a factor of two or three would leave the qualitative efficiency advantage intact; by contrast, the fidelity claim depends on the analog current shape being a usable Gaussian kernel, and the paper supplies no evidence for this. Section III quantifies the mean and variance of ISC but never compares the full ISC(Vz) curve with the Gaussian kernel used in Fig. 6. The self-acknowledged change in peak current with variance (\"Changing the variance will affect the maximum current as the overdrive voltage changes\") is a concrete mechanism by which a real current-summing readout would differ from the ideal renderer unless an explicit normalization scheme is described; none is. A single SPICE-in-the-loop rendering check would settle whether the 21.99 dB figure survives contact with the hardware. I therefore leave the verdict at conditional: the concern is a missing validation step, not a demonstrated contradiction, but it is load-bearing for the headline fidelity claim.","tokens_in":7575,"tokens_out":6304,"duration_ms":59596,"concrete_test":"Re-run the train-scene rendering by replacing each ideal Gaussian kernel with the SPICE-simulated ISC(Vz; VTn, |VTp|) for the exact threshold-voltage settings used in the Fig. 6 render, using the un-normalized column current as the component weight (as in a parallel current-sum readout), and recompute PSNR against the same ground truth; additionally report the L2 or KL divergence between each ISC curve and its best-fit Gaussian. If PSNR drops by more than 1 dB, or the divergence is large, the 21.99 dB fidelity claim is not supported by the hardware simulations.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Section IV and Fig. 6 compute PSNR from a software Gaussian-splatting renderer in which each component is an ideal Gaussian whose mean and covariance are constrained to the FG-inverter programming range (\"programmed within the constraints of 6T FG inverter columns\"). The actual analog output of the columns, namely the SPICE ISC(Vz) curve including its absolute peak magnitude, never enters the fidelity computation. Section III states that changing the variance changes the maximum current because the overdrive voltage changes; if the renderer normalizes or fixes the weight of each Gaussian kernel, it suppresses a hardware effect that would alter mixture weights in a real parallel-column current-summing readout. The paper reports no goodness-of-fit between ISC(Vz) and a Gaussian kernel, and the prior work on this 6T array describes the output as \"Gaussian-like\" (HMGM), not Gaussian. Therefore the headline claim that ProbSplat renders scenes at 21.99 dB PSNR is not yet a claim about the hardware's actual analog behavior; the 21.99 dB figure is a software rendering result with programmable-range constraints only.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript proposes ProbSplat, a compute-in-memory architecture based on 6T floating-gate inverter columns that programs both the mean and the variance of Gaussian mixture components by setting transistor threshold voltages. It reports TSMC 180nm SPICE simulations showing mean and variance programming with less than 2.4% deviation, and it projects energy per log-likelihood inference of 17.99 pJ at 4-bit precision and 202.57 pJ at 8-bit precision for a 500-column array. The architecture is applied to 3D Gaussian splatting using the train scene dataset, and the paper reports a rendering quality of 21.99 dB PSNR at 8-bit precision.","tokens_in":7803,"tokens_out":9952,"duration_ms":85179,"significance":"If the claims hold, the ability to program Gaussian means and variances independently in a standard floating-gate CMOS inverter array is a useful extension of the authors' prior HMGM work and could enable low-power probabilistic computing for edge 3D vision and robotics. The paper includes SPICE-level simulations, Monte Carlo sampling, explicit energy-modeling assumptions, and a real-scene rendering experiment, which are strengths. However, the headline fidelity and energy results are projections: the PSNR is computed from ideal Gaussian kernels in software rather than from the simulated analog column currents, and the energy numbers rely on ideal scaling of external ADC/DAC designs. The central independence claim also needs reconciliation with the mean drift shown in Fig. 5(b). These issues are load-bearing for the main claims but appear addressable in revision.","major_comments":[{"comment":"The 21.99 dB PSNR figure is computed from a software Gaussian-splatting renderer in which the means and covariances are constrained to the 6T FG inverter programming range, but the simulated ISC(Vz) curves, including their non-Gaussian shape and the peak-current variation with variance noted in Section III, do not enter the rendering. Consequently, the fidelity claim is not yet a claim about the hardware's actual analog behavior. Please recompute the rendering using the simulated column currents or provide a validated analytical model of ISC(Vz), and report a goodness-of-fit metric between ISC(Vz) and the Gaussian kernel used in the renderer.","section":"Section IV, Fig. 6"},{"comment":"The energy figures of 17.99 pJ and 202.57 pJ are obtained by ideal scaling of reference ADC and DAC designs, not from simulation or measurement of the proposed system, but the abstract presents them as consumption numbers. In addition, the DAC reference [19] is a NAND-flash memory paper, not a 10-bit DAC, so the 3-DAC energy estimate is not supported. Please relabel all energy numbers as projections, supply the correct DAC reference, justify the exponential bit-scaling assumption for the log-ADC, and state the simulation basis for the 5.67 pJ inverter-column energy.","section":"Section IV, Table I and Abstract"},{"comment":"The claimed mean-variance independence with 2.17-2.37% deviation appears inconsistent with Fig. 5(b), where sweeping VTn = |VTp| along the variance-programming axis shifts the peak location of ISC by roughly 0.25 V (from about 0.70 V to 0.95 V) for Wp = 3*Wn. This is a substantial fraction of the stated 0-0.9 V mean mapping range and exceeds the reported percentage. Please define the exact deviation metric used for the 2.37%/2.17% figures, specify the usable programming range over which the claim holds, and either demonstrate independence over that range or qualify the claim accordingly.","section":"Section III, Fig. 5(b) and Fig. 2 caption"},{"comment":"The comparison with a conventional digital implementation is not a controlled baseline: the 477 pJ figure is derived from a WFST speech-recognizer design and standard-cell library projections [20,21], not from a GMM or Gaussian-splatting processor, and the comparison uses different component counts (30 vs. 500 mixtures) and different workload assumptions. Please either remove the comparison or provide a matched baseline with the same task, technology, precision, and number of components.","section":"Section IV and Section II"}],"minor_comments":[{"comment":"The circuit outputs currents proportional to Gaussian kernel values; calling this 'log-likelihood inference' is imprecise. Please clarify that a log-ADC converts the summed current to a log-likelihood, or use 'likelihood evaluation' where appropriate.","section":"Abstract and Section II"},{"comment":"The variables Vx and Vy in the caption of Fig. 4 are not defined in the text. Please define them and describe the programming procedure for setting the floating-gate voltages.","section":"Section III, Fig. 4"},{"comment":"The statement 'In applications like gaussian splatting, the variances are typically low' should be justified or qualified, since 3D Gaussian splatting scenes can require a wide range of covariance values.","section":"Section III"},{"comment":"Please specify how the 6T FG inverter constraints (diagonal covariance, limited variance range, mean range) are imposed on the trained Gaussian splat parameters, and whether the Gaussians are re-fit or simply clipped to the hardware range.","section":"Section IV"},{"comment":"The claim that the mean and variance contours are orthogonal should be supported by a quantitative measure, since the simulations in Fig. 5(b) show a non-negligible cross-coupling.","section":"Fig. 7(a)"}],"recommendation":"major_revision","confidential_remarks":"The core idea of independently programming mean and variance in a 6T FG inverter array is a reasonable extension of the authors' prior work and the simulation data are a useful contribution. The main risks are that the PSNR result does not exercise the analog hardware model and that the energy numbers are over-stated in the abstract; both are fixable with a revision. The DAC citation error in Table I should be checked carefully before any acceptance. I see no circularity or novelty-disclosure problem, but the paper's claims should be recalibrated to distinguish projections from measured/simulated results."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"First, the real content: this paper shows you can tune both mean and variance of the 6T FG inverter column from Shukla et al. by coordinated changes in threshold voltages. The SPICE results are believable and the <2.4% coupling is honestly reported. That's a genuine extension, and the paper does a fair job explaining the trade-off between Wp:Wn ratio and mean drift.\n\nThe energy numbers are the weak spot, as you'd expect. The 18 pJ and 202 pJ figures are projections from external ADC/DAC designs with ideal scaling assumptions. That's not a crime in a conference paper, but it should be labeled as a projection, not a measurement.\n\nThe bigger issue is the PSNR claim. The 21.99 dB result in Fig. 6 is computed from a software renderer using ideal Gaussians whose parameters are constrained to the hardware's programming range. The actual ISC(Vz) curves never enter that fidelity check. The paper even notes that changing variance alters peak current, which would change mixture weights in a real current-summing readout, so the rendered scene could look different on actual hardware. I think the stress-test note is right on this. The hardware is 'Gaussian-like', not Gaussian, and the fidelity check doesn't test the hardware's analog behavior.\n\nThe paper is honest about its limitations: it acknowledges the deviations, it acknowledges the need for high-range ADC, and it cites prior work clearly. It's not a circular argument; the independent variance control is new.\n\nWho should read it? People building CIM for GMM evaluation and edge AR/VR hardware folks. It's a solid ISVLSI-level contribution. The central idea holds, but the headline PSNR and energy claims need to be taken with a big grain of salt until the analog output is directly characterized.\n\nI'd send it to peer review. It's a legitimate, well-scoped extension with new simulation evidence. But I'd ask the authors to either simulate a full column readout and compute PSNR from the actual ISC values, or at least add a goodness-of-fit plot showing how close ISC is to a Gaussian kernel.","headline":"A plausible, honestly-reported extension of the 6T FG inverter array to program mean and variance, but the headline PSNR and energy claims are projections, not hardware measurements.","tokens_in":8319,"tokens_out":2301,"would_cite":false,"duration_ms":19677,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A 6T floating-gate inverter column can be programmed to store and evaluate a Gaussian component, making Gaussian splatting likelihood run at 18 pJ per inference.","keywords":["Gaussian splatting","compute-in-memory","floating-gate inverter","probabilistic computing","Gaussian mixture model","energy-efficient hardware","3D scene reconstruction","threshold-voltage programming"],"falsifier":"Simulate or fabricate the 180-nm 6T floating-gate array, measure the actual $I_{SC}$ curves across the full programmed mean and variance range, and render a test scene using those measured currents instead of idealized Gaussian kernels; if the PSNR falls clearly below 21.99 dB or mean/variance deviations exceed roughly 2.4 percent, the independent-programmability and fidelity claims fail.","tokens_in":7389,"feed_emoji":"⚡","tokens_out":9595,"duration_ms":73064,"temperature":0.7,"pith_summary":"ProbSplat claims that a column of six-transistor floating-gate inverters can act as a programmable Gaussian mixture component in hardware, with the mean set by shifting the nMOS and pMOS threshold voltages in opposite directions and the variance set by shifting them in the same direction. Because the two shifts are orthogonal in the threshold-voltage plane, the mean and variance of each component can be tuned independently with less than 2.4 percent deviation, and the column's short-circuit current directly evaluates the component's log-likelihood. This converts Gaussian splatting from a digital sequence of multiplies, adds, and look-ups into an analog current readout, which the paper reports at 18 pJ per inference at 4-bit precision and 202.57 pJ at 8-bit precision across 500 mixture components. The same hardware-constrained Gaussians render a test scene at 21.99 dB PSNR at 8-bit precision, which the authors argue is acceptable for edge robotics and AR/VR scene reconstruction.","feed_headline":"Inverter columns compute Gaussian splatting at 18 pJ","feed_subtitle":"Threshold voltages set each Gaussian's mean and variance independently, cutting scene-reconstruction energy for edge hardware.","key_machinery":"The central object is the 6T floating-gate inverter column: six transistors whose floating-gate threshold voltages $V_{Tn}$ and $|V_{Tp}|$ are programmed to store a Gaussian component, and whose short-circuit current $I_{SC}$ evaluates that component's likelihood at the input voltage $V_z$. The key identity is the orthogonality of programming directions in the $(V_{Tn}, |V_{Tp}|)$ plane: shifting $V_{Tn}$ up by an amount and $|V_{Tp}|$ down by the same amount moves the mean, while shifting both by the same amount broadens or narrows the current spread and hence the variance. A pull-up to pull-down width ratio of $W_p = 3W_n$ minimizes the residual coupling between the two controls. This mechanism carries the argument because it replaces digital log-likelihood computation with an analog current that is already the stored-and-computed Gaussian value.","core_discovery":"The paper's discovery is a voltage-programming rule that makes a 6T floating-gate inverter column a faithful, independently tunable Gaussian-like element rather than a fixed-shape kernel. If $V_{Tn}$ and $|V_{Tp}|$ are treated as two programming axes, then moving the threshold voltages along a line of slope $-1$ changes only the mean, while moving them along a line of slope $+1$ changes only the variance; the contour lines of mean and variance in this plane are orthogonal, so the two parameters decouple. The short-circuit current $I_{SC}$ of each column then behaves as the component's likelihood current, and parallel columns sum a Gaussian mixture in the analog domain. ProbSplat applies this to 3D Gaussian splatting by mapping each scene Gaussian's mean and diagonal covariance to one inverter column, gating whole scene cells with digital control logic, and reading the mixture likelihood through a logarithmic ADC. Simulated in 180-nm CMOS at 1.8 V and 50 MHz, the design reports mean-variance independence with under 2.4 percent deviation, 18 pJ per 4-bit log-likelihood inference, 202.57 pJ per 8-bit inference with 500 mixture functions, and a rendered-scene PSNR of 21.99 dB.","pith_inferences":["Pith inference: because the mean and variance contours are orthogonal, the same threshold-voltage plane could in principle program other parametric kernels, such as Laplace or asymmetric shapes, by choosing nonlinear programming paths, extending the architecture beyond Gaussian mixtures.","Pith inference: the paper's fidelity check re-parameterizes the splatting Gaussians into the hardware's allowable mean and variance range; an end-to-end simulation that feeds actual $I_{SC}$ curves through the ADC would test how much analog non-ideality changes the 21.99 dB figure.","Pith inference: the energy comparison projects reference ADC and DAC designs to 180 nm and 1.8 V under ideal scaling; a fabricated ProbSplat prototype would be the decisive test of whether the 18 pJ and 202.57 pJ figures survive real peripheral overheads."],"forward_implications":["If the 6T column behaves as simulated, Gaussian splatting likelihood evaluation drops to 18 pJ at 4-bit precision, with the inverter columns contributing only 5.67 pJ and the logarithmic ADC dominating at 8-bit precision.","Scene reconstruction using hardware-constrained diagonal-covariance Gaussians reaches 21.99 dB PSNR at int8 precision, and raising the opacity threshold from 0.005 to 0.25 reduces the number of required 6T columns by 3.49x with only a modest PSNR penalty.","Because each scene cell is gated by 2-bit-per-axis digital control, only Gaussians near the queried position dissipate switching power, making energy scale with scene locality rather than full mixture size.","Mean and variance can be programmed independently across each column, so a scene's Gaussian components can have different spreads, not just the fixed variance of the earlier mean-only inverter design."],"supporting_citations":[{"why":"Provides the 6T floating-gate inverter column structure and current-based log-likelihood evaluation that ProbSplat extends from mean-only to mean-and-variance programming.","marker":"[15]"},{"why":"Supplies the 3D Gaussian splatting algorithm and the train scene dataset used for the rendered-PSNR evaluation.","marker":"[16]"},{"why":"Supplies the logarithmic ADC whose measured power is scaled to 180 nm and 1.8 V for the readout energy in the 4-bit and 8-bit estimates.","marker":"[18]"},{"why":"Supplies the DAC power figure used to estimate peripheral conversion energy in the 4-bit and 8-bit estimates.","marker":"[19]"},{"why":"Provides the conventional 65-nm digital implementation whose power is projected to 180 nm as the comparison baseline for the energy savings claim.","marker":"[20]"},{"why":"Supplies standard-cell power estimates used to project the conventional digital datapath's per-inference energy.","marker":"[21]"}],"fun_headline_variants":["Orthogonal threshold axes decouple mean and variance in 6T inverter column","18 pJ Gaussian splatting via analog inverter columns","Voltage-programmed Gaussian kernels cut 3D scene energy","Mean and variance decouple on a single float-gate column","CIM-inspired splatting: orthogonal threshold tuning"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that a real scene's Gaussians can be squeezed into the hardware's narrow, diagonal-covariance threshold-voltage range and that the analog column current tracks the intended Gaussian closely enough that render quality computed from the re-parameterized Gaussians is what the hardware would actually produce.","fun_headline_variants_meta":{"raw":{"variants":["Orthogonal threshold axes decouple mean and variance in 6T inverter column","18 pJ Gaussian splatting via analog inverter columns","Voltage-programmed Gaussian kernels cut 3D scene energy","Mean and variance decouple on a single float-gate column","CIM-inspired splatting: orthogonal threshold tuning"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000834,"raw_usage":{"total_tokens":3689,"prompt_tokens":1042,"completion_tokens":2647,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":658,"completion_tokens_details":{"reasoning_tokens":2561}},"tokens_in":658,"tokens_out":2647,"duration_ms":17482,"temperature":1.0,"reasoning_tokens":2561,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T15:48:48.694253+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Simulate or fabricate the 180-nm 6T floating-gate array, measure the actual $I_{SC}$ curves across the full programmed mean and variance range, and render a test scene using those measured currents instead of idealized Gaussian kernels; if the PSNR falls clearly below 21.99 dB or mean/variance deviations exceed roughly 2.4 percent, the independent-programmability and fidelity claims fail.","supporting_citations":[{"cited_title":"Ultralow-power localization of insect-scale drones: Interplay of probabilistic filtering and compute-in-memory,","cited_arxiv_id":null,"evidence_quote":"Provides the 6T floating-gate inverter column structure and current-based log-likelihood evaluation that ProbSplat extends from mean-only to mean-and-variance programming."},{"cited_title":"A 2.5 mw 80 db dr 36 db sndr 22 ms/s logarithmic pipeline adc,","cited_arxiv_id":null,"evidence_quote":"Supplies the logarithmic ADC whose measured power is scaled to 180 nm and 1.8 V for the readout energy in the 4-bit and 8-bit estimates."},{"cited_title":"A 6 mw, 5,000-word real- time speech recognizer using wfst models,","cited_arxiv_id":null,"evidence_quote":"Provides the conventional 65-nm digital implementation whose power is projected to 180 nm as the comparison baseline for the energy savings claim."},{"cited_title":"Performance comparisons between 7-nm finfet and conventional bulk cmos standard cell libraries,","cited_arxiv_id":null,"evidence_quote":"Supplies standard-cell power estimates used to project the conventional digital datapath's per-inference energy."}],"review_version":1}