Duet is a manycore-eFPGA architecture with cache-coherent integration that supports fine-grained acceleration and hardware augmentation, shown in RTL evaluation to cut communication latency by up to 82% and deliver 1.5-24.9x speedups on seven benchmarks.
Algorithms for Scalable Synchronization on Shared-Memory Multiprocessors
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CIDER improves throughput of memory-disaggregated KV stores by up to 6.6x on YCSB by replacing optimistic synchronization with pessimistic synchronization, global write-combining, and a contention-aware scheme.
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Duet: Creating Harmony between Processors and Embedded FPGAs
Duet is a manycore-eFPGA architecture with cache-coherent integration that supports fine-grained acceleration and hardware augmentation, shown in RTL evaluation to cut communication latency by up to 82% and deliver 1.5-24.9x speedups on seven benchmarks.
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CIDER: Boosting Memory-Disaggregated Key-Value Stores with Pessimistic Synchronization
CIDER improves throughput of memory-disaggregated KV stores by up to 6.6x on YCSB by replacing optimistic synchronization with pessimistic synchronization, global write-combining, and a contention-aware scheme.