{"schema":"pith.reference-change-event.v1","doi":"10.1038/s41928-021-00546-4","canonical_url":"https://pith.science/event/10.1038/s41928-021-00546-4","json_url":"https://pith.science/event/10.1038/s41928-021-00546-4.json","not_a_judgment":"This page records that a citing paper's bibliography includes a work with a published notice. It is not a judgment on the citing paper.","primary":{"event_id":245717,"doi":"10.1038/s41928-021-00546-4","event_type":"correction","event_type_label":"Correction","source":"crossref","source_label":"Crossref","event_date":"2021-07-27","title":"Author Correction: Scaling out Ising machines using a multi-chip architecture for simulated bifurcation","work_title":"Scaling out Ising machines using a multi-chip architecture for simulated bifurcation","work_doi":"10.1038/s41928-021-00546-4","work_arxiv_id":null,"notice_doi":"10.1038/s41928-021-00637-2","flag_count":0,"flags_open":0,"flags_disputed":0,"latest_flag_at":null,"human_href":"/event/10.1038/s41928-021-00546-4","json_href":"/event/10.1038/s41928-021-00546-4.json"},"events":[{"event_id":245717,"doi":"10.1038/s41928-021-00546-4","event_type":"correction","event_type_label":"Correction","source":"crossref","source_label":"Crossref","event_date":"2021-07-27","title":"Author Correction: Scaling out Ising machines using a multi-chip architecture for simulated bifurcation","work_title":"Scaling out Ising machines using a multi-chip architecture for simulated bifurcation","work_doi":"10.1038/s41928-021-00546-4","work_arxiv_id":null,"notice_doi":"10.1038/s41928-021-00637-2","flag_count":0,"flags_open":0,"flags_disputed":0,"latest_flag_at":null,"human_href":"/event/10.1038/s41928-021-00546-4","json_href":"/event/10.1038/s41928-021-00546-4.json"}],"flags":[{"id":8910,"status":"open","status_label":"Open","citing_arxiv_id":"2506.16924","citing_title":"Real-Time Black-Box Optimization for Dynamic Discrete Environments Using Embedded Ising Machines","ref_index":24,"evidence_raw":"K. Tatsumura, M. Yamasaki, and H. Goto. “Scaling out Ising machines using a multi-chip architecture for simulated bifurcation”. In: Nature Electronics 4.3 (2021), pp. 208–217. doi: 10.1038/s41928-021-00546-4","evidence_cleaned":null,"evidence_source_label":"bibliography line","event_type":"correction","event_type_label":"Correction","source_label":"Crossref","event_date":"2021-07-27","work_title":"Scaling out Ising machines using a multi-chip architecture for simulated bifurcation","work_doi":"10.1038/s41928-021-00546-4","event_doi":"10.1038/s41928-021-00546-4","flag_href":"/flags/8910","event_href":"/event/10.1038/s41928-021-00546-4","paper_href":"/paper/2506.16924","created_at":"2026-08-07T06:19:20.141415Z","dispute_note":null,"disputed_at":null,"disputed_by":null}],"flag_count":1,"flags_open":1,"flags_disputed":0,"desk_url":"https://pith.science/flags"}