pith. sign in

arxiv: 2409.08290 · v4 · submitted 2024-08-29 · 💻 cs.NE · cs.AI· cs.LG

Reconsidering the energy efficiency of spiking neural networks

Zhanglu Yan , Zhenyu Bai , Weng-Fai Wong This is my paper

Pith reviewed 2026-05-23 21:35 UTC · model grok-4.3

classification 💻 cs.NE cs.AIcs.LG
keywords spiking neural networksenergy efficiencyquantized neural networksneuromorphic hardwarespike ratedata movementanalytical energy modelrate encoding
0
0 comments X

The pith

Spiking neural networks beat equivalent quantized networks in energy use only when average spike rates stay below 6.4 percent on typical neuromorphic hardware.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper re-evaluates the energy efficiency of spiking neural networks by creating a fair baseline against quantized neural networks. It maps rate-encoded SNNs that use T timesteps to QNNs that use ceil(log2(T+1)) bits so both have matching representational capacity and hardware needs. A detailed analytical energy model that counts both core computation and data movement overheads is applied across ranges of T, spike rate, model size, sparsity, and hardware parameters. The results show SNNs deliver lower energy only inside narrow operating windows, and one concrete example is that such an optimized SNN can nearly double the battery life of a typical smartwatch.

Core claim

By establishing a fair baseline through mapping rate-encoded SNNs with T timesteps to functionally equivalent QNNs using ceil(log2(T+1)) bits, and applying an analytical energy model that includes both computation and data movement, the paper identifies specific regimes where SNNs are more energy efficient, for instance requiring an average spike rate below 6.4 percent for T in [5,10] under typical neuromorphic hardware conditions, and shows that this can nearly double the operational lifetime of a smartwatch relative to the equivalent QNN.

What carries the argument

The fair baseline mapping of rate-encoded SNNs with T timesteps to QNNs using ceil(log2(T+1)) bits, together with the analytical energy model that accounts for computation plus data movement and memory access.

If this is right

  • SNNs with moderate time windows T in [5,10] require spike rates below 6.4 percent to outperform equivalent QNNs on typical neuromorphic hardware.
  • An optimized SNN can nearly double the battery life of a typical smartwatch compared with a QNN.
  • Energy evaluations of SNNs must include data movement and memory access costs rather than computation alone.
  • Advantageous regimes for SNNs depend on the combination of network size, weight bit width, QNN sparsity, and network-on-chip characteristics.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Hardware architects could target lower data-movement energy to widen the parameter region where SNNs win.
  • Training techniques that reliably achieve spike rates under 6 percent would expand the practical use cases for SNNs.
  • The same mapping and energy model could be applied to other event-driven accelerators to locate their efficiency boundaries.
  • Similar re-examinations might be warranted for hybrid analog-digital neuromorphic designs.

Load-bearing premise

The mapping of SNNs with T timesteps to QNNs using ceil(log2(T+1)) bits produces models that have comparable representational capacity and similar hardware requirements.

What would settle it

Direct energy measurement on actual neuromorphic hardware for an SNN with T between 5 and 10 at a spike rate of 6 percent versus its mapped QNN counterpart, checking whether total energy per inference is lower for the SNN.

Figures

Figures reproduced from arXiv: 2409.08290 by Weng-Fai Wong, Zhanglu Yan, Zhenyu Bai.

Figure 1
Figure 1. Figure 1: Integrate-and-fire SNN model memory operations is becoming even dominating over the energy spent by the computations themself [13], [14], [15], [16]. For instance, while SNNs often claim to be event￾driven [17], therefore leverages spike-train sparsity to skip computations, this mechanism require multiple data ac￾cesses per neuron activation cycles (T ×sr times per weight, where T the timesteps and sr the … view at source ↗
Figure 2
Figure 2. Figure 2: A classical neuromorphic processing element (PE) [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Energy ratio ESNN/EANN across SNN Model Configurations (rows, defined by T, sr) and Hardware Settings (columns). Within each cell, three bars correspond to comparing the SNN against QNNs with three activation densities. All calculations assume Nsrc = 4096 and 8-bit weights. Fundamental operational costs are: EACC = 0.05448 pJ, ECMP = 0.05448 pJ, ESUB = 0.05448 pJ, and Eweight = 0.18 pJ. The QNN EMAC cost v… view at source ↗
Figure 4
Figure 4. Figure 4: Mac vs Acc tions. The first centers around purely brain-inspired methodologies—algorithmic innovations and neuromor￾phic hardware—to emulate the functionalities of the human brain [31], [32], [33]. Despite significant exploration, brain￾inspired algorithms consistently fall short compared to con￾ventional neural networks enhanced by GPU acceleration, especially in terms of performance, speed, and scalabili… view at source ↗
Figure 5
Figure 5. Figure 5: Sensitivity analysis of SNN and QNN energy consumption (pJ) versus SNN spike rate ( [PITH_FULL_IMAGE:figures/full_fig_p009_5.png] view at source ↗
read the original abstract

Spiking Neural Networks (SNNs) promise higher energy efficiency over conventional Quantized Artificial Neural Networks (QNNs) due to their event-driven, spike-based computation. However, prevailing energy evaluations often oversimplify, focusing on computational aspects while neglecting critical overheads like comprehensive data movement and memory access. Such simplifications can lead to misleading conclusions regarding the true energy benefits of SNNs. This paper presents a rigorous re-evaluation. We establish a fair baseline by mapping rate-encoded SNNs with $T$ timesteps to functionally equivalent QNNs with $\lceil \log_2(T+1) \rceil$ bits. This ensures both models have comparable representational capacities, as well has similar hardware requirement, enabling meaningful energy comparisons. We introduce a detailed analytical energy model encompassing core computation and data movement. Using this model, we systematically explore a wide parameter space, including intrinsic network characteristics ($T$, spike rate $s_r$, QNN sparsity $\gamma$, model size $N$, weight bit-level) and hardware characteristics (memory system and network-on-chip). Our analysis identifies specific operational regimes where SNNs genuinely offer superior energy efficiency. For example, under typical neuromorphic hardware conditions, SNNs with moderate time windows ($T \in [5,10]$) require an average spike rate ($s_r$) below 6.4\% to outperform equivalent QNNs. Furthermore, to illustrate the real-world implications of our findings, we analyze the operational lifetime of a typical smartwatch, showing that an optimized SNN can nearly double its battery life compared to a QNN. These insights guide the design of turely energy-efficient neural network solutions.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript claims that by mapping rate-encoded SNNs with T timesteps to functionally equivalent QNNs using ⌈log₂(T+1)⌉ bits (ensuring comparable representational capacity and hardware requirements), and applying a detailed analytical energy model that includes computation plus data movement/NoC/memory costs, SNNs outperform QNNs only when the average spike rate sr falls below 6.4% for moderate T ∈ [5,10] under typical neuromorphic hardware. The work further claims that an optimized SNN can nearly double the operational lifetime of a typical smartwatch battery relative to the QNN baseline, after systematic sweeps over network parameters (T, sr, γ, N, weight bits) and hardware parameters.

Significance. If the analytical model and equivalence mapping are accurate, the paper makes a useful contribution by replacing oversimplified SNN-vs-QNN comparisons with concrete operational regimes and a practical battery-life illustration. The inclusion of data-movement costs and the breadth of the explored parameter space are strengths that could guide neuromorphic design choices.

major comments (2)
  1. [Abstract] Abstract: The central 6.4% sr threshold rests on the claim that the ⌈log₂(T+1)⌉-bit QNN mapping yields 'similar hardware requirement.' The text does not indicate whether the energy model multiplies memory traffic and state accesses by T to reflect the temporal unfolding of rate-coded SNNs versus the single-pass QNN; if this scaling is omitted, SNN energy is underestimated and the reported crossover sr is shifted.
  2. [Abstract] Abstract: The quantitative results (6.4% threshold, near-doubling of battery life) are derived from externally supplied hardware parameters with no reported validation against measured energy traces, error bars, or sensitivity analysis on those parameters, leaving the specific numerical claims without empirical support.
minor comments (2)
  1. [Abstract] Abstract: 'as well has similar hardware requirement' should read 'as well as similar hardware requirements.'
  2. [Abstract] Abstract: 'turely energy-efficient' is a typo for 'truly energy-efficient.'

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments. We respond to each major comment below.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The central 6.4% sr threshold rests on the claim that the ⌈log₂(T+1)⌉-bit QNN mapping yields 'similar hardware requirement.' The text does not indicate whether the energy model multiplies memory traffic and state accesses by T to reflect the temporal unfolding of rate-coded SNNs versus the single-pass QNN; if this scaling is omitted, SNN energy is underestimated and the reported crossover sr is shifted.

    Authors: The analytical energy model in the full manuscript explicitly scales memory traffic, state accesses, and related data-movement costs by T for rate-encoded SNNs to reflect their temporal unfolding, while the equivalent QNN incurs these costs only once. This is described in the methods and energy-model sections. The abstract summarizes the outcome but does not spell out this scaling detail; we will revise the abstract to state explicitly that the model incorporates the T-fold unfolding for SNNs. revision: yes

  2. Referee: [Abstract] Abstract: The quantitative results (6.4% threshold, near-doubling of battery life) are derived from externally supplied hardware parameters with no reported validation against measured energy traces, error bars, or sensitivity analysis on those parameters, leaving the specific numerical claims without empirical support.

    Authors: Hardware parameters are taken from published neuromorphic-platform characterizations, and the manuscript already reports systematic sweeps over both network and hardware parameters (T, sr, γ, N, weight bits, memory hierarchy, NoC). We agree that framing these sweeps more explicitly as a sensitivity analysis, together with error bars on derived quantities where feasible, would improve clarity. We will add such a section. Direct validation against measured energy traces on physical hardware lies outside the scope of the present analytical study. revision: partial

Circularity Check

0 steps flagged

No circularity in the derivation chain

full rationale

The paper defines an equivalence mapping between rate-encoded SNNs (T timesteps) and QNNs (⌈log₂(T+1)⌉ bits) as a modeling choice to enable comparison, then applies an independent analytical energy model that incorporates computation, data movement, memory, and NoC costs. The 6.4% spike-rate threshold for T ∈ [5,10] is produced by systematic exploration of the parameter space (T, sr, γ, N, bit-width, hardware specs) rather than by fitting to the target data or by any self-referential definition. No load-bearing self-citations, uniqueness theorems, or ansatzes are invoked that would reduce the central claim to its own inputs; the derivation remains self-contained against external hardware parameters.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on the validity of the analytical energy model (whose equations are not shown) and on the representational-equivalence mapping; both are introduced in the abstract without external benchmarks or prior derivation.

axioms (1)
  • domain assumption The bit-width mapping ⌈log₂(T+1)⌉ produces networks of comparable representational capacity and hardware cost.
    Invoked to establish the fair baseline for energy comparison.

pith-pipeline@v0.9.0 · 5841 in / 1330 out tokens · 33610 ms · 2026-05-23T21:35:15.775620+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Forward citations

Cited by 4 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Plug-and-Play Spiking Operators: Breaking the Nonlinearity Bottleneck in Spiking Transformers

    cs.LG 2026-05 unverdicted novelty 6.0

    A modular framework decomposes Transformer nonlinearities into spike-compatible primitives realized via LIF population coding and bit-shift scaling, supporting Softmax, SiLU, and normalization with under 1% accuracy d...

  2. Energy-Efficient Implementation of Spiking Recurrent Cells on FPGA

    cs.NE 2026-05 conditional novelty 5.0

    An FPGA implementation of SRC-based SNNs reaches 96.31% MNIST accuracy at 1.74 ms per digit and drops to 0.45 mJ per digit with 4-bit weights and shorter traces while retaining richer dynamics than LIF models.

  3. Energy-Efficient Implementation of Spiking Recurrent Cells on FPGA

    cs.NE 2026-05 conditional novelty 5.0

    Simplified Spiking Recurrent Cells enable FPGA SNNs to reach 92-96% MNIST accuracy at 0.45-1.74 mJ per classification while retaining richer dynamics than basic LIF models.

  4. ShiftLIF: Efficient Multi-Level Spiking Neurons with Power-of-Two Quantization

    cs.NE 2026-05 unverdicted novelty 5.0

    ShiftLIF maps membrane potentials to logarithmically spaced power-of-two spike levels, improving representational capacity in SNNs while keeping synaptic operations multiplier-free.

Reference graph

Works this paper leans on

41 extracted references · 41 canonical work pages · cited by 3 Pith papers · 2 internal anchors

  1. [1]

    Train- ing spiking neural networks using lessons from deep learning,

    J. K. Eshraghian, M. Ward, E. O. Neftci, X. Wang, G. Lenz, G. Dwivedi, M. Bennamoun, D. S. Jeong, and W. D. Lu, “Train- ing spiking neural networks using lessons from deep learning,” Proceedings of the IEEE, 2023

    work page 2023

  2. [2]

    A discrete time framework for spike transfer process in a cortical neuron with asynchronous epsp, ipsp, and variable threshold,

    C. Ganguly and S. Chakrabarti, “A discrete time framework for spike transfer process in a cortical neuron with asynchronous epsp, ipsp, and variable threshold,” IEEE Transactions on Neural Systems and Rehabilitation Engineering , vol. 28, no. 4, pp. 772–781, 2020

    work page 2020

  3. [3]

    Con- version of continuous-valued deep networks to efficient event- driven networks for image classification,

    B. Rueckauer, I.-A. Lungu, Y. Hu, M. Pfeiffer, and S.-C. Liu, “Con- version of continuous-valued deep networks to efficient event- driven networks for image classification,” Frontiers in Neuroscience, vol. 11, p. 682, 2017

    work page 2017

  4. [4]

    Dynamic threshold integrate and fire neuron model for low latency spiking neural networks,

    X. Wu, Y. Zhao, Y. Song, Y. Jiang, Y. Bai, X. Li, Y. Zhou, X. Yang, and Q. Hao, “Dynamic threshold integrate and fire neuron model for low latency spiking neural networks,” Neurocomputing, vol. 544, p. 126247, 2023

    work page 2023

  5. [5]

    Neuronal variability: noise or part of the signal?

    R. B. Stein, E. R. Gossen, and K. E. Jones, “Neuronal variability: noise or part of the signal?” Nature Reviews Neuroscience , vol. 6, no. 5, pp. 389–397, 2005

    work page 2005

  6. [6]

    Philosophy of the spike: rate-based vs. spike-based theories of the brain,

    R. Brette, “Philosophy of the spike: rate-based vs. spike-based theories of the brain,” Frontiers in systems neuroscience , vol. 9, p. 151, 2015

    work page 2015

  7. [7]

    Spikingformer: Spike-driven residual learning for transformer- based spiking neural network,

    C. Zhou, L. Yu, Z. Zhou, Z. Ma, H. Zhang, H. Zhou, and Y. Tian, “Spikingformer: Spike-driven residual learning for transformer- based spiking neural network,” arXiv preprint arXiv:2304.11954 , 2023

    work page arXiv 2023

  8. [8]

    Spikingbert: Distilling bert to train spik- ing language models using implicit differentiation,

    M. Bal and A. Sengupta, “Spikingbert: Distilling bert to train spik- ing language models using implicit differentiation,” in Proceedings of the AAAI conference on artificial intelligence , vol. 38, no. 10, 2024, pp. 10 998–11 006

    work page 2024

  9. [9]

    Spikelm: Towards general spike-driven lan- guage modeling via elastic bi-spiking mechanisms,

    X. Xing, Z. Zhang, Z. Ni, S. Xiao, Y. Ju, S. Fan, Y. Wang, J. Zhang, and G. Li, “Spikelm: Towards general spike-driven lan- guage modeling via elastic bi-spiking mechanisms,” arXiv preprint arXiv:2406.03287, 2024. JOURNAL OF LATEX CLASS FILES 11

    work page arXiv 2024

  10. [10]

    Sorbet: A neuromor- phic hardware-compatible transformer-based spiking language model,

    K. Tang, Z. Yan, and W.-F. Wong, “Sorbet: A neuromor- phic hardware-compatible transformer-based spiking language model,” arXiv preprint arXiv:2409.15298, 2024

    work page arXiv 2024

  11. [11]

    Are snns really more energy-efficient than anns? an in-depth hardware-aware study,

    M. Dampfhoffer, T. Mesquida, A. Valentian, and L. Anghel, “Are snns really more energy-efficient than anns? an in-depth hardware-aware study,” IEEE Transactions on Emerging Topics in Computational Intelligence, vol. 7, no. 3, pp. 731–741, 2022

    work page 2022

  12. [12]

    Cq ++ training: Minimizing accuracy loss in conversion from convolutional neural networks to spiking neural networks,

    Z. Yan, J. Zhou, and W.-F. Wong, “Cq ++ training: Minimizing accuracy loss in conversion from convolutional neural networks to spiking neural networks,” IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 45, no. 10, pp. 11 600–11 611, 2023

    work page 2023

  13. [13]

    1.1 computing’s energy problem (and what we can do about it),

    M. Horowitz, “1.1 computing’s energy problem (and what we can do about it),” in 2014 IEEE international solid-state circuits conference digest of technical papers (ISSCC). IEEE, 2014, pp. 10–14

    work page 2014

  14. [14]

    Efficient processing of deep neural networks: A tutorial and survey,

    V . Sze, Y.-H. Chen, T.-J. Yang, and J. S. Emer, “Efficient processing of deep neural networks: A tutorial and survey,” Proceedings of the IEEE, vol. 105, no. 12, pp. 2295–2329, 2017

    work page 2017

  15. [15]

    Eyeriss v2: A flex- ible accelerator for emerging deep neural networks on mobile devices,

    Y.-H. Chen, T.-J. Yang, J. Emer, and V . Sze, “Eyeriss v2: A flex- ible accelerator for emerging deep neural networks on mobile devices,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 9, no. 2, pp. 292–308, 2019

    work page 2019

  16. [16]

    A method to estimate the energy consumption of deep neural networks,

    T.-J. Yang, Y.-H. Chen, J. Emer, and V . Sze, “A method to estimate the energy consumption of deep neural networks,” in 2017 51st asilomar conference on signals, systems, and computers . IEEE, 2017, pp. 1916–1920

    work page 2017

  17. [17]

    Event-driven learning for spiking neural networks,

    W. Wei, M. Zhang, J. Zhang, A. Belatreche, J. Wu, Z. Xu, X. Qiu, H. Chen, Y. Yang, and H. Li, “Event-driven learning for spiking neural networks,” arXiv preprint arXiv:2403.00270, 2024

    work page arXiv 2024

  18. [18]

    Compute substrate for software 2.0,

    J. Vasiljevic, L. Bajic, D. Capalija, S. Sokorac, D. Ignjatovic, L. Bajic, M. Trajkovic, I. Hamer, I. Matosevic, A. Cejkov et al. , “Compute substrate for software 2.0,” IEEE micro, vol. 41, no. 2, pp. 50–55, 2021

    work page 2021

  19. [19]

    Cerebras architecture deep dive: First look inside the hw/sw co-design for deep learning: Cerebras systems,

    S. Lie, “Cerebras architecture deep dive: First look inside the hw/sw co-design for deep learning: Cerebras systems,” in 2022 IEEE Hot Chips 34 Symposium (HCS) . IEEE Computer Society, 2022, pp. 1–34

    work page 2022

  20. [20]

    Sambanova sn10 rdu: A 7nm dataflow architecture to accelerate software 2.0,

    R. Prabhakar, S. Jairath, and J. L. Shin, “Sambanova sn10 rdu: A 7nm dataflow architecture to accelerate software 2.0,” in2022 IEEE International Solid-State Circuits Conference (ISSCC), vol. 65. IEEE, 2022, pp. 350–352

    work page 2022

  21. [21]

    Loihi asynchronous neuromorphic research chip,

    A. Lines, P . Joshi, R. Liu, S. McCoy, J. Tse, Y.-H. Weng, and M. Davies, “Loihi asynchronous neuromorphic research chip,” Energy, vol. 10, no. 15, pp. 10–1109, 2018

    work page 2018

  22. [22]

    Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip,

    F. Akopyan, J. Sawada, A. Cassidy, R. Alvarez-Icaza, J. Arthur, P . Merolla, N. Imam, Y. Nakamura, P . Datta, G.-J. Nam et al. , “Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip,” IEEE transactions on computer- aided design of integrated circuits and systems , vol. 34, no. 10, pp. 1537–1557, 2015

    work page 2015

  23. [23]

    Neural inference at the frontier of energy, space, and time,

    D. S. Modha, F. Akopyan, A. Andreopoulos, R. Appuswamy, J. V . Arthur, A. S. Cassidy, P . Datta, M. V . DeBole, S. K. Esser, C. O. Otero et al., “Neural inference at the frontier of energy, space, and time,” Science, vol. 382, no. 6668, pp. 329–335, 2023

    work page 2023

  24. [24]

    Loihi: A neuromorphic manycore processor with on-chip learning,

    M. Davies, N. Srinivasa, T.-H. Lin, G. Chinya, Y. Cao, S. H. Choday, G. Dimou, P . Joshi, N. Imam, S. Jainet al., “Loihi: A neuromorphic manycore processor with on-chip learning,” Ieee Micro , vol. 38, no. 1, pp. 82–99, 2018

    work page 2018

  25. [25]

    The brainscales-2 accelerated neuromorphic system with hybrid plas- ticity front,

    C. Pehle, S. Billaudelle, B. Cramer, J. Kaiser, K. Schreiber, Y. Strad- mann, J. Weis, A. Leibfried, E. M ¨uller, and J. Schemmel, “The brainscales-2 accelerated neuromorphic system with hybrid plas- ticity front,” 2022

    work page 2022

  26. [26]

    LLaMA: Open and Efficient Foundation Language Models

    H. Touvron, T. Lavril, G. Izacard, X. Martinet, M.-A. Lachaux, T. Lacroix, B. Rozi`ere, N. Goyal, E. Hambro, F. Azharet al., “Llama: Open and efficient foundation language models,” arXiv preprint arXiv:2302.13971, 2023

    work page internal anchor Pith review Pith/arXiv arXiv 2023

  27. [27]

    Diet-snn: A low-latency spiking neural network with direct input encoding and leakage and threshold optimization,

    N. Rathi and K. Roy, “Diet-snn: A low-latency spiking neural network with direct input encoding and leakage and threshold optimization,” IEEE Transactions on Neural Networks and Learning Systems, vol. 34, no. 6, pp. 3174–3182, 2023

    work page 2023

  28. [28]

    Low latency conversion of artificial neural network models to rate-encoded spiking neural networks,

    Z. Yan, K. Tang, J. Zhou, and W.-F. Wong, “Low latency conversion of artificial neural network models to rate-encoded spiking neural networks,” IEEE Transactions on Neural Networks and Learning Systems, pp. 1–12, 2025

    work page 2025

  29. [29]

    Deep spiking neural network: Energy ef- ficiency through time based coding,

    B. Han and K. Roy, “Deep spiking neural network: Energy ef- ficiency through time based coding,” in European conference on computer vision. Springer, 2020, pp. 388–404

    work page 2020

  30. [30]

    Rmp-snn: Residual membrane po- tential neuron for enabling deeper high-accuracy and low-latency spiking neural network,

    B. Han, G. Srin, and K. Roy, “Rmp-snn: Residual membrane po- tential neuron for enabling deeper high-accuracy and low-latency spiking neural network,” in Proceedings of the IEEE/CVF conference on computer vision and pattern recognition , 2020, pp. 13 558–13 567

    work page 2020

  31. [31]

    Brain-inspired computing: A systematic survey and future trends,

    G. Li, L. Deng, H. Tang, G. Pan, Y. Tian, K. Roy, and W. Maass, “Brain-inspired computing: A systematic survey and future trends,” Proceedings of the IEEE, 2024

    work page 2024

  32. [32]

    Brain-inspired methods for achieving robust computation in heterogeneous mixed-signal neuromorphic processing systems,

    D. Zendrikov, S. Solinas, and G. Indiveri, “Brain-inspired methods for achieving robust computation in heterogeneous mixed-signal neuromorphic processing systems,” Neuromorphic Computing and Engineering, vol. 3, no. 3, p. 034002, 2023

    work page 2023

  33. [33]

    Review of spike-based neuromorphic computing for brain-inspired vision: biology, algorithms, and hardware,

    H. Hendy and C. Merkel, “Review of spike-based neuromorphic computing for brain-inspired vision: biology, algorithms, and hardware,” Journal of Electronic Imaging, vol. 31, no. 1, pp. 010 901– 010 901, 2022

    work page 2022

  34. [34]

    Neuromorphic com- puting for interactive robotics: a systematic review,

    M. Aitsam, S. Davies, and A. Di Nuovo, “Neuromorphic com- puting for interactive robotics: a systematic review,” Ieee Access , vol. 10, pp. 122 261–122 279, 2022

    work page 2022

  35. [35]

    Real-time visual data processing us- ing neuromorphic systems,

    N. Ghoshal and B. Tripathy, “Real-time visual data processing us- ing neuromorphic systems,” in Primer to Neuromorphic Computing. Elsevier, 2025, pp. 161–183

    work page 2025

  36. [36]

    Neuromorphic hardware for artificial sensory systems: A review,

    Y. Kim, C. W. Lee, and H. W. Jang, “Neuromorphic hardware for artificial sensory systems: A review,” Journal of Electronic Materials, pp. 1–42, 2025

    work page 2025

  37. [37]

    Time- to-first-spike coding in sensory neuron for energy-efficient spiking neural networks,

    J.-H. Lee, S.-H. Hwang, W. Jo, K.-U. Byeon, and J.-K. Han, “Time- to-first-spike coding in sensory neuron for energy-efficient spiking neural networks,” IEEE Electron Device Letters, 2025

    work page 2025

  38. [38]

    First-to-spike-time of neuronal models with multiple morphologies under three spatial distribution patterns of the excitatory and inhibitory inputs,

    R. Wang and J. Liang, “First-to-spike-time of neuronal models with multiple morphologies under three spatial distribution patterns of the excitatory and inhibitory inputs,” Nonlinear Dynamics, pp. 1– 17, 2025

    work page 2025

  39. [39]

    A hybrid spiking model for anomaly detection in multivariate time series,

    W. Zhang, P . He, S. Wang, F. Yang, and Y. Liu, “A hybrid spiking model for anomaly detection in multivariate time series,” Expert Systems, vol. 42, no. 8, p. e70086, 2025

    work page 2025

  40. [40]

    SparrowSNN: A Hardware/software Co-design for Energy Efficient ECG Classification

    Z. Yan, Z. Bai, T. Mitra, and W.-F. Wong, “Sparrowsnn: A hard- ware/software co-design for energy efficient ecg classification,” arXiv preprint arXiv:2406.06543, 2024

    work page internal anchor Pith review Pith/arXiv arXiv 2024

  41. [41]

    Spikellm: Scaling up spiking neural network to large language models via saliency-based spiking,

    X. Xing, B. Gao, Z. Zhang, D. A. Clifton, S. Xiao, L. Du, G. Li, and J. Zhang, “Spikellm: Scaling up spiking neural network to large language models via saliency-based spiking,” arXiv preprint arXiv:2407.04752, 2024

    work page arXiv 2024