{"as_of":"2026-08-16T09:27:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:4d96395f76fef7081d6af620d35f5e177160d93b837dba98b2fc659740cdb573","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":1,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-16T06:30:59.297886+00:00","state":"measured"},{"denominator":1,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":1,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-14T12:45:40.651646Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"pith","source_observed_at":"2026-08-14T12:45:40.717003Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"1708.04198","last_updated":"2017-08-16T17:50:21Z","snapshot_observed_at":"2026-08-14T20:41:29.754758Z","submitted_at":"2017-08-14T16:28:02Z","title":"A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)","version":2},"cited_work":{"arxiv_id":"1708.04198","doi":null,"metadata_source":"pith","pith_arxiv_id":"1708.04198","snapshot_observed_at":"2026-08-14T12:45:40.717003Z","title":"A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)","venue":"cs.AR","work_id":"310a6d45-71bb-41d9-98f9-267a7c71dc6e","year":2017},"citing_paper":{"arxiv_id":"1908.07413","last_updated":"2019-08-18T22:43:19Z","snapshot_observed_at":"2026-08-16T08:00:10.244672Z","submitted_at":"2019-08-18T22:43:19Z","title":"A bi-directional Address-Event transceiver block for low-latency inter-chip communication in neuromorphic systems","version":1},"reference_index":4,"source":"arxiv_source","source_observed_at":"2026-08-14T12:45:40.651646Z"},"links":{"cited_paper":"/paper/1708.04198","citing_paper":"/paper/1908.07413"},"observation_digest":"sha256:0d4fca9fb3c215bf6fc78f39e24c811da4453cd741a2a83b88856ea8027483ae","observation_id":"b81d7912-3504-44c6-b2a8-748e7fb8b464","resolution":{"observed_at":"2026-08-14T12:45:40.724485Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/1708.04198/citation-record","integrity":"/paper/1708.04198/integrity","json":"/paper/1708.04198/citation-record.json","paper":"/paper/1708.04198"},"outbound":[],"paper":{"arxiv_id":"1708.04198","last_updated":"2017-08-16T17:50:21Z","latest_version":2,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-14T20:41:29.754758Z","submitted_at":"2017-08-14T16:28:02Z","title":"A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"thesis":"As of 16 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 1 inbound Pith citation observation for arXiv:1708.04198."}