{"as_of":"2026-08-12T07:54:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:6efbf7cad19410ea0503e437205ae126b7c31bc42887fc1b488ddc188f21fd73","coverage":[{"denominator":71,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":71,"source":"paper_references, paper_reference_links","source_observed_at":"2026-05-25T09:19:39.479960Z","state":"measured"},{"denominator":72,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":72,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-12T06:34:41.77262+00:00","state":"measured"},{"denominator":1,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":1,"source":"paper_references, paper_reference_links","source_observed_at":"2026-05-25T09:19:39.479960Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"pith","source_observed_at":"2026-05-25T09:20:34.499332Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"cited_work":{"arxiv_id":"1907.02167","doi":null,"metadata_source":"pith","pith_arxiv_id":"1907.02167","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","venue":"cs.AR","work_id":"c43fe8e8-df0e-4885-a50f-b6896beb7f42","year":2019},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"cited_paper":"/paper/1907.02167","citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:26bb642c30b580cc30cbab6afc9c2784ff5244103036bfc77c0883ba9059216a","observation_id":"0a463b01-cab0-4f02-b932-766622c2ec91","resolution":{"observed_at":"2026-05-25T09:20:34.501861Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/1907.02167/citation-record","integrity":"/paper/1907.02167/integrity","json":"/paper/1907.02167/citation-record.json","paper":"/paper/1907.02167"},"outbound":[{"citation":{"cited_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"cited_work":{"arxiv_id":"1907.02167","doi":null,"metadata_source":"pith","pith_arxiv_id":"1907.02167","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","venue":"cs.AR","work_id":"c43fe8e8-df0e-4885-a50f-b6896beb7f42","year":2019},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"cited_paper":"/paper/1907.02167","citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:26bb642c30b580cc30cbab6afc9c2784ff5244103036bfc77c0883ba9059216a","observation_id":"0a463b01-cab0-4f02-b932-766622c2ec91","resolution":{"observed_at":"2026-05-25T09:20:34.501861Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":null,"venue":null,"work_id":"9fd4d486-4b2e-4da7-9f81-4bd3bab6db64","year":null},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:45aa6587469d23c834ade62a10983ecaf0ec3274c5b68a65e90444088803cd55","observation_id":"68599f44-8b33-4018-ada8-c5221608e16d","resolution":{"observed_at":"2026-05-25T09:20:35.141624Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"We extend USIMM to include a DRAM cache","venue":null,"work_id":"2988dc36-fc20-4ee5-9a4c-4157d39a8a86","year":2006},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:bbf5463e5c3da5d66aa66abf2a07a627bbdc942487f0d244519edbba61c20ee9","observation_id":"9034dd72-7443-4c48-bf6f-d6fb53453051","resolution":{"observed_at":"2026-05-25T09:20:35.231444Z","resolver_source":"raw_fallback","status":"malformed_identifier"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"4.1 RRIP as a Bypassing Policy We design a version of RRIP for limited-associativity caches, called RRIP: Age-On-Bypass (RRIP-AOB)","venue":null,"work_id":"d19b571a-0384-40ed-b6fb-33d5fbf70733","year":null},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:d1a5e2927e2b12fc60f920c762b5c8c0e52c7329509c51e19930f95585c509cc","observation_id":"d551be1d-24b5-4501-8a3f-564bb6bd27ac","resolution":{"observed_at":"2026-05-25T09:20:35.149869Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"We can avoid state update costs if we have an effective way to infer an RRPV state","venue":null,"work_id":"ba9cba13-f9ce-4f0c-aaa3-686a9484b876","year":null},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:b18ffc6564aadf951e7b0c8da462a256ee1363263bd765f6baf027fa3fd022f6","observation_id":"4093348f-3306-4850-9032-ace9cd6cc2a2","resolution":{"observed_at":"2026-05-25T09:20:35.120431Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":null,"venue":null,"work_id":"b3bc5880-ca83-4595-9984-33a415a25132","year":null},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:20401811792c20991afadcffa180643820dfc73efcbf74aa94ab6d0465489579","observation_id":"780d2b36-3090-4506-bb8d-fab72604c55b","resolution":{"observed_at":"2026-05-25T09:20:35.116687Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":null,"venue":null,"work_id":"aa65cde4-59e7-4624-9203-10f49d49ca34","year":null},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:d11c6c4d1cff129353d464042021cb1d961191d0ca7d86e2e894b6b501bdd76d","observation_id":"8b24813d-2472-4997-8fc4-7b8a2885c97d","resolution":{"observed_at":"2026-05-25T09:20:35.177184Z","resolver_source":"raw_fallback","status":"parse_uncertain"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"De- motions only occur on first miss to a region","venue":null,"work_id":"91c8fe33-f3d9-4520-ad8e-44efd5cd5e3a","year":null},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:0f5bdf3bd75622fd7f4a225fc6873adda9a4e85ccb036901e59fc9cccf029aaa","observation_id":"f0c4ced4-dbe6-4b3f-806f-90fdfefe8699","resolution":{"observed_at":"2026-05-25T09:20:35.090235Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":null,"venue":null,"work_id":"ebe26b7e-b114-4e1c-8b01-03b2a6966adb","year":null},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:b1023e9a1bc104c0da4979c20916a817cd360050d70dfb4c0d3f2fb0b482cd3f","observation_id":"bfdebd9b-e391-4a0c-bfe8-9d721c680437","resolution":{"observed_at":"2026-05-25T09:20:35.130641Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"A recent proposal ACCORD [34] tries to make DRAM caches set-associative, to improve hit rate albeit at an expense of bandwidth and latency [35,36,37]","venue":null,"work_id":"1012958e-45a7-40c9-98a2-6f96588d7f09","year":null},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:8d257a33623ffbf87751f94dbef78e5854e3dfd968acbe3c41978e69d5cf5182","observation_id":"4c517fb6-a730-498a-9da9-abb8a676c956","resolution":{"observed_at":"2026-05-25T09:20:35.156665Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Due to space constraints, we limit these results to ETR implemented on RRIP-AOB","venue":null,"work_id":"e1b78d12-6949-4de6-8cd9-26d3a338ddab","year":null},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:954dec4bc09f46077476719f2e8c07f0b64269fc43d7a85ec7b72792eeeedfc9","observation_id":"dad0d778-a670-43aa-acc5-629307499bb9","resolution":{"observed_at":"2026-05-25T09:20:35.160211Z","resolver_source":"raw_fallback","status":"malformed_identifier"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Probabilistic replacement policies [17, 43], become probabilistic bypass [8] in Figure 5","venue":null,"work_id":"cb1d6926-ef35-4e71-8f81-32d550dd1197","year":null},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:ca08a448c99a752f4aef2f406b91b30e08ba4980dbead871aa19c7028fd856f0","observation_id":"10d4d54d-aa7b-4071-b82a-35654657deea","resolution":{"observed_at":"2026-05-25T09:20:35.220644Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"We would like to use the most effective replacement policies to improve DRAM cache hit-rate","venue":null,"work_id":"732c3a7b-99db-43ff-8376-9d952282e6e7","year":null},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:d88d49f7f4c83383cd5f997ee1ec356e74376ec43033ff756ae176139e22d04c","observation_id":"d5e7435e-0310-4361-bcd2-1f0b9d3f97ad","resolution":{"observed_at":"2026-05-25T09:20:35.211821Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"High bandwidth memory (hbm) dram","venue":null,"work_id":"aba5e159-9256-491a-b38b-846dd0e0dfd8","year":2013},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:6d08338b29ebbcd122e8174dca8535f380b6f7fefd7defa35755f35a29d04f55","observation_id":"9096a150-c77f-4634-95c0-a46397f8cff3","resolution":{"observed_at":"2026-05-25T09:20:35.082546Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":null,"venue":null,"work_id":"10c4a853-2937-4083-a8b8-5c8fcc559027","year":2013},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:fb005b1c5b90fd96bc2ab29fe81f38fad82798076b75db89cad5aa0b85c44ded","observation_id":"2256056b-91f9-496a-82a1-c690ad4ea919","resolution":{"observed_at":"2026-05-25T09:20:35.123554Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"A revolutionary breakthrough in memory technology","venue":null,"work_id":"b7065bc0-31cf-4690-b415-7c96b8105b0e","year":2015},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:7189d5aefcb8453066a923d9a8291cff405faddd51b8cbbbe5420297b5bfe83d","observation_id":"92baab0d-e950-4a8a-9b4a-db88418ac1e0","resolution":{"observed_at":"2026-05-25T09:20:35.242121Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Knights landing: Second-generation intel xeon phi product","venue":null,"work_id":"9d1dda0d-63a4-4840-9be5-9dd95d890410","year":2016},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:0614c7122c79355e51b35ff589b70c6a072dc9304c61325e146f04921fa947c8","observation_id":"532d76ed-c784-476a-bc42-50974b816b66","resolution":{"observed_at":"2026-05-25T09:20:35.249501Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Fundamental latency trade-off in architecting dram caches: Outperforming impractical sram-tags with a simple and practical design","venue":null,"work_id":"c49e839e-4eee-42c5-bb9a-d74804e04b18","year":2012},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:d1a7f53caef28f7e9cd2b482d4eae454d41168eb4707979baea2ef89b1d002d1","observation_id":"b98834c7-c363-41fc-ad35-e8fe2afa2c5b","resolution":{"observed_at":"2026-05-25T09:20:35.235062Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Bear: Techniques for mitigating bandwidth bloat in gigascale dram caches","venue":null,"work_id":"6595613e-e38b-4b61-9076-a08079ad99d0","year":2015},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:271454843070447afc5065bbc35eeb2c90ff4b694a2d70d95475a87a2beda210","observation_id":"2753fb9e-0f88-41fc-8cb7-65388af7edc8","resolution":{"observed_at":"2026-05-25T09:20:35.164154Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Counter-based cache replacement and bypassing algorithms","venue":null,"work_id":"9b6f97da-50b6-4559-9e38-cf3a88cea511","year":2008},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:d01f029e54e3d629b2bc74b3bd138afbd80541c526a2dd9cdd5734da90d62115","observation_id":"b4c1424a-ef2b-46db-8f66-3d0e9e9f2c3d","resolution":{"observed_at":"2026-05-25T09:20:35.069799Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"A dueling segmented lru replacement algorithm with adaptive bypassing","venue":null,"work_id":"c87c8007-7d9d-459c-932b-ab0c21513800","year":2010},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:6cf421ba554df1c67f4a9781d81c33419362646354b79fcc60791bb273e49a1c","observation_id":"95ad2431-fd95-4aae-9a42-fea98b0e005c","resolution":{"observed_at":"2026-05-25T09:20:35.073791Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"High performance cache replacement using re-reference interval prediction (rrip)","venue":null,"work_id":"4f9b0296-f68a-4f15-9cd6-06bcbc3268c1","year":2010},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:d07fb6691b30570dcbf67cc5e10713af12a39b15b980bedd0f672e470ba246ea","observation_id":"fcd45db2-476b-4c57-bf11-87d1950b77cd","resolution":{"observed_at":"2026-05-25T09:20:35.077531Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Ship: Signature-based hit predictor for high performance caching","venue":null,"work_id":"4c507a8c-66b8-46ba-8651-eaa1b1d89a38","year":2011},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:2d8c60f359c1c318da083033cd77322b760f1dfe48c79a4da073d803e8f3f5d2","observation_id":"a79445da-2e7b-44e1-afa0-1bb3f66ffdb7","resolution":{"observed_at":"2026-05-25T09:20:35.028784Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Ship++: Enhancing signature-based hit predictor for improved cache performance","venue":null,"work_id":"c1082f03-767d-4d55-b3c9-fbbbfc7ae905","year":2017},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:698595da28acc33d0b4c2d42263c6250916ef9e53a04c92d32709e5548b18651","observation_id":"b88acbe4-f713-4aec-8e37-389a5b7456b1","resolution":{"observed_at":"2026-05-25T09:20:35.054269Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Back to the future: Leveraging belady’s algorithm for improved cache replacement","venue":null,"work_id":"4c916c40-d92e-4cc5-8c47-d44543c94b76","year":2016},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:7736cf6f95aa4e443daaed07c2f4c9258ac37e9de8be29e6209838f6a922b6bc","observation_id":"dd51df33-2f63-4803-938e-523d79823aef","resolution":{"observed_at":"2026-05-25T09:20:35.043418Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Multiperspective reuse prediction","venue":null,"work_id":"5a8ceb04-b303-49e6-b305-96c28de690e5","year":2017},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:3c0e1bb4dbfcd6d935c84ec7e7a7b517e6b1c15e1fb4589b377be03bb07412bb","observation_id":"8ec02e1e-6a1a-40f6-b142-08df579663e4","resolution":{"observed_at":"2026-05-25T09:20:35.094019Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Unison cache: A scalable and effective die-stacked dram cache","venue":null,"work_id":"9ec6d001-c12d-40c6-9af1-827081c89d34","year":2014},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:675c899f36fc54eecb154053ff772f7c1b23f91a7f1074013f2540376065f1e8","observation_id":"e3f8bac9-443a-4f31-9ab6-6d6a77452d46","resolution":{"observed_at":"2026-05-25T09:20:35.007247Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Resilient die-stacked dram caches","venue":null,"work_id":"a00629e8-b7f0-4a3c-90a1-3b3dc5c9d24b","year":2013},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:308f1a1f1fdc4e4b0ef2fdba838bc2c9ce08bae0301283e5ce6d137306148660","observation_id":"dbce78c3-e52a-49f4-8f97-cf286fed3f40","resolution":{"observed_at":"2026-05-25T09:20:35.145782Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Modified lru policies for improving second-level cache behavior","venue":null,"work_id":"719190bd-c8cd-46ac-a14e-04613ff8998d","year":2000},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:0f65e2794a671b6f4766a60f6bebf3398244d3009849135015894116924438ec","observation_id":"1a819ff5-22d7-4b32-bcb1-4cc4e2d47a37","resolution":{"observed_at":"2026-05-25T09:20:35.245881Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Adaptive insertion policies for high performance caching","venue":null,"work_id":"17d2e907-d3da-4eda-9bc1-3f79035b5557","year":2007},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:416317dbba10307fbd3812be6a125199715d5b8a8d4d3ab1a39ef628a22a63f4","observation_id":"3731a49a-9e9b-4850-9c39-ae485b327ebe","resolution":{"observed_at":"2026-05-25T09:20:35.184305Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Data cache management using frequency-based replacement","venue":null,"work_id":"77bb6e21-bb57-49b6-82e8-8463e0d764e3","year":1990},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:370de7311a2eddb3cc28fecb1da0b45ada950b73a16c8d87cda9a63149ae4a67","observation_id":"2d4d5f19-0565-4edb-98d9-7b9b08b6114a","resolution":{"observed_at":"2026-05-25T09:20:35.039530Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"The v-way cache: demand-based associativity via global replacement","venue":null,"work_id":"4825f53a-589b-4a18-b621-7b0fb171696e","year":2005},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:89b4de752f2bbf0eaf66d504b0f345a191121647b6b8b770bd9c21e5ff08809b","observation_id":"f5467d89-10ea-4aed-97b5-8b3161b78fd9","resolution":{"observed_at":"2026-05-25T09:20:35.134436Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Usimm: the utah simulated memory module","venue":null,"work_id":"8b7e8283-2a6c-4e6e-9fd8-b00ee5ae37c7","year":2012},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:fc77f82f8d32f144d42f35503af370119258ea112f4c7f0ba9ce4dcf5a51770f","observation_id":"f860c4c9-a0f7-45fb-98ac-d36771b211a0","resolution":{"observed_at":"2026-05-25T09:20:35.138212Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Knights landing: Second-generation intel xeon phi product","venue":null,"work_id":"bfa2adea-789a-4525-af1f-0cd5debf3adb","year":2016},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:d4d5f9fae5aedb58be0e1efcb19def7b53ad843187f4702f2c22c21c3024645b","observation_id":"b8e39d1a-6a2f-4140-929d-d5d65d5099e7","resolution":{"observed_at":"2026-05-25T09:20:35.061123Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1903.05714","last_updated":"2019-08-09T18:41:24Z","snapshot_observed_at":"2026-07-06T07:39:08.614339Z","submitted_at":"2019-03-13T21:14:40Z","title":"Basic Performance Measurements of the Intel Optane DC Persistent Memory Module","version":3},"cited_work":{"arxiv_id":"1903.05714","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"1903.05714","snapshot_observed_at":"2026-07-04T05:59:38.178927Z","title":"Basic performance measurements of the intel optane DC persistent memory module","venue":null,"work_id":"aa8eb87b-8286-459d-9fb6-9d8de52e6552","year":2019},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"cited_paper":"/paper/1903.05714","citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:a86966214b601c3882ced82bb4e358d5ac41a11c81f5b7cc8393fabc36122fe1","observation_id":"40f917a3-219e-4ccc-bf95-9665d21014e6","resolution":{"observed_at":"2026-05-25T09:20:34.507873Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Fact sheet: New intel architectures and technologies target expanded market opportunities","venue":null,"work_id":"80944f17-1439-4c94-8e38-8edf4dd7d5ae","year":2018},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:26b1ee997fdd63f23b54c99c641c89f34715e0018fdc38d9206e3ed44c07abfc","observation_id":"5ce9475b-5e2f-4fdf-b8c7-e3e6bfa90dd6","resolution":{"observed_at":"2026-05-25T09:20:35.238753Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Phase change memory: From devices to systems","venue":null,"work_id":"838e6645-27c4-4342-ad8b-3d225174e2f4","year":2011},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:748821fee1f6c24c4be056000ec5d2256c403d3fb25df2d5e65ca44d91fe1c61","observation_id":"ca73930e-a9a6-4b9d-a2cb-ecb5cee273bb","resolution":{"observed_at":"2026-05-25T09:20:35.204450Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"A 20nm 1.8v 8gb pram with 40mb/s program bandwidth","venue":null,"work_id":"9887df61-43df-450f-bd40-1d00559b90c5","year":2012},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:4273933c2e97b5daf7b0d4329a1ae535a0f258ab277bf277658da2feb12093dd","observation_id":"d431a492-e968-4714-a279-b39852eb69fc","resolution":{"observed_at":"2026-05-25T09:20:34.997446Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Phase change memory","venue":null,"work_id":"6bdb9a0b-20d3-4364-a9ca-7dada6fcbd77","year":2010},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:085d7934a3212bfb6c2d9b81b2e44191f20efed23246d44ad8036582ed524f7e","observation_id":"5582f578-e195-4bdc-8b6b-2d9cde9869e4","resolution":{"observed_at":"2026-05-25T09:20:35.167820Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Architecting phase change memory as a scalable dram alternative","venue":null,"work_id":"6336a57f-0b21-4176-ba61-d6f4abca1abb","year":2009},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:4e8cad772e2d3cfbaa85b553a93c89ed6f04655bb973364debf6d70805bc204f","observation_id":"ee312c19-550c-4b9c-bea9-d916a9e0ffab","resolution":{"observed_at":"2026-05-25T09:20:35.050769Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Pinpointing representative portions of large intel itanium programs with dynamic instrumentation","venue":null,"work_id":"c20df377-f81b-44f0-9ab7-d3ee0caa8b3c","year":2004},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:14f0c372911e99913a061f3d18b701afacb236143cd9d1d79c017a1cd30937e9","observation_id":"286a17e9-34c6-4ae3-b190-01d736155b47","resolution":{"observed_at":"2026-05-25T09:20:35.181037Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Spec cpu2006 benchmark descriptions","venue":null,"work_id":"3e28d79b-cf87-4100-897c-590f053a4dfc","year":2006},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:a4e62c0d30ee127b8fd519782a37859b701cac4d176bf4646ed9e7b6f5e54507","observation_id":"38e0b54c-9914-47c8-a495-becbfeecbf90","resolution":{"observed_at":"2026-05-25T09:20:35.109607Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1508.03619","last_updated":"2017-05-16T19:14:14Z","snapshot_observed_at":"2026-07-06T04:26:46.231818Z","submitted_at":"2015-08-14T19:46:48Z","title":"The GAP Benchmark Suite","version":4},"cited_work":{"arxiv_id":"1508.03619","doi":"10.48550/arxiv.1508.03619arxiv:1508.03619","metadata_source":"pith","pith_arxiv_id":"1508.03619","snapshot_observed_at":"2026-07-10T06:15:00.866473Z","title":"The GAP Benchmark Suite","venue":"cs.DC","work_id":"d1a9ec25-5504-46a7-842c-f099ee53f73f","year":2015},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"cited_paper":"/paper/1508.03619","citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:184cee1d18fc6657b999598d12370950c8ed9292c56d849eef6aa0327f57e996","observation_id":"63ba1e76-f57f-4ade-b6c8-7b1c8499f9df","resolution":{"observed_at":"2026-05-25T09:20:34.513215Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Spatial memory streaming","venue":null,"work_id":"4c3a2de4-b3fc-466c-a040-c8f6afafb9db","year":2006},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:ad185742c03a4403ba2fbe81d808343523a3b04192251dcd088d7fed0482118c","observation_id":"f3c0566f-9dbb-4637-8977-acc49205630e","resolution":{"observed_at":"2026-05-25T09:20:35.000521Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Sampling dead block prediction for last-level caches","venue":null,"work_id":"b69c96a5-c135-4f0b-a161-03ac6a5cb1ef","year":2010},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":45,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:1c1f2615a1b5af71d9f9399049096af5f81b1320e0571947ff6178b635798f4d","observation_id":"869575ad-ecd1-48bc-81ec-54a8d71bbdbd","resolution":{"observed_at":"2026-05-25T09:20:35.012336Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Rethinking belady’s algorithm to accommodate prefetching","venue":null,"work_id":"a900b93b-2636-499b-8e37-405af7732c45","year":2018},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":46,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:352759aac4bc4fb9e148389228db1984230db14cc8cd8e79971ff0a8e11fc1f9","observation_id":"84b93ca0-4507-4a40-8e4e-cc8264196234","resolution":{"observed_at":"2026-05-25T09:20:34.989541Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Accord: Enabling associativity for gigascale dram caches by coordinating way-install and way-prediction","venue":null,"work_id":"10ccb413-de4c-4496-9467-bec902207236","year":2018},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":47,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:e969556f800f38092c575670836bc61cffc2d64aaac46d1de489c721408c9e4a","observation_id":"a1c0392c-367d-423c-a621-b8ae16e17d55","resolution":{"observed_at":"2026-05-25T09:20:34.993971Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Agarwal and S","venue":null,"work_id":"a561aadd-14b1-4a0a-99ff-df666ce2c001","year":1993},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":48,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:c07599f44752e04fba49529ab9784977c76d39e0944ca4e18c69643ae687d7c3","observation_id":"9f13b66d-6f66-40cf-a324-c9bdcb692e3e","resolution":{"observed_at":"2026-05-25T09:20:35.003611Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Predictive sequential associative cache","venue":null,"work_id":"ad628a41-1865-438a-8493-2b37aaa7c8c8","year":1996},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":49,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:e4e9ad5a82aa6c47d628bdeeb114cee54a2e28ae885aeabc30533f41dce91429","observation_id":"c3b765f2-6cf6-44af-8b1f-baf28134c167","resolution":{"observed_at":"2026-05-25T09:20:35.228164Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Selective cache ways: On-demand cache resource allocation","venue":null,"work_id":"4cac5829-02b9-47b2-a6f7-e8bf1c29d699","year":1999},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":50,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:197740cabc8d2f4d669e91433a2c1d3c4356017c23c71765100887900aec0047","observation_id":"04deb398-0fc5-447e-ae4a-83e5040c7c09","resolution":{"observed_at":"2026-05-25T09:20:35.032195Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"System and circuit level power modeling of energy-efficient 12 3d-stacked wide i/o drams","venue":null,"work_id":"772c199f-8ada-4b9c-aa02-8da286bc4c48","year":2013},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":51,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:524a7a171cf2443c547435203ab134c013b67852d4d7493a927c03e00535cffa","observation_id":"0172fded-bc02-48b7-a6e6-f93628c71fdb","resolution":{"observed_at":"2026-05-25T09:20:35.127102Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Rethinking dram power modes for energy proportionality","venue":null,"work_id":"d0f92513-6304-4850-b800-5a1b5d64ff93","year":2012},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":52,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:a4eaa5b843475db19d8a9b64d211c2ae999bfa6bc80d014f8a2a7c80c5b902af","observation_id":"3f3d3766-663f-4b3c-8181-c73b4fe9c096","resolution":{"observed_at":"2026-05-25T09:20:35.197201Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Enabling efficient and scalable hybrid memories using fine-granularity dram cache management","venue":null,"work_id":"f893d181-b358-4fd9-a7a7-83c182a9d2fa","year":2012},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":53,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:edbe51a8426895785181be1b81f2210b501ae76340fa467f868a79a737882942","observation_id":"371282cc-3201-4556-b59b-19a8e8c8a750","resolution":{"observed_at":"2026-05-25T09:20:35.106138Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Insertion and promotion for tree-based pseudolru last-level caches","venue":null,"work_id":"e89044e0-610c-49a7-ad69-92dc74495492","year":2013},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":54,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:e876b4521c9674607db4df38d91c32f207650bba03e727fbd3d9040f0036ecb3","observation_id":"2a1ff033-7c65-4a1b-85b1-fcd52194c7a0","resolution":{"observed_at":"2026-05-25T09:20:35.207879Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Eelru: simple and effective adaptive page replacement","venue":null,"work_id":"1a2ed527-facc-4cae-b28a-82c0bf1f6ffb","year":1999},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":55,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:212244c26e54284d767d5855bf79b77efb66439a74ae4ecb4b419080f408cc0e","observation_id":"41d3ca0d-24ee-46f8-8cc4-3e6acc813e74","resolution":{"observed_at":"2026-05-25T09:20:35.193718Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Adaptive insertion policies for managing shared caches","venue":null,"work_id":"9125a25c-9911-4f42-aca0-87e414fd377b","year":2008},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":56,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:50b921e885f73e54a049110634d35740f20fc027235cfad82a20bfd2c73387d0","observation_id":"89080561-9261-46f1-a16b-4f09a17ac6e5","resolution":{"observed_at":"2026-05-25T09:20:35.024584Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"A fully associative software-managed cache design","venue":null,"work_id":"91d40bb7-96f9-4c23-a8ef-f136ee8a39c4","year":2000},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":57,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:61673210e2e574888472eab2c9245a34bd247231e4048188e45f583ab0566b47","observation_id":"b4a9e86a-220d-438c-8ddb-1383890b1100","resolution":{"observed_at":"2026-05-25T09:20:35.020607Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"The lru-k page replacement algorithm for database disk buffering","venue":null,"work_id":"18bcec0a-c463-4595-805d-6a0425174cc6","year":1993},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":58,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:3f0726dd3f3f7fe1ec0bf01b35fecac99aa8ab5a5b05f5cc9be9ccb39d1a0858","observation_id":"07c9ff9a-cd83-4a54-a3df-dff110428fa6","resolution":{"observed_at":"2026-05-25T09:20:35.047278Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Lrfu: A spectrum of policies that subsumes the least recently used and least frequently used policies","venue":null,"work_id":"93c1cd97-d4b1-42a8-823b-56bf665a831e","year":2001},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":59,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:5efb33190f2c742e7c7fbc16a10fd8003f9c3bd16cec1c1e1dd5a304c2c49171","observation_id":"ff90b8f3-4379-4399-ad35-29ea2968aace","resolution":{"observed_at":"2026-05-25T09:20:35.057600Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Improving cache management policies using dynamic reuse distances","venue":null,"work_id":"4699d72e-acb6-4398-9fc6-cb98461ad992","year":2012},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":60,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:701ae6b20b1ac5869734463cf9d8b939ce068fbdd4423e1fb147881131184331","observation_id":"e53dae57-a393-4aa1-924d-f382e2aac7d5","resolution":{"observed_at":"2026-05-25T09:20:35.016363Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Cache replacement based on reuse-distance prediction","venue":null,"work_id":"fd52562c-c7d3-4e67-b69c-1da09d7fc869","year":2007},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":61,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:106a1c8e29c6842d2fad2014de1bf6fb94ca1d6477d15ea410f2477aba4d4ef8","observation_id":"78a20048-7d82-4503-acc7-dbc183f55296","resolution":{"observed_at":"2026-05-25T09:20:35.098291Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"245–250, IEEE","venue":null,"work_id":"9e81b9ab-92a3-4ba4-9796-270d538aaf5f","year":2007},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":62,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:f54bb01a1241db16fe7827f6d0f14ed0c24cf63cdcdd8be1c438a021d0a770d1","observation_id":"6b337f35-fabc-46e8-9cbe-554dd669ceeb","resolution":{"observed_at":"2026-05-25T09:20:35.086435Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Candy: Enabling coherent dram caches for multi-node systems","venue":null,"work_id":"24b3be5a-9ba4-4b33-ad4c-508f1ff34d1a","year":2016},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":63,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:06c7e93f554c04fe74116d938a513967a9d974daef5171940319303bf5f7df90","observation_id":"53fe1371-b560-46d7-861a-c9249df12b57","resolution":{"observed_at":"2026-05-25T09:20:35.201030Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Efficiently enabling conventional block sizes for very large die-stacked dram caches","venue":null,"work_id":"fbcc4553-11be-4870-abe0-b0babea26a5d","year":2011},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":64,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:6b1b9098567d3f509e8134196874e83dc72410d87f68944463f25cd21770faf0","observation_id":"8df46999-9796-499c-8290-8c0acf9fc566","resolution":{"observed_at":"2026-05-25T09:20:35.188421Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Atcache: reducing dram cache latency via a small sram tag cache","venue":null,"work_id":"c1d28dfe-60de-425f-89e1-ad363bd2f8d1","year":2014},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":65,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:887261862492987146d60b328dbd119b737b3053204f80884e30286fac03c4f9","observation_id":"9a584967-7121-4185-b20c-6b7ae191454a","resolution":{"observed_at":"2026-05-25T09:20:35.113510Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Building a low latency, highly associative dram cache with the buffered way predictor","venue":null,"work_id":"1479c7da-13ec-4e02-963c-da8f50c13142","year":2016},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":66,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:1ab121ba5ec7c90146c38a0f00e9faaa7fbb14fd49a95f468cc987927096d210","observation_id":"9929a961-0105-42ca-81d1-9a149e264b42","resolution":{"observed_at":"2026-05-25T09:20:35.036029Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Die-stacked dram caches for servers: Hit ratio, latency, or bandwidth? have it all with footprint cache","venue":null,"work_id":"6057dd21-965e-4a9c-a1f3-a5e4d3582e94","year":2013},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":67,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:5f01f0a72ab2ee06cec4121c18c598f2fe5ee3be4d7f65b4456580d368c97cfc","observation_id":"cfcc6eb5-a8cd-43d9-9224-33b282dac817","resolution":{"observed_at":"2026-05-25T09:20:35.224622Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"A fully associative, tagless dram cache","venue":null,"work_id":"0fe11b94-cd33-4b59-bd9b-b51db2c2700c","year":2015},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":68,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:a5f3cb4d2a76512171b58c05941ea7af680fccc5ebfa65dc86def607a409c66b","observation_id":"3b15dc4e-fdca-4a5b-8675-4144d3d8e586","resolution":{"observed_at":"2026-05-25T09:20:35.065076Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Efficient footprint caching for tagless dram caches","venue":null,"work_id":"924a1ec8-99e2-4418-a1dd-51809e74e33c","year":2016},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":69,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:1b3ae2a6f7cd64f06efb49f42a458dad483731547e7f3d58796fecf3a33adf01","observation_id":"c48b0502-a321-4492-9468-0a13334ff3ab","resolution":{"observed_at":"2026-05-25T09:20:35.102086Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Challenges in heterogeneous die-stacked and off-chip memory systems","venue":null,"work_id":"5e87d815-d1be-49e6-acb3-4ce3796a96ec","year":2012},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":70,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:daa834d2d61ecb61831ee71f8c29206ab06da60b9bd165cc09081954eb0ddb70","observation_id":"76793232-9798-4bf3-8695-9aa4c563857a","resolution":{"observed_at":"2026-05-25T09:20:35.215258Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Banshee: Bandwidth-efficient dram caching via software/hardware cooperation","venue":null,"work_id":"b452b84b-2c0e-4398-aaee-3de30dd662de","year":2017},"citing_paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches","version":1},"reference_index":71,"source":"pdf_text","source_observed_at":"2026-05-25T09:19:39.479960Z"},"links":{"citing_paper":"/paper/1907.02167"},"observation_digest":"sha256:e88b9b52a9f27895bb69e7dafbc283c3bd2bf71fd77d55918ed21917b9302e6d","observation_id":"f8088547-8561-48f1-8505-8986d95f785f","resolution":{"observed_at":"2026-05-25T09:20:35.173654Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"1907.02167","last_updated":"2019-07-04T00:28:51Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-02T09:24:55.112488Z","submitted_at":"2019-07-04T00:28:51Z","title":"To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches"},"reference_resolution":{"displayed":71,"state_counts":{"malformed_identifier":2,"metadata_mismatch":0,"parse_uncertain":1,"unresolved":4,"verified_exact":3,"verified_fuzzy":61},"total_outbound_references":71},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"thesis":"As of 12 August 2026, this Paper Citation Record lists 71 of 71 outbound references and 1 inbound Pith citation observation for arXiv:1907.02167."}