{"as_of":"2026-08-07T11:53:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:636313d7d9dbde8a8df25d79c01a03af5aaecb86868578f75089dd91877d7fac","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":6,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":6,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-07T06:34:17.273281+00:00","state":"measured"},{"denominator":6,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":6,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-01T22:14:38.679513Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"arxiv_reference","source_observed_at":"2026-05-25T02:20:14.417068Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"1907.10701","last_updated":"2019-10-22T06:07:55Z","snapshot_observed_at":"2026-08-03T06:07:39.760319Z","submitted_at":"2019-07-24T20:18:28Z","title":"Benchmarking TPU, GPU, and CPU Platforms for Deep Learning","version":4},"cited_work":{"arxiv_id":"1907.10701","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"1907.10701","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"arXiv preprint arXiv:1907.10701 (2019)","venue":null,"work_id":"167e28ec-4477-48f0-ba9f-313dd7b16d5c","year":2019},"citing_paper":{"arxiv_id":"2409.07609","last_updated":"2026-07-21T12:24:53Z","snapshot_observed_at":"2026-08-04T02:09:32.375092Z","submitted_at":"2024-09-11T20:43:59Z","title":"Survival of the Cheapest: Cost-Aware Hardware Adaptation for Adversarial Robustness","version":2},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-05-23T21:14:38.949892Z"},"links":{"cited_paper":"/paper/1907.10701","citing_paper":"/paper/2409.07609"},"observation_digest":"sha256:1e1896ce63c53c767e0c61419aa2686fbf9ccc6ee3a1c24d0fd4278adec1ddd7","observation_id":"d3a05b38-cbbb-4da1-aef0-b2f90d4d2bd7","resolution":{"observed_at":"2026-05-23T21:15:49.399879Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1907.10701","last_updated":"2019-10-22T06:07:55Z","snapshot_observed_at":"2026-08-03T06:07:39.760319Z","submitted_at":"2019-07-24T20:18:28Z","title":"Benchmarking TPU, GPU, and CPU Platforms for Deep Learning","version":4},"cited_work":{"arxiv_id":"1907.10701","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"1907.10701","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"arXiv preprint arXiv:1907.10701 (2019)","venue":null,"work_id":"167e28ec-4477-48f0-ba9f-313dd7b16d5c","year":2019},"citing_paper":{"arxiv_id":"2503.08223","last_updated":"2026-04-09T15:28:27Z","snapshot_observed_at":"2026-07-06T20:50:33.513259Z","submitted_at":"2025-03-11T09:41:29Z","title":"Will LLMs Scaling Hit the Wall? Breaking Barriers via Distributed Resources on Massive Edge Devices","version":3},"reference_index":134,"source":"pdf_text","source_observed_at":"2026-05-23T01:03:26.037233Z"},"links":{"cited_paper":"/paper/1907.10701","citing_paper":"/paper/2503.08223"},"observation_digest":"sha256:b8b84d6ea96ae3e0448217c651b148a47e82db1734c54eb50ffb0695694927b9","observation_id":"ae994997-f93c-458d-884c-7d7ba2c9ebb5","resolution":{"observed_at":"2026-05-23T01:05:16.335725Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1907.10701","last_updated":"2019-10-22T06:07:55Z","snapshot_observed_at":"2026-08-03T06:07:39.760319Z","submitted_at":"2019-07-24T20:18:28Z","title":"Benchmarking TPU, GPU, and CPU Platforms for Deep Learning","version":4},"cited_work":{"arxiv_id":"1907.10701","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"1907.10701","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"arXiv preprint arXiv:1907.10701 (2019)","venue":null,"work_id":"167e28ec-4477-48f0-ba9f-313dd7b16d5c","year":2019},"citing_paper":{"arxiv_id":"2604.07523","last_updated":"2026-04-10T21:02:31Z","snapshot_observed_at":"2026-07-06T22:55:46.307881Z","submitted_at":"2026-04-08T18:54:07Z","title":"FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration","version":2},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-05-10T17:23:57.512298Z"},"links":{"cited_paper":"/paper/1907.10701","citing_paper":"/paper/2604.07523"},"observation_digest":"sha256:2c5855e9f7556b1135101e052b26d3a89fcf8f5f7e85d414e463e2587c6492bd","observation_id":"1d800c68-cbaa-46d4-a8d1-43f86d82617c","resolution":{"observed_at":"2026-05-11T06:55:58.951271Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1907.10701","last_updated":"2019-10-22T06:07:55Z","snapshot_observed_at":"2026-08-03T06:07:39.760319Z","submitted_at":"2019-07-24T20:18:28Z","title":"Benchmarking TPU, GPU, and CPU Platforms for Deep Learning","version":4},"cited_work":{"arxiv_id":"1907.10701","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"1907.10701","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"arXiv preprint arXiv:1907.10701 (2019)","venue":null,"work_id":"167e28ec-4477-48f0-ba9f-313dd7b16d5c","year":2019},"citing_paper":{"arxiv_id":"2604.17476","last_updated":"2026-04-19T15:07:01Z","snapshot_observed_at":"2026-07-06T23:04:32.734175Z","submitted_at":"2026-04-19T15:07:01Z","title":"Privatar: Scalable Privacy-preserving Multi-user VR via Secure Offloading","version":1},"reference_index":79,"source":"arxiv_source","source_observed_at":"2026-05-10T06:20:18.479234Z"},"links":{"cited_paper":"/paper/1907.10701","citing_paper":"/paper/2604.17476"},"observation_digest":"sha256:4bb525362db3c13315f112c37fd37a0db7b60c43a26fcefabfc54642d65f24a1","observation_id":"f2e2a97c-6a0a-41fe-a829-bae645295e92","resolution":{"observed_at":"2026-05-10T06:21:26.886374Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1907.10701","last_updated":"2019-10-22T06:07:55Z","snapshot_observed_at":"2026-08-03T06:07:39.760319Z","submitted_at":"2019-07-24T20:18:28Z","title":"Benchmarking TPU, GPU, and CPU Platforms for Deep Learning","version":4},"cited_work":{"arxiv_id":"1907.10701","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"1907.10701","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"arXiv preprint arXiv:1907.10701 (2019)","venue":null,"work_id":"167e28ec-4477-48f0-ba9f-313dd7b16d5c","year":2019},"citing_paper":{"arxiv_id":"2605.23833","last_updated":"2026-05-22T16:41:23Z","snapshot_observed_at":"2026-07-06T02:11:23.670680Z","submitted_at":"2026-05-22T16:41:23Z","title":"DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration","version":1},"reference_index":52,"source":"pdf_text","source_observed_at":"2026-05-25T02:17:02.764223Z"},"links":{"cited_paper":"/paper/1907.10701","citing_paper":"/paper/2605.23833"},"observation_digest":"sha256:7ed34da26f0ea148af27f71bc32579cde6333243bba904a89819e6261bd8f92c","observation_id":"5f51bbeb-b4f1-49e4-baa2-91e36b6643ea","resolution":{"observed_at":"2026-05-25T02:20:14.420124Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1907.10701","last_updated":"2019-10-22T06:07:55Z","snapshot_observed_at":"2026-08-03T06:07:39.760319Z","submitted_at":"2019-07-24T20:18:28Z","title":"Benchmarking TPU, GPU, and CPU Platforms for Deep Learning","version":4},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1907.10701","snapshot_observed_at":"2026-08-01T22:14:38.679513Z","title":null,"venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2607.15846","last_updated":"2026-07-17T11:04:21Z","snapshot_observed_at":"2026-08-07T09:07:30.834173Z","submitted_at":"2026-07-17T11:04:21Z","title":"DSTAR: Accelerating Diffusion Transformers via Spatial and Temporal Redundancy Reduction","version":1},"reference_index":56,"source":"pdf_text","source_observed_at":"2026-08-01T22:14:38.679513Z"},"links":{"cited_paper":"/paper/1907.10701","citing_paper":"/paper/2607.15846"},"observation_digest":"sha256:74cd0c15fe72cf4b6cb16cc96869313deb97a9e41d678744bbd625a9b2f8f340","observation_id":"42033959-676d-4e5b-a287-59547366981c","resolution":{"observed_at":"2026-08-01T22:14:38.679513Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"links":{"evidence":"/evidence","html":"/paper/1907.10701/citation-record","integrity":"/paper/1907.10701/integrity","json":"/paper/1907.10701/citation-record.json","paper":"/paper/1907.10701"},"outbound":[],"paper":{"arxiv_id":"1907.10701","last_updated":"2019-10-22T06:07:55Z","latest_version":4,"primary_category":"cs.LG","snapshot_observed_at":"2026-08-03T06:07:39.760319Z","submitted_at":"2019-07-24T20:18:28Z","title":"Benchmarking TPU, GPU, and CPU Platforms for Deep Learning"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"thesis":"As of 7 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 6 inbound Pith citation observations for arXiv:1907.10701."}