{"as_of":"2026-08-16T05:39:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:62f308c1d0670b283cd7c8ffce404c4ae2a339a16305579aaa6fd479800494a7","coverage":[{"denominator":4,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":4,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-14T13:49:03.141611Z","state":"measured"},{"denominator":4,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":4,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-15T06:32:42.880941+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/1908.04236/citation-record","integrity":"/paper/1908.04236/integrity","json":"/paper/1908.04236/citation-record.json","paper":"/paper/1908.04236"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T13:49:03.213745Z","title":"Code Transformations to Improve Memory Parallelism","venue":null,"work_id":"8fe2b03e-5a1d-4497-90d8-a282a6873b85","year":1999},"citing_paper":{"arxiv_id":"1908.04236","last_updated":"2019-08-12T16:45:41Z","snapshot_observed_at":"2026-08-14T13:45:07.542107Z","submitted_at":"2019-08-12T16:45:41Z","title":"MLP Aware Scheduling Techniques in Multithreaded Processors","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-14T13:49:03.129538Z"},"links":{"citing_paper":"/paper/1908.04236"},"observation_digest":"sha256:2a5435dae5bfefc14384d88c26ae69d9c99202e6cd34860d8663c2cba0b9836e","observation_id":"cf535ada-d5ee-433b-a00a-91d368706771","resolution":{"observed_at":"2026-08-14T13:49:03.218506Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T13:49:03.200151Z","title":"MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor","venue":null,"work_id":"aa90c5fc-d04a-46e6-a4b6-db7017b4cebd","year":2008},"citing_paper":{"arxiv_id":"1908.04236","last_updated":"2019-08-12T16:45:41Z","snapshot_observed_at":"2026-08-14T13:45:07.542107Z","submitted_at":"2019-08-12T16:45:41Z","title":"MLP Aware Scheduling Techniques in Multithreaded Processors","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-14T13:49:03.134091Z"},"links":{"citing_paper":"/paper/1908.04236"},"observation_digest":"sha256:104c9f3e968ed8406fd0c79ebb76cd6f1e122e3283313636b0ee4d554ec2269c","observation_id":"b71e4ab7-e685-4f8d-98d8-2c8dd3b425eb","resolution":{"observed_at":"2026-08-14T13:49:03.204764Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T13:49:03.187460Z","title":"Co-optimizing memory-level parallelism and cache-level parallelism","venue":null,"work_id":"e3f0eeed-8310-43ef-88ed-09d53313eef5","year":2019},"citing_paper":{"arxiv_id":"1908.04236","last_updated":"2019-08-12T16:45:41Z","snapshot_observed_at":"2026-08-14T13:45:07.542107Z","submitted_at":"2019-08-12T16:45:41Z","title":"MLP Aware Scheduling Techniques in Multithreaded Processors","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-14T13:49:03.138014Z"},"links":{"citing_paper":"/paper/1908.04236"},"observation_digest":"sha256:dc211086d3198e21151a5a3285bf19de19287326bab95089abc8b5a3f6af7ce4","observation_id":"29c98ec7-1dcc-498f-8bd1-e6ebefd248e6","resolution":{"observed_at":"2026-08-14T13:49:03.191863Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T13:49:03.172561Z","title":"Parallelism-Aware Batch Scheduling: Enhancing Both Performance and Fairness of Shared DRAM Systems","venue":null,"work_id":"827b42a9-22cd-4db6-87e4-8074521c467e","year":2008},"citing_paper":{"arxiv_id":"1908.04236","last_updated":"2019-08-12T16:45:41Z","snapshot_observed_at":"2026-08-14T13:45:07.542107Z","submitted_at":"2019-08-12T16:45:41Z","title":"MLP Aware Scheduling Techniques in Multithreaded Processors","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-14T13:49:03.141611Z"},"links":{"citing_paper":"/paper/1908.04236"},"observation_digest":"sha256:be7ae9c85de92743d7a2155c050a31363eccf39038e65ccddef4668214b36c9f","observation_id":"cfa4d321-9ec0-4ce9-8cf7-bc7f55bf73d0","resolution":{"observed_at":"2026-08-14T13:49:03.178736Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"1908.04236","last_updated":"2019-08-12T16:45:41Z","latest_version":1,"primary_category":"cs.PF","snapshot_observed_at":"2026-08-14T13:45:07.542107Z","submitted_at":"2019-08-12T16:45:41Z","title":"MLP Aware Scheduling Techniques in Multithreaded Processors"},"reference_resolution":{"displayed":4,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":4},"total_outbound_references":4},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"thesis":"As of 16 August 2026, this Paper Citation Record lists 4 of 4 outbound references and 0 inbound Pith citation observations for arXiv:1908.04236."}