{"as_of":"2026-08-16T16:23:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:2837789582cee3ab2110da4ed559d6d9dcebef7313a2a9750fef40274c0fa1e7","coverage":[{"denominator":19,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":19,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-14T12:45:07.247253Z","state":"measured"},{"denominator":19,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":19,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-16T06:30:59.297886+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/1908.06532/citation-record","integrity":"/paper/1908.06532/integrity","json":"/paper/1908.06532/citation-record.json","paper":"/paper/1908.06532"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:08.055295Z","title":"A scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors (DYNAPs),","venue":null,"work_id":"974e78d4-571d-4ec3-8d17-17804b06b05a","year":2017},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.081485Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:fc4810869eb49643cccdb7298c22a8016f2e78e8e188b4b032dbad7eedbfa25f","observation_id":"7180cb94-2a9d-45ae-825a-2fe20420b760","resolution":{"observed_at":"2026-08-14T12:45:08.077922Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:08.018244Z","title":"Hierarchical address event routing for reconﬁgurable large-scale neuromorphic sys- tems,","venue":null,"work_id":"1a15bc59-98a7-4e16-a234-c8fa2f8c5495","year":2016},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.088620Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:e16255da61e85b30d8d9ea4e6b92c06f6e076df12ecb39d40d8745bca72add59","observation_id":"d1e3c0db-9d80-427d-a8bf-300ce9ca9f5c","resolution":{"observed_at":"2026-08-14T12:45:08.031189Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.980771Z","title":"A million spiking-neuron integrated circuit with a scalable communication network and interface,","venue":null,"work_id":"ed72a788-0256-4017-98de-94cd6c9b4f9f","year":2014},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.098846Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:131827e7b278cef800c02bc30f615172db57f3cc963e3aef7c0edeb6de91c5f8","observation_id":"efdccd91-4476-4963-8865-57ae43e2bf53","resolution":{"observed_at":"2026-08-14T12:45:07.993882Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.105924Z","title":"The SpiNNaker project,","venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.105924Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:e6c61bc3b7ef7e7facb8d17e0ba2ed9dd2d38df8a68e5869d919735b2398ad70","observation_id":"e114afed-8558-4874-84e8-c4bae52e9669","resolution":{"observed_at":"2026-08-14T12:45:07.105924Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.121070Z","title":"Neurogrid: A mixed-analog-digital multichip system for large-scale neural simulations,","venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.121070Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:8788490bd0271ee71f2b27bdeb654b3d81e66702bd8c3f9e8d0b108c51b01aa8","observation_id":"512f30c6-9d42-4d5d-9c94-5584280ee087","resolution":{"observed_at":"2026-08-14T12:45:07.121070Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.891226Z","title":null,"venue":null,"work_id":"bfdfe6e9-7dee-43a6-ad3a-84e397d46613","year":2014},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.137228Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:e1ef9abc8ac770ef3271dfebd61b66217054abcfb74feb7ddc215957f5cbe3d2","observation_id":"373884b4-0fbc-4d19-8f47-dfb13832e410","resolution":{"observed_at":"2026-08-14T12:45:07.918027Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.863119Z","title":"Neuromorphic sensory systems,","venue":null,"work_id":"136f567c-7af4-42c4-baad-f714c152bf6b","year":2010},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.143593Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:ef416fea162c427a634c61f7afad34e55f64aa178e1b530aab751e94363a9b80","observation_id":"2a2d9890-2462-4dc6-85de-69baf13df00e","resolution":{"observed_at":"2026-08-14T12:45:07.869280Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.829534Z","title":"A re-conﬁgurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128k synapses,","venue":null,"work_id":"cdf13d1d-a4f9-4c75-ac7f-aebb2c077c27","year":2015},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.150151Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:6e590eb8e13fe2939d2da16bc1beded23e040c744843f8d519b644907a650aaa","observation_id":"7dbc76a9-2262-4c28-a60c-ce3a0ef15181","resolution":{"observed_at":"2026-08-14T12:45:07.838816Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.788444Z","title":"Robust working memory in an asynchronously spiking neural network realized in neuromorphic VLSI,","venue":null,"work_id":"1858fceb-68cb-4159-8075-ab5af327cc4b","year":2012},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.155092Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:2a95f2160457994a1ee580db07518a7411a57b02afbaa6631e041e193fb3ff07","observation_id":"39a9b228-d0a3-4238-b555-bbf0e3b6d53c","resolution":{"observed_at":"2026-08-14T12:45:07.800873Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.752325Z","title":"Synthesizing cognition in neuromorphic electronic systems,","venue":null,"work_id":"d84cd6e7-42e0-4f0d-954b-41bfd69297bc","year":2013},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.165191Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:f5d09fdf0d95b0c63e8cecd4ae72cf0a5b659dfb93902495b5188d7b42d63eea","observation_id":"9c033f48-6e25-408a-b0a2-6f13715a088c","resolution":{"observed_at":"2026-08-14T12:45:07.762570Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.695370Z","title":"CAVIAR: A 45k neuron, 5M synapse, 12G connects/s aer hardware sensory– processing– learning–actuating system for high-speed visual object recognition and tracking,","venue":null,"work_id":"f71cd8f8-6467-49ed-9da4-7dbc42f48f3b","year":2009},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.170449Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:ca29015dc086fde497a00ec72f6a143c5f8a276e1470936205d2c434d1e6d348","observation_id":"aa45e33b-bcb6-41dd-aee7-05efb4f52850","resolution":{"observed_at":"2026-08-14T12:45:07.717175Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.623020Z","title":"A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity,","venue":null,"work_id":"6a23872d-b1f8-44b3-8d8c-ca30e705d13e","year":2007},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.175881Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:e50e7253c3193a4e0ebcb6e557de44796abdf8dbe2335dfe8c2bdb77f08778fe","observation_id":"c736e621-99a4-4c74-a18e-c52a688c8f29","resolution":{"observed_at":"2026-08-14T12:45:07.634859Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.568119Z","title":"A 240×180 130 dB 3µs latency global shutter spatiotemporal vision sensor,","venue":null,"work_id":"b426c33c-56a6-4854-b384-3c33fffe1025","year":2014},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.184410Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:0d0d6fb027fbe6390d2a868794f0c7a57e4472a5a597e0188d204ba079775d71","observation_id":"a4af1519-df03-4cef-a61e-62ff95bbbc93","resolution":{"observed_at":"2026-08-14T12:45:07.590368Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.527985Z","title":"A 1.5ns OFF/ON switching-time voltage-mode LVDS driver/receiver pair for asynchronous AER bit-serial chip grid links with up to 40 times event-rate dependent power savings,","venue":null,"work_id":"67e5faa1-6c4a-4bd0-8861-bf7cfcd2fa89","year":2013},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.197431Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:432857888314974e3eaf61fbbbb75babd292f6c4fd51085b59888ff3ec61b72c","observation_id":"79901ed0-721f-40d0-b949-0cd4f3aa3b44","resolution":{"observed_at":"2026-08-14T12:45:07.538602Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.487987Z","title":"Eﬃcient self-timing with level-encoded 2-phase dual-rail (LEDR),","venue":null,"work_id":"8a242595-e32d-4047-a543-7a136aeaad37","year":1991},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.204202Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:4eb49e76f2346d9a036a7029c9173883f1974e708bd507e8a72f9391911ae8c2","observation_id":"1a602d80-f617-4c26-9ebd-594a4b200f3b","resolution":{"observed_at":"2026-08-14T12:45:07.503701Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.456134Z","title":"A high-speed clockless serial link transceiver,","venue":null,"work_id":"2e9388d1-1e3f-4579-9263-b59d0e1abccc","year":2003},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.215005Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:d0dd72a4af11b0e7417a40c327d65ffc2d928e10885c1fdb727ba2a4199eb041","observation_id":"96db5c95-51e2-4749-a7bb-634a311124de","resolution":{"observed_at":"2026-08-14T12:45:07.466620Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.418088Z","title":"A0.35 µm sub-ns wake-up time ON-OFF switchable LVDS driver- receiver chip I/O pad pair for rate-dependent power saving in AER bit-serial links,","venue":null,"work_id":"1fa34a79-b5b8-430a-ae00-13072f831375","year":2012},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.225225Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:c4477473a5e8b6580f1262ef846dd5c206d5536cb8c2b36845845185dfb43594","observation_id":"4a268d3e-19d0-4f4a-93be-2fed0e7c306d","resolution":{"observed_at":"2026-08-14T12:45:07.428111Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.374311Z","title":"LVDS interface for aer links with burst mode operation capability,","venue":null,"work_id":"f7e80041-dcb4-4cb3-985f-905a89ad2cb5","year":2008},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.233605Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:432b5a5b6c73838bc04ad61016bf43bda972c0dac67be7c4e733fc2218096529","observation_id":"46f6e3cd-39d7-48f1-a209-abc5aa4ee0ea","resolution":{"observed_at":"2026-08-14T12:45:07.386096Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-14T12:45:07.319321Z","title":"Memory and information processing in neuromorphic systems,","venue":null,"work_id":"b268d1e2-0d50-45d4-9b19-ed7778b9d988","year":2015},"citing_paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-14T12:45:07.247253Z"},"links":{"citing_paper":"/paper/1908.06532"},"observation_digest":"sha256:59b956e66e5605f0c5c58e2d963683875f3a3cd81287423280174e89b9f3fe07","observation_id":"bc89bed6-32bf-4fb2-8f07-7124a709606c","resolution":{"observed_at":"2026-08-14T12:45:07.338154Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"1908.06532","last_updated":"2019-08-18T23:01:04Z","latest_version":1,"primary_category":"cs.ET","snapshot_observed_at":"2026-08-16T14:25:29.314332Z","submitted_at":"2019-08-18T23:01:04Z","title":"A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems"},"reference_resolution":{"displayed":19,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":3,"verified_exact":0,"verified_fuzzy":16},"total_outbound_references":19},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"thesis":"As of 16 August 2026, this Paper Citation Record lists 19 of 19 outbound references and 0 inbound Pith citation observations for arXiv:1908.06532."}