{"as_of":"2026-08-20T05:52:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:f86039a37c71466b2f9bb040121f4faa40b003f58bfaf5ea51dad4755f5013b2","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":1,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-19T06:32:44.657259+00:00","state":"measured"},{"denominator":1,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":1,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-06T16:09:32.835500Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"pith","source_observed_at":"2026-08-06T16:09:36.338727Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2104.09252","last_updated":"2021-04-19T12:50:27Z","snapshot_observed_at":"2026-08-19T16:50:27.895176Z","submitted_at":"2021-04-19T12:50:27Z","title":"Learning on Hardware: A Tutorial on Neural Network Accelerators and Co-Processors","version":1},"cited_work":{"arxiv_id":"2104.09252","doi":null,"metadata_source":"pith","pith_arxiv_id":"2104.09252","snapshot_observed_at":"2026-08-06T16:09:36.338727Z","title":"Learning on Hardware: A Tutorial on Neural Network Accelerators and Co-Processors","venue":"cs.LG","work_id":"bf624148-40c5-45c8-86e9-e60b17367af7","year":2021},"citing_paper":{"arxiv_id":"2507.17771","last_updated":"2025-07-19T00:57:54Z","snapshot_observed_at":"2026-08-19T19:35:35.767632Z","submitted_at":"2025-07-19T00:57:54Z","title":"Flexible Vector Integration in Embedded RISC-V SoCs for End to End CNN Inference Acceleration","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-06T16:09:32.835500Z"},"links":{"cited_paper":"/paper/2104.09252","citing_paper":"/paper/2507.17771"},"observation_digest":"sha256:420673e2cd3def2aa54b62fc9381adb31479d728be8858ebff1a022d9acbf76f","observation_id":"042e30b7-8e5b-4829-a855-a8c46f6f883a","resolution":{"observed_at":"2026-08-06T16:09:36.343794Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/2104.09252/citation-record","integrity":"/paper/2104.09252/integrity","json":"/paper/2104.09252/citation-record.json","paper":"/paper/2104.09252"},"outbound":[],"paper":{"arxiv_id":"2104.09252","last_updated":"2021-04-19T12:50:27Z","latest_version":1,"primary_category":"cs.LG","snapshot_observed_at":"2026-08-19T16:50:27.895176Z","submitted_at":"2021-04-19T12:50:27Z","title":"Learning on Hardware: A Tutorial on Neural Network Accelerators and Co-Processors"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"thesis":"As of 20 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 1 inbound Pith citation observation for arXiv:2104.09252."}