{"as_of":"2026-08-08T16:40:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:4167c5a2aa83fc0169b1cf64cd20fedc1c58c9c90813d2f06cbdfe92842de4a2","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":1,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-08T06:32:00.761636+00:00","state":"measured"},{"denominator":1,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":1,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-06T17:31:26.015343Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"pith","source_observed_at":"2026-08-06T17:31:29.679302Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2110.08221","last_updated":"2021-11-10T15:57:28Z","snapshot_observed_at":"2026-08-08T03:51:56.551015Z","submitted_at":"2021-10-15T17:32:59Z","title":"Metrics and Design of an Instruction Roofline Model for AMD GPUs","version":2},"cited_work":{"arxiv_id":"2110.08221","doi":null,"metadata_source":"pith","pith_arxiv_id":"2110.08221","snapshot_observed_at":"2026-08-06T17:31:29.679302Z","title":"Metrics and Design of an Instruction Roofline Model for AMD GPUs","venue":"cs.DC","work_id":"c95d93a7-3dc8-4121-a960-872078d366da","year":2021},"citing_paper":{"arxiv_id":"2507.10789","last_updated":"2025-07-21T19:31:37Z","snapshot_observed_at":"2026-08-07T11:15:14.923695Z","submitted_at":"2025-07-14T20:38:09Z","title":"Dissecting the NVIDIA Blackwell Architecture with Microbenchmarks","version":2},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-06T17:31:26.015343Z"},"links":{"cited_paper":"/paper/2110.08221","citing_paper":"/paper/2507.10789"},"observation_digest":"sha256:47ccd5a28624f1537a9fb8c9f8ce466b14bf0198bc416e06cce4b26969b5b875","observation_id":"636fafbd-fd30-4670-99b9-bb859b2c5c59","resolution":{"observed_at":"2026-08-06T17:31:29.730486Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/2110.08221/citation-record","integrity":"/paper/2110.08221/integrity","json":"/paper/2110.08221/citation-record.json","paper":"/paper/2110.08221"},"outbound":[],"paper":{"arxiv_id":"2110.08221","last_updated":"2021-11-10T15:57:28Z","latest_version":2,"primary_category":"cs.DC","snapshot_observed_at":"2026-08-08T03:51:56.551015Z","submitted_at":"2021-10-15T17:32:59Z","title":"Metrics and Design of an Instruction Roofline Model for AMD GPUs"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"thesis":"As of 8 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 1 inbound Pith citation observation for arXiv:2110.08221."}