{"as_of":"2026-08-07T23:07:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:0f8311a16846026a369a8759261d57849aeb6e5280bbe30e2d4ba6a80764fa10","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":14,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":14,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-07T06:34:17.273281+00:00","state":"measured"},{"denominator":14,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":14,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-07T05:27:36.054040Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"arxiv_reference","source_observed_at":"2026-07-04T12:39:49.554588Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-08-07T05:27:36.054040Z","title":"Towards llm-powered verilog rtl assistant: Self-verification and self-correction,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.054040Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:532703e128750bc5a68571463ad26bd631850ebfe9c0b01feafea9b5c095fe1c","observation_id":"480b4146-1067-4756-8dac-0222d286ce71","resolution":{"observed_at":"2026-08-07T05:27:36.054040Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-08-07T00:31:00.481281Z","title":"Towards llm-powered verilog rtl assistant: Self-verification and self-correction,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.13905","last_updated":"2025-09-08T18:17:46Z","snapshot_observed_at":"2026-08-07T17:09:46.132647Z","submitted_at":"2025-06-16T18:33:25Z","title":"Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems","version":2},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-07T00:31:00.481281Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2506.13905"},"observation_digest":"sha256:ffae9bd5f528c2d6abe9d90460e210d0298a7c54cc9a8e9b5a63618a1ce90de1","observation_id":"3120106e-599f-4138-a0a5-eb93bfefb473","resolution":{"observed_at":"2026-08-07T00:31:00.481281Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-08-06T22:55:09.361068Z","title":"Towards llm-powered verilog rtl assistant: Self-verification and self-correction,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.20415","last_updated":"2025-06-25T13:31:13Z","snapshot_observed_at":"2026-08-06T22:46:10.805099Z","submitted_at":"2025-06-25T13:31:13Z","title":"SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models","version":1},"reference_index":74,"source":"pdf_text","source_observed_at":"2026-08-06T22:55:09.361068Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2506.20415"},"observation_digest":"sha256:2621d97d52825eb1a81837c109b15e83e69c94c101c666bbfbffa4b64a80b4aa","observation_id":"db456d25-33ab-4d0c-8769-8e304ccf650c","resolution":{"observed_at":"2026-08-06T22:55:09.361068Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-08-06T20:40:17.027402Z","title":"Towards llm-powered verilog rtl assistant: Self-verification and self-correction,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.02226","last_updated":"2025-07-03T01:17:44Z","snapshot_observed_at":"2026-08-06T20:31:57.968196Z","submitted_at":"2025-07-03T01:17:44Z","title":"DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-06T20:40:17.027402Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2507.02226"},"observation_digest":"sha256:f194743c14bf8f6b849eac5bfb140d230dbd53f2a32f916488affb403b469d64","observation_id":"159afa08-7ae4-4b08-8cdc-bfa3296fb328","resolution":{"observed_at":"2026-08-06T20:40:17.027402Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":"2406.00115","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-07-04T12:39:49.554588Z","title":"Available: https://arxiv.org/abs/2406.00115","venue":null,"work_id":"5689894f-4dde-4586-bae0-564eebab647a","year":2024},"citing_paper":{"arxiv_id":"2604.03245","last_updated":"2026-07-20T21:40:17Z","snapshot_observed_at":"2026-08-02T18:43:41.133826Z","submitted_at":"2026-03-06T21:41:28Z","title":"FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification","version":1},"reference_index":48,"source":"pdf_text","source_observed_at":"2026-05-15T14:31:36.233977Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2604.03245"},"observation_digest":"sha256:b031ea5fee453698e8d6f089240ccbebe5aff0f2bc65a9f8620d59749ecfd62e","observation_id":"dde3f72e-d215-4131-8db1-d9705908aed2","resolution":{"observed_at":"2026-05-15T14:35:55.934463Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-08-02T18:43:47.275015Z","title":"Towards llm-powered verilog rtl assistant: Self-verification and self-correction,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2604.03245","last_updated":"2026-07-20T21:40:17Z","snapshot_observed_at":"2026-08-02T18:43:41.133826Z","submitted_at":"2026-03-06T21:41:28Z","title":"FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification","version":2},"reference_index":45,"source":"pdf_text","source_observed_at":"2026-08-02T18:43:47.275015Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2604.03245"},"observation_digest":"sha256:5a944a36200b508c6a028bbc5155d548f8cd9fa7bd45bd58bd5fa3b70850882b","observation_id":"1b966f08-832e-4e4e-b634-47022de4a411","resolution":{"observed_at":"2026-08-02T18:43:47.275015Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":"2406.00115","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-07-04T12:39:49.554588Z","title":"Available: https://arxiv.org/abs/2406.00115","venue":null,"work_id":"5689894f-4dde-4586-bae0-564eebab647a","year":2024},"citing_paper":{"arxiv_id":"2604.21952","last_updated":"2026-04-23T05:27:39Z","snapshot_observed_at":"2026-08-02T07:47:00.163884Z","submitted_at":"2026-04-23T05:27:39Z","title":"Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Models","version":1},"reference_index":59,"source":"pdf_text","source_observed_at":"2026-05-09T23:02:07.554154Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2604.21952"},"observation_digest":"sha256:91c1ca45c0c8290628c210b134c0660285d449916293688f4b3aea20e8519174","observation_id":"1499d74d-28dc-4b41-833c-512b0909cd71","resolution":{"observed_at":"2026-05-09T23:04:17.800221Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":"2406.00115","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-07-04T12:39:49.554588Z","title":"Available: https://arxiv.org/abs/2406.00115","venue":null,"work_id":"5689894f-4dde-4586-bae0-564eebab647a","year":2024},"citing_paper":{"arxiv_id":"2604.23100","last_updated":"2026-04-25T01:46:33Z","snapshot_observed_at":"2026-08-05T22:13:27.111745Z","submitted_at":"2026-04-25T01:46:33Z","title":"From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-05-08T08:19:42.493657Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2604.23100"},"observation_digest":"sha256:3c578f80ec81c3fa07cf725680a35187da637ac5ea263653eb5e93954d4f6088","observation_id":"fa10f018-ebf0-4baa-8dc3-dec12330b3a2","resolution":{"observed_at":"2026-05-11T20:41:11.970177Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":"2406.00115","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-07-04T12:39:49.554588Z","title":"Available: https://arxiv.org/abs/2406.00115","venue":null,"work_id":"5689894f-4dde-4586-bae0-564eebab647a","year":2024},"citing_paper":{"arxiv_id":"2604.23355","last_updated":"2026-05-18T06:50:33Z","snapshot_observed_at":"2026-07-06T23:09:34.300163Z","submitted_at":"2026-04-25T15:44:48Z","title":"LEGO: An LLM Skill-Based Front-End Design Generation Platform","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-05-08T08:22:04.845485Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2604.23355"},"observation_digest":"sha256:f9a504f07eb7067035c50b019a027a2a81d5be54aae0bb4a1e0ca575662aa048","observation_id":"eef541ec-7945-40d3-94f6-9ad2792bc3ce","resolution":{"observed_at":"2026-05-11T20:41:10.289237Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":"2406.00115","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-07-04T12:39:49.554588Z","title":"Available: https://arxiv.org/abs/2406.00115","venue":null,"work_id":"5689894f-4dde-4586-bae0-564eebab647a","year":2024},"citing_paper":{"arxiv_id":"2604.23355","last_updated":"2026-05-18T06:50:33Z","snapshot_observed_at":"2026-07-06T23:09:34.300163Z","submitted_at":"2026-04-25T15:44:48Z","title":"LEGO: An LLM Skill-Based Front-End Design Generation Platform","version":2},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-05-21T09:15:26.963601Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2604.23355"},"observation_digest":"sha256:fb0697305acb595913dee9125dda61c11555cd1e9406601dbcd83434ad6a70d3","observation_id":"3e358536-4f1c-4a53-a6c4-24c87543371f","resolution":{"observed_at":"2026-05-21T09:19:56.730612Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":"2406.00115","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-07-04T12:39:49.554588Z","title":"Available: https://arxiv.org/abs/2406.00115","venue":null,"work_id":"5689894f-4dde-4586-bae0-564eebab647a","year":2024},"citing_paper":{"arxiv_id":"2606.05680","last_updated":"2026-06-04T04:02:51Z","snapshot_observed_at":"2026-08-02T16:31:21.190227Z","submitted_at":"2026-06-04T04:02:51Z","title":"CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-06-27T23:06:44.339563Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2606.05680"},"observation_digest":"sha256:3bb01062d6e4356fc57e7fe84ad01e80976340f50331c1c552d4bed2a75f8909","observation_id":"4470e7b9-4633-414e-b910-418dfb2f6064","resolution":{"observed_at":"2026-07-02T15:57:07.341010Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":"2406.00115","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-07-04T12:39:49.554588Z","title":"Available: https://arxiv.org/abs/2406.00115","venue":null,"work_id":"5689894f-4dde-4586-bae0-564eebab647a","year":2024},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-06-27T00:26:54.438203Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:e3b9ee2ff99d0f219e245f80372c73bcee7b2a95b96123c333e69cdfa73c354e","observation_id":"53fcf13a-3da7-41a3-bdfe-91bcc83f766d","resolution":{"observed_at":"2026-07-03T21:28:59.390858Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:d60c0790b87f2a7a2b69af850f913706e1e08043adf333931170390d14e6d82a","observation_id":"4489cdac-83fa-4611-b8a6-05c136d689a7","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":"2406.00115","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-07-04T12:39:49.554588Z","title":"Available: https://arxiv.org/abs/2406.00115","venue":null,"work_id":"5689894f-4dde-4586-bae0-564eebab647a","year":2024},"citing_paper":{"arxiv_id":"2606.23759","last_updated":"2026-06-22T09:15:40Z","snapshot_observed_at":"2026-08-06T09:50:16.621913Z","submitted_at":"2026-06-22T09:15:40Z","title":"VeriPilot: An LLM-Powered Verilog Debugging Framework","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-06-26T06:21:00.038218Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2606.23759"},"observation_digest":"sha256:c2ee94211792d042058c8d8f9e46ce292bb113f0d52637b8acd3b14da100e891","observation_id":"3fb142ea-2c27-4b99-ae60-6eed7f00f3c6","resolution":{"observed_at":"2026-07-04T12:39:49.556138Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/2406.00115/citation-record","integrity":"/paper/2406.00115/integrity","json":"/paper/2406.00115/citation-record.json","paper":"/paper/2406.00115"},"outbound":[],"paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","latest_version":1,"primary_category":"cs.PL","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"thesis":"As of 7 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 14 inbound Pith citation observations for arXiv:2406.00115."}