{"as_of":"2026-08-20T07:26:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:edaf75f6b4ee8a2b6ce3414aab17b61543548315b2cb256a90ec08405cc34b6a","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":1,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-20T06:33:59.587034+00:00","state":"measured"},{"denominator":1,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":1,"source":"paper_references, paper_reference_links","source_observed_at":"2026-07-12T00:33:59.659330Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":1,"source":"pith","source_observed_at":"2026-08-05T02:28:24.338817Z","state":"measured"}],"external_citation_measurements":[{"count":6,"observed_at":"2026-08-05T02:28:24.338817Z","source":"pith"}],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2407.10977","last_updated":"2024-06-06T01:59:59Z","snapshot_observed_at":"2026-08-16T13:45:42.778310Z","submitted_at":"2024-06-06T01:59:59Z","title":"CIRCUITSYNTH: Leveraging Large Language Models for Circuit Topology Synthesis","version":1},"cited_work":{"arxiv_id":"2407.10977","doi":"10.1109/lad62341.2024.10691716","metadata_source":"pith","pith_arxiv_id":"2407.10977","snapshot_observed_at":"2026-08-05T02:49:54.815029Z","title":"CIRCUITSYNTH: Leveraging Large Language Models for Circuit Topology Synthesis","venue":"cs.LG","work_id":"309d9571-b03a-42ed-9d83-6639feb6e90b","year":2024},"citing_paper":{"arxiv_id":"2607.03701","last_updated":"2026-07-04T04:37:57Z","snapshot_observed_at":"2026-08-16T22:27:56.189581Z","submitted_at":"2026-07-04T04:37:57Z","title":"SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-07-12T00:33:59.659330Z"},"links":{"cited_paper":"/paper/2407.10977","citing_paper":"/paper/2607.03701"},"observation_digest":"sha256:d7742c9a93bb443636b703b719a3eeda111de8f8542db31d7ecc7b3eb9c8a401","observation_id":"e08c49cb-d0f3-42dc-bad4-7e1afc8ea08c","resolution":{"observed_at":"2026-07-12T00:38:26.374638Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-07-12T21:19:22.695747+00:00","source":"crossref_status_cache"},{"observed_at":"2026-07-12T21:19:22.695747+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/2407.10977/citation-record","integrity":"/paper/2407.10977/integrity","json":"/paper/2407.10977/citation-record.json","paper":"/paper/2407.10977"},"outbound":[],"paper":{"arxiv_id":"2407.10977","last_updated":"2024-06-06T01:59:59Z","latest_version":1,"primary_category":"cs.LG","snapshot_observed_at":"2026-08-16T13:45:42.778310Z","submitted_at":"2024-06-06T01:59:59Z","title":"CIRCUITSYNTH: Leveraging Large Language Models for Circuit Topology Synthesis"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"thesis":"As of 20 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 1 inbound Pith citation observation for arXiv:2407.10977."}