{"as_of":"2026-08-07T15:32:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:39bccd697ea52bd60595181b3a73301c67ae8545afc97b7a037f0368e47f9d8c","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":6,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":6,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-07T06:34:17.273281+00:00","state":"measured"},{"denominator":6,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":6,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-07T14:11:57.333888Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"arxiv_reference","source_observed_at":"2026-05-19T14:42:37.300033Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2409.11414","last_updated":"2024-09-04T09:59:37Z","snapshot_observed_at":"2026-08-03T17:47:44.483939Z","submitted_at":"2024-09-04T09:59:37Z","title":"RTLRewriter: Methodologies for Large Models aided RTL Code Optimization","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2409.11414","snapshot_observed_at":"2026-08-07T14:11:57.333888Z","title":"Rtlrewriter: Methodologies for large models aided rtl code optimization,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2505.19734","last_updated":"2025-05-26T09:20:07Z","snapshot_observed_at":"2026-08-07T14:05:10.339781Z","submitted_at":"2025-05-26T09:20:07Z","title":"ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-07T14:11:57.333888Z"},"links":{"cited_paper":"/paper/2409.11414","citing_paper":"/paper/2505.19734"},"observation_digest":"sha256:cc34e22efd4d53f71c701bf7afdd6ac772d162f813f5c0cee9948ee7963ea2cd","observation_id":"07a7521a-01d5-4ff9-8b2f-b3d3512c4ad5","resolution":{"observed_at":"2026-08-07T14:11:57.333888Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2409.11414","last_updated":"2024-09-04T09:59:37Z","snapshot_observed_at":"2026-08-03T17:47:44.483939Z","submitted_at":"2024-09-04T09:59:37Z","title":"RTLRewriter: Methodologies for Large Models aided RTL Code Optimization","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2409.11414","snapshot_observed_at":"2026-08-07T05:43:46.257689Z","title":"Rtlrewriter: Methodologies for large models aided rtl code optimization,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.07239","last_updated":"2025-06-29T01:51:01Z","snapshot_observed_at":"2026-08-07T05:36:00.643486Z","submitted_at":"2025-06-08T17:53:22Z","title":"VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code","version":2},"reference_index":53,"source":"pdf_text","source_observed_at":"2026-08-07T05:43:46.257689Z"},"links":{"cited_paper":"/paper/2409.11414","citing_paper":"/paper/2506.07239"},"observation_digest":"sha256:c7b5914aeccd605c30c8f45e6d844963d5851d48123cb8120cb389ad14bd9b1d","observation_id":"8db082dd-76ef-4d61-a987-ff36c8bf4fee","resolution":{"observed_at":"2026-08-07T05:43:46.257689Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2409.11414","last_updated":"2024-09-04T09:59:37Z","snapshot_observed_at":"2026-08-03T17:47:44.483939Z","submitted_at":"2024-09-04T09:59:37Z","title":"RTLRewriter: Methodologies for Large Models aided RTL Code Optimization","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2409.11414","snapshot_observed_at":"2026-08-06T20:40:17.127598Z","title":"Rtlrewriter: Methodologies for large models aided rtl code optimization,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.02226","last_updated":"2025-07-03T01:17:44Z","snapshot_observed_at":"2026-08-06T20:31:57.968196Z","submitted_at":"2025-07-03T01:17:44Z","title":"DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-06T20:40:17.127598Z"},"links":{"cited_paper":"/paper/2409.11414","citing_paper":"/paper/2507.02226"},"observation_digest":"sha256:2e66851ad1a0ec27d32c383215baaf81d5900817c0d6be39eea6bcc85c83b1cd","observation_id":"01bb3927-ee07-4999-b435-5411213d6122","resolution":{"observed_at":"2026-08-06T20:40:17.127598Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2409.11414","last_updated":"2024-09-04T09:59:37Z","snapshot_observed_at":"2026-08-03T17:47:44.483939Z","submitted_at":"2024-09-04T09:59:37Z","title":"RTLRewriter: Methodologies for Large Models aided RTL Code Optimization","version":1},"cited_work":{"arxiv_id":"2409.11414","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2409.11414","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Rtlrewriter: Methodologies for large models aided rtl code optimization","venue":null,"work_id":"d162f226-02f5-4eba-82a1-1023a059b63d","year":2024},"citing_paper":{"arxiv_id":"2507.04736","last_updated":"2026-04-10T04:48:11Z","snapshot_observed_at":"2026-08-02T06:48:38.838100Z","submitted_at":"2025-07-07T08:08:20Z","title":"ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning","version":2},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-05-19T06:48:29.015759Z"},"links":{"cited_paper":"/paper/2409.11414","citing_paper":"/paper/2507.04736"},"observation_digest":"sha256:f3def0e370f8f69b64a36903044641357793061f6c73bc708d5723084c47e5e7","observation_id":"76c0da57-48eb-4fa2-a721-8012c0959822","resolution":{"observed_at":"2026-05-19T06:52:08.261925Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2409.11414","last_updated":"2024-09-04T09:59:37Z","snapshot_observed_at":"2026-08-03T17:47:44.483939Z","submitted_at":"2024-09-04T09:59:37Z","title":"RTLRewriter: Methodologies for Large Models aided RTL Code Optimization","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2409.11414","snapshot_observed_at":"2026-08-06T15:19:53.025192Z","title":"Rtlrewriter: Methodologies for large models aided rtl code optimization,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.025192Z"},"links":{"cited_paper":"/paper/2409.11414","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:bd90c47e7279c05318e1987493a745b7c7ef0f42cb0c6597828c35344c94a4af","observation_id":"ad6362d0-0e6e-438e-baef-b3c23f524025","resolution":{"observed_at":"2026-08-06T15:19:53.025192Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2409.11414","last_updated":"2024-09-04T09:59:37Z","snapshot_observed_at":"2026-08-03T17:47:44.483939Z","submitted_at":"2024-09-04T09:59:37Z","title":"RTLRewriter: Methodologies for Large Models aided RTL Code Optimization","version":1},"cited_work":{"arxiv_id":"2409.11414","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2409.11414","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Rtlrewriter: Methodologies for large models aided rtl code optimization","venue":null,"work_id":"d162f226-02f5-4eba-82a1-1023a059b63d","year":2024},"citing_paper":{"arxiv_id":"2605.15537","last_updated":"2026-05-15T02:17:46Z","snapshot_observed_at":"2026-07-06T23:26:51.110846Z","submitted_at":"2026-05-15T02:17:46Z","title":"RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-05-19T14:42:16.802186Z"},"links":{"cited_paper":"/paper/2409.11414","citing_paper":"/paper/2605.15537"},"observation_digest":"sha256:e84ce7bdbbfe232348e88d72d2d18a18900f15a3fc959340237b83ae362ad9c8","observation_id":"9886c5b5-a343-445f-ae03-58635c91d9c5","resolution":{"observed_at":"2026-05-19T14:42:37.303419Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/2409.11414/citation-record","integrity":"/paper/2409.11414/integrity","json":"/paper/2409.11414/citation-record.json","paper":"/paper/2409.11414"},"outbound":[],"paper":{"arxiv_id":"2409.11414","last_updated":"2024-09-04T09:59:37Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-03T17:47:44.483939Z","submitted_at":"2024-09-04T09:59:37Z","title":"RTLRewriter: Methodologies for Large Models aided RTL Code Optimization"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"thesis":"As of 7 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 6 inbound Pith citation observations for arXiv:2409.11414."}