{"as_of":"2026-08-13T00:01:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:42add6d2c3af7a010f781d8e1d736bbd0e37c01627f0f0a526dac9cbfa83ff9d","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":4,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":4,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-12T06:34:41.77262+00:00","state":"measured"},{"denominator":4,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":4,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-10T23:27:32.442663Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"arxiv_reference","source_observed_at":"2026-05-21T07:04:01.685684Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2409.14317","last_updated":"2024-09-22T05:11:16Z","snapshot_observed_at":"2026-08-12T22:40:17.439814Z","submitted_at":"2024-09-22T05:11:16Z","title":"Dissecting CXL Memory Performance at Scale: Analysis, Modeling, and Optimization","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2409.14317","snapshot_observed_at":"2026-08-10T23:27:32.442663Z","title":"Available: https://arxiv.org/abs/2409.14317","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2412.20249","last_updated":"2025-02-20T13:11:03Z","snapshot_observed_at":"2026-08-12T05:10:53.563757Z","submitted_at":"2024-12-28T19:34:31Z","title":"Next-Gen Computing Systems with Compute Express Link: a Comprehensive Survey","version":2},"reference_index":2024,"source":"pdf_text","source_observed_at":"2026-08-10T23:27:32.442663Z"},"links":{"cited_paper":"/paper/2409.14317","citing_paper":"/paper/2412.20249"},"observation_digest":"sha256:989dc63e3d9e686d7051b67af05879a54f41f7a95adc87faa0084f58fedd0b83","observation_id":"b12a9351-1507-482f-a0b3-22b60181092f","resolution":{"observed_at":"2026-08-10T23:27:32.442663Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2409.14317","last_updated":"2024-09-22T05:11:16Z","snapshot_observed_at":"2026-08-12T22:40:17.439814Z","submitted_at":"2024-09-22T05:11:16Z","title":"Dissecting CXL Memory Performance at Scale: Analysis, Modeling, and Optimization","version":1},"cited_work":{"arxiv_id":"2409.14317","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2409.14317","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Available: https://arxiv.org/abs/2409.14317","venue":null,"work_id":"d0866582-8d19-4048-86ba-bc8d45a90993","year":2024},"citing_paper":{"arxiv_id":"2602.08800","last_updated":"2026-04-20T15:31:04Z","snapshot_observed_at":"2026-07-06T22:45:11.110274Z","submitted_at":"2026-02-09T15:39:56Z","title":"Equilibria: Fair Multi-Tenant CXL Memory Tiering At Scale","version":2},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-05-16T03:51:01.862220Z"},"links":{"cited_paper":"/paper/2409.14317","citing_paper":"/paper/2602.08800"},"observation_digest":"sha256:bc5c31ee42f5fc099a45cb56ded01b5760864386cea2522c71e31c89acf5189f","observation_id":"01004247-c3a5-4a88-8e66-bb06f3f7a0b0","resolution":{"observed_at":"2026-05-16T03:52:15.346871Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2409.14317","last_updated":"2024-09-22T05:11:16Z","snapshot_observed_at":"2026-08-12T22:40:17.439814Z","submitted_at":"2024-09-22T05:11:16Z","title":"Dissecting CXL Memory Performance at Scale: Analysis, Modeling, and Optimization","version":1},"cited_work":{"arxiv_id":"2409.14317","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2409.14317","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Available: https://arxiv.org/abs/2409.14317","venue":null,"work_id":"d0866582-8d19-4048-86ba-bc8d45a90993","year":2024},"citing_paper":{"arxiv_id":"2604.19494","last_updated":"2026-04-21T14:12:56Z","snapshot_observed_at":"2026-08-11T10:16:07.649383Z","submitted_at":"2026-04-21T14:12:56Z","title":"DPC: A Distributed Page Cache over CXL","version":1},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-05-10T01:26:56.818278Z"},"links":{"cited_paper":"/paper/2409.14317","citing_paper":"/paper/2604.19494"},"observation_digest":"sha256:48b0705575899c5b627af1a11d9fb050e6b943f6c4ca80d20ae0f6c340f47615","observation_id":"47652cd7-d12b-4eaf-a4a0-2d269a597dd1","resolution":{"observed_at":"2026-05-11T13:36:06.900323Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2409.14317","last_updated":"2024-09-22T05:11:16Z","snapshot_observed_at":"2026-08-12T22:40:17.439814Z","submitted_at":"2024-09-22T05:11:16Z","title":"Dissecting CXL Memory Performance at Scale: Analysis, Modeling, and Optimization","version":1},"cited_work":{"arxiv_id":"2409.14317","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2409.14317","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Available: https://arxiv.org/abs/2409.14317","venue":null,"work_id":"d0866582-8d19-4048-86ba-bc8d45a90993","year":2024},"citing_paper":{"arxiv_id":"2605.20370","last_updated":"2026-05-19T18:21:07Z","snapshot_observed_at":"2026-07-06T23:30:58.549353Z","submitted_at":"2026-05-19T18:21:07Z","title":"Clove: Object-Level CXL Memory Management in Managed Runtimes","version":1},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-05-21T07:00:45.334941Z"},"links":{"cited_paper":"/paper/2409.14317","citing_paper":"/paper/2605.20370"},"observation_digest":"sha256:1dd8728cb4593e31d53d230374ca3206cd107686dfc018483f29d658542fa47a","observation_id":"923329c2-cf16-4519-846b-ae16fa7388d5","resolution":{"observed_at":"2026-05-21T07:04:01.687367Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/2409.14317/citation-record","integrity":"/paper/2409.14317/integrity","json":"/paper/2409.14317/citation-record.json","paper":"/paper/2409.14317"},"outbound":[],"paper":{"arxiv_id":"2409.14317","last_updated":"2024-09-22T05:11:16Z","latest_version":1,"primary_category":"cs.OS","snapshot_observed_at":"2026-08-12T22:40:17.439814Z","submitted_at":"2024-09-22T05:11:16Z","title":"Dissecting CXL Memory Performance at Scale: Analysis, Modeling, and Optimization"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"thesis":"As of 13 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 4 inbound Pith citation observations for arXiv:2409.14317."}