{"as_of":"2026-08-17T15:53:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:e9509310a0fd31d2318f93b4cc71788634cfa6918d50e753c59e2118d65c95ce","coverage":[{"denominator":68,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":68,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-12T20:37:37.597763Z","state":"measured"},{"denominator":68,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":68,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-17T06:30:58.91139+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2411.09546/citation-record","integrity":"/paper/2411.09546/integrity","json":"/paper/2411.09546/citation-record.json","paper":"/paper/2411.09546"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:39.133557Z","title":"A 65 nm 1.4-6.7 TOPS/W Adaptive-SNR Sparsity-Aware CIM Core with Load Balancing Support for DL work- loads,","venue":null,"work_id":"c972a005-5e38-404b-8e54-e23280e10bee","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.232880Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:8f6bdb82fc8ed1e7991e39a8b99f493d3241bcee628b1790d7ef8ee40dcb638d","observation_id":"42c1a49d-9169-4db2-a559-f0ed545c714c","resolution":{"observed_at":"2026-08-12T20:37:39.138223Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:39.118093Z","title":"EASI-CiM: Event-driven Asynchronous Stream-based Im- age classifier with Compute-in-Memory kernels,","venue":null,"work_id":"7e780b43-6d99-4956-bf50-f62def0d2437","year":2024},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.238388Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:a4750ac06c05146e810d009b598c7c14d12204a7bc4c94d9ef8873f869739edd","observation_id":"bfeda15e-591a-4d90-9f36-47dedf7ef987","resolution":{"observed_at":"2026-08-12T20:37:39.123415Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:39.099945Z","title":"A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference,","venue":null,"work_id":"a51de93b-9aad-4d75-a736-c5202d7614b7","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.244204Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:22003fdd313448b9cd163bbade58a93fd20ced9c1ed51d8339a83833c54dda3f","observation_id":"9bbbce45-4a69-4f60-8be4-0b538d31c667","resolution":{"observed_at":"2026-08-12T20:37:39.106144Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:39.083392Z","title":"A Local Computing Cell and 6T SRAM-Based Computing-in- Memory Macro With 8-b MAC Operation for Edge AI Chips,","venue":null,"work_id":"287d92e0-49af-46d2-82b7-0d21dddbaec7","year":2021},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.251400Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:09e0f5d148cff6c98717cfec7c665059e06255d178db174c1a8163ad643551ef","observation_id":"bd6f9b5c-b8c6-4301-ac20-0e7da0705f28","resolution":{"observed_at":"2026-08-12T20:37:39.088590Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:39.067353Z","title":"A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training,","venue":null,"work_id":"7463943d-8771-4b31-baa2-f1b3b22775d7","year":2018},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.256775Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:f61a893d567bc79e710f1dca3b2e485e3a29c91135162cb5ed1b572b305c88a1","observation_id":"5aa7bfba-4f18-43ba-8707-097f153c1732","resolution":{"observed_at":"2026-08-12T20:37:39.072477Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:39.051899Z","title":"IMAC: In-memory multi-bit multiplication and ACcumulation in 6T SRAM array,","venue":null,"work_id":"020bea56-7105-47aa-a384-b57929009c6e","year":2020},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.261911Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:61ae9bb88a223da2a1c122b9a6012fae2231215cea111a80666069a3d3672aa1","observation_id":"5a3652fa-ca85-4889-b4cb-924f3a32fdc6","resolution":{"observed_at":"2026-08-12T20:37:39.057295Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:39.034026Z","title":"A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural Network,","venue":null,"work_id":"528eb128-306f-4be8-ba69-7461e43ab924","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.268086Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:c0e94bc3ea9a2dc3e15803ce6408659de3f499685027424e425e7afe12ec0b42","observation_id":"00b873eb-37a1-454a-988f-0fe6d8f41266","resolution":{"observed_at":"2026-08-12T20:37:39.039712Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:39.016960Z","title":"A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In- Memory Computing Macro,","venue":null,"work_id":"0da5dabf-82c0-4643-b1c4-822dd0d1d685","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.273142Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:75b23ed52b57516676636618c7710de5a46e72a020d3585473efb65f3479ee82","observation_id":"5b857eb5-865a-4a95-a828-f02853a17414","resolution":{"observed_at":"2026-08-12T20:37:39.022182Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.996645Z","title":"Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN- based machine learning applications,","venue":null,"work_id":"ff51db15-fd93-4437-ae84-22f813128d2d","year":2018},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.280086Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:c9cfe29f6c40e3fd36cd45af10824138d1f26f74009cc4d8def63062a597f278","observation_id":"1c749054-ace9-41a2-8e1b-fd039420a85c","resolution":{"observed_at":"2026-08-12T20:37:39.001813Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:37.285400Z","title":"A Resonant Time- Domain Compute-in-Memory (rTD-CiM) ADC-Less Architecture for MAC Operations,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.285400Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:f95e82b7978983a3b5f96a685f3f3e11267a6c05692a7e905dbdb7fed876fdd0","observation_id":"4d7cd355-080b-420a-a004-023b853136c1","resolution":{"observed_at":"2026-08-12T20:37:37.285400Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.980271Z","title":"Design and Analysis of Multibit Multiply and Accumulate (MAC) unit: An Analog In-Memory Computing Approach,","venue":null,"work_id":"0feee58f-b8a8-483d-a1ac-b7a914a322b3","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.291015Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:a1fc5e047f2e1fdbc96b96d9428a99e74226dced8b68bcb2ff299cb514558005","observation_id":"9322fc74-c569-4318-a2f7-300ab5b56a0a","resolution":{"observed_at":"2026-08-12T20:37:38.985117Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.964315Z","title":"CiMComp: An Energy Effi- cient Compute-in-Memory Based Comparator for Convolutional Neural Networks,","venue":null,"work_id":"3b0e362a-f7c7-4277-b3ac-d93be573da68","year":2024},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.296210Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:4ec50363239318631246e073691e8196f0a9166e9216009bd15025e007a2f1cc","observation_id":"18679b6f-8584-4489-9f65-7dd09968dfde","resolution":{"observed_at":"2026-08-12T20:37:38.969380Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.949365Z","title":"A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture,","venue":null,"work_id":"f7e69b39-f42e-4170-ac11-312a93bae1b6","year":2024},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.301007Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:9fd5ab54c998711a0fb5722c8160c226312144adad0bf88b716554aeb7353b13","observation_id":"8f5922e2-3b4b-4445-bb9a-f8ce5ebbb82f","resolution":{"observed_at":"2026-08-12T20:37:38.954414Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.934986Z","title":"A 129.83 TOPS/W Area Efficient Digital SOT/STT MRAM-Based Computing-In-Memory for Advanced Edge AI Chips,","venue":null,"work_id":"609740ce-8eca-49bb-aab9-00ab6d93708c","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.306683Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:803bedf3ce118e2d673a8a38221303e3d6f98805d250ff55baa41dc6825ddccf","observation_id":"557939eb-041d-496b-9e42-03332b484da7","resolution":{"observed_at":"2026-08-12T20:37:38.939756Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.919697Z","title":"An 8b-Precision 6T SRAM Computing-in- Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips,","venue":null,"work_id":"5ab2ed99-271c-4b69-9214-b4dc1784ce56","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.311998Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:71be02382a43e43bc454bb29b7e3e504e5b5d6550d010db9b9ec961e3ba53ce6","observation_id":"37baa3f9-54c0-4f6c-9cb6-08a7a1ba8b76","resolution":{"observed_at":"2026-08-12T20:37:38.924989Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.903902Z","title":"SUN: Dynamic Hybrid-Precision SRAM-Based CIM Accelerator With High Macro Utilization Using Structured Pruning Mixed-Precision Networks,","venue":null,"work_id":"ea483818-83fa-48ba-8b42-eeccb63f9e68","year":2024},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.317612Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:aefab637dbe3a856d5169ccf116930db0f486f655a42dabbfc71a13983d942bf","observation_id":"bdcd625a-6117-4318-bcdf-66e531290ad7","resolution":{"observed_at":"2026-08-12T20:37:38.908994Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.888715Z","title":"A Hierarchically Reconfigurable SRAM-Based Compute-in-Memory Macro for Edge Computing,","venue":null,"work_id":"d6dd1150-4da7-4f46-8b7e-4ab36ed85bbf","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.323097Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:551cf123eca81085350561ac5a48655c660ef4456ecd6e2739e327f7597cbee9","observation_id":"70047c52-dc36-46a5-a57e-c8d6e770a0f8","resolution":{"observed_at":"2026-08-12T20:37:38.893517Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.873665Z","title":"Impact of Aging and Process Vari- ability on SRAM-Based In-Memory Computing Architectures,","venue":null,"work_id":"77cbb2b8-8d74-49d5-b303-ca9432392ac9","year":2024},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.328867Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:5a0b3bdca61129e913e072179c1c3adc15715caac8d38c1b517d23e4b493c8b7","observation_id":"2bd54292-3cea-42ee-b21c-bbe8f36093ec","resolution":{"observed_at":"2026-08-12T20:37:38.878428Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.858399Z","title":"An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array,","venue":null,"work_id":"fdf042e7-cebe-4706-ba26-f3b1080bb81d","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.333615Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:c1af72eb3f1227d0062711ccfd03cd9800f6ae099f8814d2dc478cd6e33564f7","observation_id":"9fa85e38-b084-482c-859e-cb90bbfc5fed","resolution":{"observed_at":"2026-08-12T20:37:38.863450Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.843450Z","title":"PIC-RAM: Process- Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM,","venue":null,"work_id":"40b0c464-4648-4bd0-a545-0104caab6317","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.338767Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:e76d9671002c454da73452dab082c5793baf4f3e81de37cb0d038be8bf7d8b30","observation_id":"2e005c6e-f280-451a-8b6c-9b65eafee99c","resolution":{"observed_at":"2026-08-12T20:37:38.848494Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.826976Z","title":"En- abling Energy-Efficient In-Memory Computing With Robust Assist- Based Reconfigurable Sense Amplifier in SRAM Array,","venue":null,"work_id":"e8e236ac-c936-4185-92ff-552c87654add","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.343534Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:fdea4dc550bff44755c4a26985b33e8ac2097ae4a1e0364ff88593d935da735a","observation_id":"7de5c87d-156d-43ed-b7f3-56e5d136f4a5","resolution":{"observed_at":"2026-08-12T20:37:38.832487Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.811299Z","title":"14.2 A Compute SRAM with Bit-Serial Integer/Floating- Point Operations for Programmable In-Memory Vector Acceleration,","venue":null,"work_id":"da1e2f3a-f33f-4839-a854-885cef540135","year":2019},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.348331Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:c920b220dc39a57807bc5d3b825fe119b20b8c95d6e1bca6bbf1f29245fd125c","observation_id":"efc7b97f-a160-4817-bb9d-a97cee26bf39","resolution":{"observed_at":"2026-08-12T20:37:38.816230Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.794699Z","title":"Analysis and Optimization Strategies Toward Reliable and High-Speed 6T Compute SRAM,","venue":null,"work_id":"06503f2f-eb6e-4fec-b4d2-5eae0fa2d1a2","year":2021},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.353002Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:45ec45a2730976eaaf89e74093c57679a707f0aeff9bcfc18fec612e4f4dee08","observation_id":"8b8ea889-0ce6-4ad3-ab14-faf868e8b8e4","resolution":{"observed_at":"2026-08-12T20:37:38.800509Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.777669Z","title":"A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations,","venue":null,"work_id":"de719ac0-e256-465d-8b98-5593e3ccd9e2","year":2022},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.358102Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:87ddc0ae739ef482fb20ad53289c4434dc5dab6516a1f306dbbccdaacaf4bd55","observation_id":"4d23afc3-c9c9-47cc-b1ed-30a89dd2738f","resolution":{"observed_at":"2026-08-12T20:37:38.783549Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.760837Z","title":"A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing,","venue":null,"work_id":"7edb43a6-389a-4bbb-a508-cb4589de6f19","year":2020},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.362908Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:c57f76a1127161ef69405bb118ceaef5cab9d06d86bd393e59b3ccd4107cbcec","observation_id":"d3b4a704-409e-41c0-af59-e17c4ae4840b","resolution":{"observed_at":"2026-08-12T20:37:38.766066Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.744539Z","title":"NUTS-BSNN: A non-uniform time-step binarized spiking neural network with energy-efficient in-memory computing macro,","venue":null,"work_id":"936e4925-15f3-43cd-bd67-6a5a0eccfbd9","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.367900Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:b3189c0b9e88d081f9fd39237b04202ff88e3ea4c9371f1437dc4069d1272416","observation_id":"84a77069-6af6-4aaa-a255-0cdd692a2e77","resolution":{"observed_at":"2026-08-12T20:37:38.750020Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.722041Z","title":"CafeHD: A Charge-Domain FeFET-Based Compute-in- Memory Hyperdimensional Encoder with Hypervector Merging,","venue":null,"work_id":"647d5913-ba83-4e99-ab5b-7ccd8aaa79f1","year":2024},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.372923Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:86e2efebd8dad01c752f1a364ed5afbaad60c1e66b580dcb5aba85893c2cc578","observation_id":"a2cae7a6-3e45-4b72-bfca-1b13db88908b","resolution":{"observed_at":"2026-08-12T20:37:38.731630Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.702328Z","title":"CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming Problems,","venue":null,"work_id":"9b489ea6-27e0-4060-abdb-d2792bd63092","year":2024},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.378061Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:4593f3517d51575d8b19080e84ce062d58b8ab370e4b2852562543213dfd6afd","observation_id":"a0f8411e-3d39-4eed-b065-80aeeca85378","resolution":{"observed_at":"2026-08-12T20:37:38.709836Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.684338Z","title":"A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial Differential Equations,","venue":null,"work_id":"a2b85673-974c-41aa-94f0-c0ca30d1723a","year":2024},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.384033Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:ae26892f319734941b07be8d7b89a17e3ae2e52a7890878445e81ad1ec96d7dd","observation_id":"5eea7bb7-a1d0-4de8-bc09-5f27b3992de4","resolution":{"observed_at":"2026-08-12T20:37:38.689986Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.666023Z","title":"Efficient and lightweight in-memory computing architecture for hardware security,","venue":null,"work_id":"8d3a6d9c-02cd-41e6-81af-1fe52c46d0c3","year":2024},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.389832Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:8ef83725562e4878596f0848ce770fa3bbefeb35489dcdabed600d23f90d2f71","observation_id":"a4af1b8c-6d42-464a-83db-aa47c81f65de","resolution":{"observed_at":"2026-08-12T20:37:38.671544Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:37.396279Z","title":"Energy Efficient Data Search Design and Optimization Based on a Compact Ferroelectric FET Content Addressable Memory,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.396279Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:1796333a239e331fd1bd4aecaff1bdf3b621f8c03894ed627e3366ca37e04e94","observation_id":"75b93be4-4945-4d4d-aa40-607f705087d2","resolution":{"observed_at":"2026-08-12T20:37:37.396279Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.647198Z","title":"BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory,","venue":null,"work_id":"aa8a7c4f-369d-494e-bb51-900482139b8f","year":2016},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.401549Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:cec48edcbc39b790525787eab71466368fdd86279e07743bd525593e3bccc9e2","observation_id":"714a5225-e10e-4562-89b7-4340bc71d0fc","resolution":{"observed_at":"2026-08-12T20:37:38.653686Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.629355Z","title":"A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation,","venue":null,"work_id":"56c691b9-05f3-4d39-9670-8500ed75cbb2","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.407202Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:c46f21c47118535a1e7a994ffa017c849de53a081194c24844a09c6aa7a2379c","observation_id":"edeea3d2-a4c8-4090-92c3-b01986108e8e","resolution":{"observed_at":"2026-08-12T20:37:38.634631Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.611488Z","title":"A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory,","venue":null,"work_id":"afae30cc-2b86-470f-81d7-f71ea9cebf86","year":2016},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.412002Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:3bca5e44799c816377af5fdff46c906b7251e449ba51e90bd29db4c03c08ef64","observation_id":"e948ccd9-8f7a-448e-a843-72ffc50e3778","resolution":{"observed_at":"2026-08-12T20:37:38.617210Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.589356Z","title":"Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports,","venue":null,"work_id":"e1a3dcc8-ec5c-4493-9e22-236f3f9137e0","year":2021},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.416748Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:dfad86f9fc86aed5b70df92234c6645bbaf30b220b088b73ec183d5c99a1a3fd","observation_id":"4f1e1278-5bb2-4f53-9ccf-56117ca9c2f9","resolution":{"observed_at":"2026-08-12T20:37:38.595467Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.573143Z","title":"CAMA: Energy and Memory Efficient Automata Processing in Content-Addressable Memories,","venue":null,"work_id":"ece56269-f230-494b-8a5c-a37031d66dc5","year":2022},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.421609Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:8635feab33c9778292f9e35437e5d31f9222d70d4126c8f1fa2a2cbfe9f65feb","observation_id":"2a7319b8-bae3-4b55-92ed-7899397d3c21","resolution":{"observed_at":"2026-08-12T20:37:38.578534Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.554933Z","title":"ABC: An academic industrial-strength verification tool,","venue":null,"work_id":"1c00c37a-eae1-4df5-adde-18d13e609624","year":2010},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.426334Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:c41f32a467bcbb32d2fc83fc05a0099dd32261f685336e584cab77df2c5211ce","observation_id":"6a474189-a4fd-4ba1-83ac-01c26f00d87b","resolution":{"observed_at":"2026-08-12T20:37:38.560516Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:37.431152Z","title":"Yosys Open SYnthesis Suite,","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.431152Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:afd92dd90e057be94ca6435a947b60e2529b80c9a152bfbd376a8ac13e39a111","observation_id":"fbe3fd6a-3a15-4777-a50d-b822642e8deb","resolution":{"observed_at":"2026-08-12T20:37:37.431152Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.525220Z","title":"The EPFL combi- national benchmark suite,","venue":null,"work_id":"1f38f6e1-8e38-4850-adeb-e8cada7f3bc5","year":2015},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.437000Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:998c1bf5fbb01225a2d1f458fc72c3bb5845c93a10d8b1289762c6b0b62b5f0c","observation_id":"927e5f04-0e50-41b9-86e3-a36f359f42fe","resolution":{"observed_at":"2026-08-12T20:37:38.530878Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.508363Z","title":"A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid- Domain Structure for Advanced AI Edge Chips,","venue":null,"work_id":"1f583f7b-6c16-454b-8a36-fdc4482f2853","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.442594Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:74ca4bbdbdae0af4ed4ffe3276703af0722d6672d2d1535a3625cac9bcf4f96e","observation_id":"be1d63f6-7bf2-4e98-8c99-7ce315564803","resolution":{"observed_at":"2026-08-12T20:37:38.514001Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.488336Z","title":"DDC-PIM: Efficient Algo- rithm/Architecture Co-design for Doubling Data Capacity of SRAM- Based Processing-In-Memory,","venue":null,"work_id":"0750c52f-006a-4cc8-b322-68d7b0bab94c","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.447609Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:04d1f8d15c7ff5ae8cf7b717d13a46d03a1453e418d16f4f0aafc24b5d52f43c","observation_id":"1d440ef0-7877-4b39-a7b4-3a30c3fc9dc9","resolution":{"observed_at":"2026-08-12T20:37:38.493435Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.469492Z","title":"ADRA: Ex- tending Digital Computing-In-Memory With Asymmetric Dual-Row- Activation,","venue":null,"work_id":"13da3dd7-c8cd-4055-b4bc-7abf5f897d54","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.452490Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:2e4a621f9cd836fdd0ffb208a7cc5ba7a351e77bd340100db93dc5c417c7249c","observation_id":"ac133d2f-a606-4e1e-91f1-8852b415afe1","resolution":{"observed_at":"2026-08-12T20:37:38.476116Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.449125Z","title":"In-Memory Wallace Tree Multipliers Based on Majority Gates Within V oltage-Gated SOT-MRAM Crossbar Arrays,","venue":null,"work_id":"2949fdb3-a428-4286-a1c1-285c03a05722","year":2024},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.457372Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:282e7ce6d40b933cb8acb4c250647e71b1609feefb9cf0833a824f8208003ae8","observation_id":"81db6012-b498-4b6f-bd23-fd980c1e5886","resolution":{"observed_at":"2026-08-12T20:37:38.454692Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.431279Z","title":"X-Former: In-Memory Acceleration of Transformers,","venue":null,"work_id":"ccf6ac27-b791-42a1-9f72-ed1b61b514f6","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.462597Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:2a20f7e6a39aafebe7d74dc0bc22a0f56d08561b4315d8c0c18daca78c2e7203","observation_id":"bdb6fb2e-7319-44ef-858b-e07ab78004e7","resolution":{"observed_at":"2026-08-12T20:37:38.436427Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.410741Z","title":"ADC-Less Reprogrammable RRAM Array Architecture for In-Memory Computing,","venue":null,"work_id":"8e622d94-314e-4ad2-b306-33393431720d","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":45,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.467519Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:8406c136d4f13ed1e804bfe73e280bec6a1a9440e108cb3693fa794af96ffebf","observation_id":"782375a3-122d-4427-9bf8-b9c093a0bbec","resolution":{"observed_at":"2026-08-12T20:37:38.418300Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.389691Z","title":"HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer,","venue":null,"work_id":"289f5cc1-6dec-4ffa-859c-f9aac1afaacb","year":2024},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":46,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.472401Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:b1707d81b667017f4af7941fee05c4f05dac308d98614058b7fc2f9b3854b0fe","observation_id":"861f51be-e029-47f2-9963-023164c51a48","resolution":{"observed_at":"2026-08-12T20:37:38.395616Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.368976Z","title":"An RRAM-Based Computing-in-Memory Architecture and Its Application in Accelerating Transformer Inference,","venue":null,"work_id":"a5a52212-ead7-405b-8871-59ed466f6350","year":2024},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":47,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.478183Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:b769a823819a16c7e56af425881d79efdc0d389692ee3ebe318c68e8827e97b5","observation_id":"6d471a98-457f-4a5b-a145-f2eb6ae71ed6","resolution":{"observed_at":"2026-08-12T20:37:38.375408Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.344988Z","title":"Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System,","venue":null,"work_id":"1bb9d7df-b6d4-4ad4-8423-67abc221dc0e","year":2024},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":48,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.483742Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:76caf54d45b1ac26ddcbae8aa21cfa8fc96d4bcb31354f10a13d1b32032ed148","observation_id":"47233c68-2bd0-47d3-9e64-0bb7932e74fb","resolution":{"observed_at":"2026-08-12T20:37:38.351136Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"9517.35303","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:37.829176Z","title":"CP-SRAM: Charge-Pulsation SRAM Marco for Ultra-High Energy-Efficiency Computing-in-Memory,","venue":null,"work_id":"fc1089d4-faf1-470b-88f2-83b913704d1a","year":2022},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":49,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.489367Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:14b6def6abe8f9a434c74182043deded6cabad605ce550de69f4b78fd379e1be","observation_id":"e82b6b66-e8be-4630-9494-073ed880b915","resolution":{"observed_at":"2026-08-12T20:37:37.838790Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2110.11292","last_updated":"2021-10-21T17:19:19Z","snapshot_observed_at":"2026-08-16T17:47:33.085842Z","submitted_at":"2021-10-21T17:19:19Z","title":"OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2110.11292","snapshot_observed_at":"2026-08-12T20:37:37.495094Z","title":"OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":50,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.495094Z"},"links":{"cited_paper":"/paper/2110.11292","citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:43e2b99961ba5b4259962470c29147e8ecfbeb9a664a30783591e9d8330ebd29","observation_id":"472f5bf2-56e9-472c-b9b3-d6ada41f21c3","resolution":{"observed_at":"2026-08-12T20:37:37.495094Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.326018Z","title":"Resonant Energy Recycling SRAM Architecture,","venue":null,"work_id":"6601ce31-c3f2-4621-aecb-72b3639d4e65","year":2021},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":51,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.501251Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:f9cca94e5209800dabf6517d4bba874841dc087cef6cf5e2a4ad7fc9a6a56413","observation_id":"4488e2ec-694a-4048-bae6-fd9d451eecac","resolution":{"observed_at":"2026-08-12T20:37:38.331976Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.300830Z","title":"A Low V oltage SRAM Using Resonant Supply Boosting,","venue":null,"work_id":"76e82a42-91f9-40fe-93d5-b44cd51b87e7","year":2017},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":52,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.508942Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:2a569ecaca4ccae4ca86f314a876c09bb09640133dd996a872097d8f4698f839","observation_id":"9d7038de-1a30-46d0-b47a-9c4adf196a3c","resolution":{"observed_at":"2026-08-12T20:37:38.311365Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1007/s00034-023-02458-4","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:37.639244Z","title":"Design Automation of Series Resonance Clocking in 14-nm FinFETs,","venue":null,"work_id":"d5072659-7beb-4512-8b8d-4dca4afb8530","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":53,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.515096Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:31816d71e3a4570f1598a6f65e2906e600b9168771caf954c071bc056c454cd5","observation_id":"64992f59-d92f-4c42-a6ae-914f61f31bec","resolution":{"observed_at":"2026-08-12T20:37:37.647157Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.280861Z","title":"Power and Skew Reduction Using Resonance Energy Recycling in FinFET based Wideband Clock Networks,","venue":null,"work_id":"b97ed767-c02c-40fe-9108-88133fbf9923","year":2022},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":54,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.521410Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:cb5316ed7940c99b3b86e11c09edd2ac3b9d2e335b01a6c92f2e24cbd945dbf2","observation_id":"4b4064c3-5aca-4f01-9516-3e3a222d79a3","resolution":{"observed_at":"2026-08-12T20:37:38.287138Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.259610Z","title":"Power and skew reduction using resonant energy recycling in 14-nm FinFET clocks,","venue":null,"work_id":"a03e04ed-83fc-4698-b23c-49950c6bcab5","year":2022},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":55,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.526470Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:f5c3ab1b8359a88b2e41ffe2c4fbd94a767888f204fb705d9951c02e5e3d9bd0","observation_id":"bf1e39c3-4f5d-4992-be4e-5ff7d5a1d30b","resolution":{"observed_at":"2026-08-12T20:37:38.265658Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:37.533185Z","title":"System and methods of reducing wideband series resonant clock skew,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":56,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.533185Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:84058b4281056066eccfb11473fff880b651cb848b108234849c3e8a9c1ac25a","observation_id":"5765fcea-dc2e-4d1d-99bf-ab13b786dace","resolution":{"observed_at":"2026-08-12T20:37:37.533185Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.230230Z","title":"Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops,","venue":null,"work_id":"d5df17df-9bf2-4c80-bd8a-247945c53cc4","year":2018},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":57,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.539021Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:6c87a21bd0a01f892c89c7978d9342be59132eb344eff6a5cb5616a8bfb491a7","observation_id":"c881f1a4-9d27-432b-9787-7b552233236f","resolution":{"observed_at":"2026-08-12T20:37:38.235707Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.209507Z","title":"Resonant Compute- In-Memory (rCIM) 10T SRAM Macro for Boolean Logic,","venue":null,"work_id":"ecb2487f-0138-4868-8e81-1c142079b0ce","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":58,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.544587Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:964e028cf04dcd9100666429767d2a69c735ad25d4feba7047af669162e0180b","observation_id":"099f57d9-3c81-49ff-b767-4ee1fca9051b","resolution":{"observed_at":"2026-08-12T20:37:38.216073Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.187936Z","title":"OpenRAM: An open-source memory compiler,","venue":null,"work_id":"cfb892ce-4b7d-4471-b9b2-ec5e08ec31d7","year":2016},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":59,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.550426Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:17974835eb95994ad218d9883d9f5a3b4128142c6f654a3db6b75bca92ae7688","observation_id":"d89a2365-bdb2-4764-924a-b9db2c981af9","resolution":{"observed_at":"2026-08-12T20:37:38.194345Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"7274.18373","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:37.729280Z","title":"Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers,","venue":null,"work_id":"3fda853f-8fea-46f4-ada9-f4477f91a13f","year":null},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":60,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.555939Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:5e56d357cfeb99dfc31bddc750e4e11a317fbf489a8926aa689947f1e787003f","observation_id":"5671e66b-84f9-4d49-8cd2-773c66b42eda","resolution":{"observed_at":"2026-08-12T20:37:37.739827Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.164630Z","title":"Open- SAR: An Open Source Automated End-to-end SAR ADC Compiler,","venue":null,"work_id":"697de272-7bb9-4eee-a666-f0cbf1e057b9","year":2021},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":61,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.561799Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:7c6cb4c7363b9ff5e519e75e5647127e40a9c51ddf1976f89ab9de4532f7ab49","observation_id":"c57253c0-d5f7-41a9-8e3f-17fbfd0dc8ca","resolution":{"observed_at":"2026-08-12T20:37:38.170325Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.133599Z","title":"AutoDCIM: An Automated Digital CIM Compiler,","venue":null,"work_id":"9dcbd4a1-e0de-4d76-9ee4-2abf904745b6","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":62,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.567133Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:e70267b3b28e6c54fc49f8b2ab255856a184f0041fa70fd678223e3e58c4c247","observation_id":"5c6d7296-42aa-44d2-87f6-1f0b058d080d","resolution":{"observed_at":"2026-08-12T20:37:38.140355Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.109980Z","title":null,"venue":null,"work_id":"0f6a08be-2a6d-4d9c-b108-199676534b51","year":2004},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":63,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.573108Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:84cf48bfacf6a9d2c7d958a41a2dd460396de490994b2830087bfc0b2b2a44e8","observation_id":"1db4d232-6498-4c75-aa7f-7271c34cd5a8","resolution":{"observed_at":"2026-08-12T20:37:38.118316Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.085176Z","title":"Bit parallel 6t sram in-memory computing with reconfigurable bit-precision,","venue":null,"work_id":"0c920263-eeda-4384-aaa8-7b385ddef918","year":2020},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":64,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.578045Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:7f6e5766bc3191db99441fd784a5250fadd7a35b5f9257b9825ad05a24424d09","observation_id":"8d809285-bb35-45c2-9b1a-4bc8b2fe5b4e","resolution":{"observed_at":"2026-08-12T20:37:38.091378Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.066769Z","title":"A 40-nm cmos multifunctional computing-in-memory (cim) using single-ended disturb-free 7t 1-kb sram,","venue":null,"work_id":"8cfdb9b3-5a0c-4668-87ff-550b88f829ab","year":2021},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":65,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.582819Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:4d15f7ab3b1a4255e1ffc1f89552ac65fd8422452b64a47e88efbf08502c36cb","observation_id":"9f858953-a8c7-48f1-921d-8a6dec6cd86e","resolution":{"observed_at":"2026-08-12T20:37:38.072546Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.044222Z","title":"A fast, reliable and wide-voltage-range in-memory computing architecture,","venue":null,"work_id":"2ef7a8ea-3793-4463-a258-334fe490512e","year":2019},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":66,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.587333Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:b8fa71bf33297370334579f5f328bd4c2ea1bedaa91ff9ae4fae01ceabcb8642","observation_id":"cb7239a8-57b3-48e8-9714-35c7884af015","resolution":{"observed_at":"2026-08-12T20:37:38.050902Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.024817Z","title":"In situ storing 8t sram-cim macro for full-array boolean logic and copy operations,","venue":null,"work_id":"cb0c040d-a1c2-46a9-99a1-1c0925b879f5","year":2023},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":67,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.592513Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:e31a2e0d3e43ad7b346b0cf2cf3e578d67a33e83a63eaec5a86ea85f325f2df8","observation_id":"f6459210-c08f-411f-9d4d-c39b65d9fcd5","resolution":{"observed_at":"2026-08-12T20:37:38.030160Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T20:37:38.004420Z","title":"Design of ion-implanted mosfet’s with very small physical dimensions,","venue":null,"work_id":"a441c69d-5bba-4309-adcf-336179439c02","year":2015},"citing_paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)","version":1},"reference_index":68,"source":"pdf_text","source_observed_at":"2026-08-12T20:37:37.597763Z"},"links":{"citing_paper":"/paper/2411.09546"},"observation_digest":"sha256:956d0993da614a7c9276f468e7109f9e8aa9d1aa915263f97e228df943bba303","observation_id":"a47bbe8e-4030-4389-9389-bc1a2c52b821","resolution":{"observed_at":"2026-08-12T20:37:38.011706Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2411.09546","last_updated":"2024-11-14T16:01:05Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-14T21:11:27.783597Z","submitted_at":"2024-11-14T16:01:05Z","title":"Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)"},"reference_resolution":{"displayed":68,"state_counts":{"malformed_identifier":0,"metadata_mismatch":2,"parse_uncertain":0,"unresolved":6,"verified_exact":1,"verified_fuzzy":59},"total_outbound_references":68},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"thesis":"As of 17 August 2026, this Paper Citation Record lists 68 of 68 outbound references and 0 inbound Pith citation observations for arXiv:2411.09546."}