{"as_of":"2026-08-22T22:17:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:529113420b9a9f6cb913498955d717472cd3f3bc001ece91f61274b683072e06","coverage":[{"denominator":44,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":44,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-12T19:08:28.898802Z","state":"measured"},{"denominator":44,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":44,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-22T06:32:14.747728+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2411.11022/citation-record","integrity":"/paper/2411.11022/integrity","json":"/paper/2411.11022/citation-record.json","paper":"/paper/2411.11022"},"outbound":[{"citation":{"cited_paper":{"arxiv_id":"2001.08361","last_updated":"2020-01-23T03:59:20Z","snapshot_observed_at":"2026-08-13T17:41:53.092611Z","submitted_at":"2020-01-23T03:59:20Z","title":"Scaling Laws for Neural Language Models","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2001.08361","snapshot_observed_at":"2026-08-12T19:08:27.703143Z","title":"Scaling laws for neural language models,","venue":null,"work_id":null,"year":2001},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:27.703143Z"},"links":{"cited_paper":"/paper/2001.08361","citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:a625a85e22a6ac60597b216c90f45e0b8ccaf53c90be9beba71611f27ddc3d98","observation_id":"3fbe0bab-1741-4e0d-bb44-c16cd3c93a47","resolution":{"observed_at":"2026-08-12T19:08:27.703143Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:27.741214Z","title":"1.1 computing’s energy problem (and what we can do about it),","venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:27.741214Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:e8d6a821e2600b7084aa95a7546d0db1d3a7e58551e4c944b46e94f52eef1830","observation_id":"88d3bd41-2fd2-4097-aaf1-dbda478e3180","resolution":{"observed_at":"2026-08-12T19:08:27.741214Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:27.852083Z","title":"In-memory computing: Advances and prospects,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:27.852083Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:7a85440128645e5969cbe4690496439fd3e6c095b6990826ff5dde97f64bea7f","observation_id":"baa4bc32-53ae-44b0-bfca-790ccf2ab795","resolution":{"observed_at":"2026-08-12T19:08:27.852083Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:27.858565Z","title":"Analog or digital in-memory computing? benchmarking through quantitative modeling,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:27.858565Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:f099fed2f62313df223729bfbee5a96e0ac390044c1f21cb65a9e4a22bd63f2c","observation_id":"bb8db7df-5dd4-4b3e-b9ce-97d8ed429a14","resolution":{"observed_at":"2026-08-12T19:08:27.858565Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:27.863158Z","title":"A 64-tile 2.4- mb in-memory-computing cnn accelerator employing charge-domain compute,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:27.863158Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:b1193b64335b5b9570689cf58daca02f5fcc865d69826d9a4d6ebfe4e80c1d7f","observation_id":"33a8a806-38ee-4ca4-8352-5e496703a043","resolution":{"observed_at":"2026-08-12T19:08:27.863158Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.556938Z","title":"Macc-sram: A multistep accumu- lation capacitor-coupling in-memory computing sram macro for deep convolutional neural networks,","venue":null,"work_id":"c992d470-7903-42bd-873c-070a77b8e4d9","year":1938},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:27.867535Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:d03df345586e791a3cd41720b8f1f0e92e58dd589979264911fc81b6c9aab226","observation_id":"0e1502e0-3311-43b5-8304-a09337804da8","resolution":{"observed_at":"2026-08-12T19:08:30.562159Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.544056Z","title":"A 28-nm 50.1-tops/w p-8t sram compute- in-memory macro design with bl charge-sharing-based in-sram dac/adc operations,","venue":null,"work_id":"c4193060-936b-4932-90f3-d71f3f8d8878","year":1926},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:27.873830Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:8075b30bcce40a9708cfbf2b658722977ffcff6ac03d37b099661781b3aba5cc","observation_id":"0995c995-2d6a-477f-a4c4-0b011fc386b4","resolution":{"observed_at":"2026-08-12T19:08:30.548737Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.529692Z","title":"Pimca: A programmable in-memory computing accelerator for energy-efficient dnn inference,","venue":null,"work_id":"cee6adff-76e4-420b-a33b-3ba8db51f7a3","year":2023},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:27.877981Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:5a65687f7dc8ec319eb5f9f6599687cdce824782cc11fb9aeef970614a5d99b9","observation_id":"460c642b-5341-477c-a868-1e2cd98d74c0","resolution":{"observed_at":"2026-08-12T19:08:30.535118Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.489632Z","title":"A 4-bit mixed-signal mac macro with one-shot adc conversion,","venue":null,"work_id":"789bff6b-dbfa-4573-b120-93a83bf6b531","year":2023},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:27.882155Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:9c0dc6a7d4540b1c76b8b0c1c0fe61b24241a3edc4b2cf4f5ae6a4c4efc51e27","observation_id":"4e4bbf9d-d0e2-4092-916f-fa8c2850fcee","resolution":{"observed_at":"2026-08-12T19:08:30.520274Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.436557Z","title":"Pico-ram: A pvt-insensitive analog compute- in-memory sram macro with in situ multi-bit charge computing and 6t thin-cell-compatible layout,","venue":null,"work_id":"4fe8a1f7-0117-4c43-96a8-c9a468cb755e","year":2024},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:27.886567Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:8a03b56f97e5ed6ecf5c086de7941799fe2ee7e9b97d5ba2c6a5eac276a52d4c","observation_id":"81d13587-cfc5-47d8-a09a-53a4e14ff82b","resolution":{"observed_at":"2026-08-12T19:08:30.455567Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.422299Z","title":"15.1 a programmable neural-network inference accelerator based on scalable in-memory computing,","venue":null,"work_id":"07dac691-1d66-4655-bab3-a6fb38a728a2","year":2021},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:27.890869Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:1e52c262697688db5076df085d0dbb5856ecd8901f07396a62cdbbc7de8919d0","observation_id":"bf1397ef-5467-4507-9e94-7a7659d940c6","resolution":{"observed_at":"2026-08-12T19:08:30.426703Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:27.973801Z","title":"C3sram: An in-memory- computing sram macro based on robust capacitive coupling computing mechanism,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:27.973801Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:52a69edae79d933c34814aa664d14d1c3be7f05e03b8aa97f1d5bd6de9c9f5c4","observation_id":"2f07eb85-fb58-4467-9daa-75397c2719b8","resolution":{"observed_at":"2026-08-12T19:08:27.973801Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.401156Z","title":"A fully bit- flexible computation in memory macro using multi-functional computing bit cell and embedded input sparsity sensing,","venue":null,"work_id":"1158f3de-06b6-416a-95d2-468c405ef73f","year":2023},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.054757Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:70634b29cde2bc13de78cf272b54146e4b39612e17a8457f43b8e3135a7d2fd0","observation_id":"6462eb7d-0cb5-48c6-8ad9-22eb1ab84029","resolution":{"observed_at":"2026-08-12T19:08:30.406107Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.315358Z","title":"Neurosim: A circuit-level macro model for benchmarking neuro-inspired architectures in online learning,","venue":null,"work_id":"fb0a3134-a4fb-4783-a436-7bf3e1ec5591","year":2018},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.157092Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:1fbc9c49022f3d4c8bc995f6b1398a66d78c150360947115fe98220edec69941","observation_id":"38ad8520-3d44-4552-97ee-358c29130d9b","resolution":{"observed_at":"2026-08-12T19:08:30.357707Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.296463Z","title":"Syscim: Systemc-ams simulation of memristive computation in-memory,","venue":null,"work_id":"03e9090f-5180-4c08-8aa0-0a4c34f98982","year":2022},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.231440Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:798edbdcac471cfdf9c9961c0d028f806a2aa295ad7c5828c8d662ddbf0d5f94","observation_id":"62b43489-9523-4e2a-b5f6-81512d822c3b","resolution":{"observed_at":"2026-08-12T19:08:30.301157Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.282940Z","title":"Pimsim-nn: An isa-based simulation framework for processing-in-memory accelerators,","venue":null,"work_id":"65d30b86-b053-45db-b2d4-e1184879af51","year":2024},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.264155Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:2c976b6f4cf69d189c3d193cec7978f92d204f3fa67d504ef19acbdc26cc7985","observation_id":"f9f162e7-3419-4b2a-85b2-fdce21a44e41","resolution":{"observed_at":"2026-08-12T19:08:30.287710Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.270325Z","title":"A flexible and fast pytorch toolkit for simulating training and inference on analog crossbar arrays,","venue":null,"work_id":"c4e3a8f2-3f2c-4b25-9a8d-f270384e7bc3","year":2021},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.274562Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:b68af5b1d727708b7167333f3b72e531bf9d51a4fa8465074d26c381e5215788","observation_id":"9a7f7693-a210-4808-9a62-f4487f0b885d","resolution":{"observed_at":"2026-08-12T19:08:30.274669Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.212570Z","title":"Memtorch: An open-source simulation framework for memristive deep learning systems,","venue":null,"work_id":"75581e30-ae2c-4503-9c0d-0dfaf173f831","year":2022},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.278848Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:88ded9f87b082e01fe6b6d1a53e7f0e308a1db874528a4d98aa6e23b74d74e98","observation_id":"a5d129f8-dcae-48ca-aabc-237e379bb1a3","resolution":{"observed_at":"2026-08-12T19:08:30.260845Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.074260Z","title":"ef2lowsim: System-level simulator of eflash-based compute-in-memory accelerators for convolu- tional neural networks,","venue":null,"work_id":"fba70449-8875-445c-8348-4774765f23e5","year":2023},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.282443Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:32b84a85da1e375bf487b4bb73581082f9c2dfb25a9bea78db8d3f1d8f06a131","observation_id":"c82c0365-0fa9-41d2-9b15-618e2b01ac85","resolution":{"observed_at":"2026-08-12T19:08:30.120906Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.063240Z","title":"A user-friendly fast and accurate simulation framework for non-ideal factors in computing-in-memory architecture,","venue":null,"work_id":"7a819585-79a4-4a94-9266-ad97f7baef6f","year":2023},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.287265Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:43e96937aeec3ede74cb9d82312f642dd4b8cbc955b888459ad5703f4e565479","observation_id":"afc174d4-1390-4d45-b6a7-a3ed93d8bd3a","resolution":{"observed_at":"2026-08-12T19:08:30.066943Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.048990Z","title":"X-pim: Fast modeling and validation framework for mixed-signal processing-in-memory using compressed equivalent model in system verilog,","venue":null,"work_id":"cf885ba6-a3bf-43ac-816e-42eff76c92ea","year":2024},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.291335Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:f1fd0fe4b5be688504ad81f0c60e299bb07c180550e25514bf984f1a23e2af15","observation_id":"5836d0f0-38b3-4a36-b69c-9d1359bd866a","resolution":{"observed_at":"2026-08-12T19:08:30.054236Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:30.037380Z","title":"Deep in-memory architectures for machine learning–accuracy versus efficiency trade- offs,","venue":null,"work_id":"ec8ace06-951d-46fe-86c7-97879f707450","year":2020},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.315847Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:1c1ddf821fddf1b05d6c495c14e49f6204e03e1dac0089849400d9e58afacc69","observation_id":"c25a450a-dc24-4cd1-8491-aceb11c98117","resolution":{"observed_at":"2026-08-12T19:08:30.041229Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:29.936486Z","title":"Fun- damental limits on the precision of in-memory architectures,","venue":null,"work_id":"64b222d3-7d77-48e0-8ecc-d9f372c88f0b","year":2020},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.320481Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:5679e6ec8504418daa6e0c86e65a8ce0d811b5ad2db1e19536505122d0db86da","observation_id":"2c4fdebb-278c-4937-89ba-591e330b7462","resolution":{"observed_at":"2026-08-12T19:08:29.981276Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:28.324730Z","title":"A programmable heterogeneous microprocessor based on bit-scalable in-memory comput- ing,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.324730Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:a076040b6214346dae84c6683698f0e5a6f73f88bc9a11eac2e85eb1398c8c43","observation_id":"21fbd90d-b849-4d6f-b611-58ef49a9ad5b","resolution":{"observed_at":"2026-08-12T19:08:28.324730Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:28.415556Z","title":"A 818–4094 tops/w capacitor-reconfigured analog cim for unified acceleration of cnns and transformers,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.415556Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:1f7b2cd32a2812f72a250e01fa84ff4f64eaea64307967ecb2ff83a3e1ee2d95","observation_id":"8380e860-1eb0-4c47-8eed-eada9cc88210","resolution":{"observed_at":"2026-08-12T19:08:28.415556Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:28.476273Z","title":"Noise modeling and analysis of sar adcs,","venue":null,"work_id":null,"year":2015},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.476273Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:32a5af39f0f4953b1d2f70dc8cc83de8e241eefe367f183344484cd5dc0d639e","observation_id":"b1f577d0-df31-4205-afd8-baf616d876b5","resolution":{"observed_at":"2026-08-12T19:08:28.476273Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:29.849275Z","title":"Simulation and analysis of random decision errors in clocked comparators,","venue":null,"work_id":"ef293893-09ec-4576-bc1c-d3ae369c30a7","year":2009},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.508426Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:baac7a180d731bdc43add89085cfdf1e13b5af5fef0f11f0e014f747d3bf5f9e","observation_id":"e63e13bb-7ac9-49eb-817d-6e89c8f23d7e","resolution":{"observed_at":"2026-08-12T19:08:29.852910Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:28.570320Z","title":"Mismatch characterization of small metal fringe capacitors,","venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.570320Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:50e456f7a1fbeccab5667a9e740cbf0025c3e1d2a79bdb643acb23f4ea80e6f2","observation_id":"569e04c7-901e-4484-9c39-805c2b2e2897","resolution":{"observed_at":"2026-08-12T19:08:28.570320Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:29.831147Z","title":"Modeling and optimization of sram-based in-memory computing hardware design,","venue":null,"work_id":"a8024ecb-612e-4c8f-9879-578021bf0504","year":2021},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.617204Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:c81eae0399bf281fc7879175d54f7de7f405059201fa2e4e3da499a093fcbd8f","observation_id":"fcf4610a-e5a9-44a4-bbd1-7a4d086cd1ec","resolution":{"observed_at":"2026-08-12T19:08:29.835464Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:29.820167Z","title":"34.5 a 818-4094tops/w capacitor-reconfigured cim macro for unified acceleration of cnns and transformers,","venue":null,"work_id":"288f5824-074a-4a71-97d1-abb845329bc4","year":2024},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.621723Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:657784169708b44a879e21454a3be26deb7cb154fb2baf07575300cb5b478a76","observation_id":"1dfd9155-b4f5-4a59-96c9-b6860d5b75d4","resolution":{"observed_at":"2026-08-12T19:08:29.823842Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:28.625689Z","title":"Dnn+neurosim: An end- to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.625689Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:1ebdec942bf8f5738678f8210fed39131709972b7a8b5b03ee4289b47a559912","observation_id":"57ffb122-22c5-4047-b88a-ae21263b9012","resolution":{"observed_at":"2026-08-12T19:08:28.625689Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2106.08295","last_updated":"2021-06-15T17:12:42Z","snapshot_observed_at":"2026-08-19T05:42:08.537901Z","submitted_at":"2021-06-15T17:12:42Z","title":"A White Paper on Neural Network Quantization","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2106.08295","snapshot_observed_at":"2026-08-12T19:08:28.630709Z","title":"A white paper on neural network quantization,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.630709Z"},"links":{"cited_paper":"/paper/2106.08295","citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:53d726484f6ff80c2e8ce77d8209ac4383ee191177ba3aff033742d2feb1aaff","observation_id":"b528c6b8-7501-4331-9fa6-60511625591e","resolution":{"observed_at":"2026-08-12T19:08:28.630709Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:29.801639Z","title":"Low-cost 7t-sram compute-in-memory design based on bit-line charge-sharing based analog-to-digital conver- sion,","venue":null,"work_id":"095f9347-7444-4ad2-85de-efe053602474","year":2022},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.634969Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:d6f0ab6d31d1741403d716272caa4be4ea010774ae2a2210a73f504090e75b41","observation_id":"b5ade5ee-220d-4afe-b2ba-17295410a2de","resolution":{"observed_at":"2026-08-12T19:08:29.805834Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2109.12948","last_updated":"2021-09-27T10:57:18Z","snapshot_observed_at":"2026-08-21T15:54:46.484963Z","submitted_at":"2021-09-27T10:57:18Z","title":"Understanding and Overcoming the Challenges of Efficient Transformer Quantization","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2109.12948","snapshot_observed_at":"2026-08-12T19:08:28.638542Z","title":"Understanding and overcoming the challenges of efficient transformer quantization,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.638542Z"},"links":{"cited_paper":"/paper/2109.12948","citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:8feca2b7c4365cda5dc938fc5777f4769d163414865dfcf470bcce3860016f60","observation_id":"c40f9115-53c2-429d-8db5-acb26df7374e","resolution":{"observed_at":"2026-08-12T19:08:28.638542Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:29.700514Z","title":"Pacim: A sparsity-centric hybrid compute-in-memory architecture via probabilistic approximation,","venue":null,"work_id":"c507e95e-f2b0-4825-a3c7-048419a3b568","year":2024},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.642813Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:065cc0dcf7d274f9b264b215757a469a400f562e4cad20625586a8c8c88775ff","observation_id":"3ad48fa3-9553-47ef-ab19-1fb895af0284","resolution":{"observed_at":"2026-08-12T19:08:29.736160Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:29.612695Z","title":"Hybrid analog-digital in- memory computing,","venue":null,"work_id":"7721b13a-0464-432f-9896-1200e9f209c4","year":2021},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.647566Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:ab324ed25ae3ce0abda8891a2adde95f8abc8b0f9fd903fe8b8c81cfe6341789","observation_id":"75a0f058-9352-4844-a355-e9304a288f18","resolution":{"observed_at":"2026-08-12T19:08:29.618498Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:28.653520Z","title":"A 22nm 832kb hybrid-domain floating-point sram in-memory-compute macro with 16.2-70.2tflops/w for high-accuracy ai-edge devices,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.653520Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:be174bf32a16cd7ebce2931e9b2f2e2c4b2aee252e49903a41199f1d0b1e426a","observation_id":"848c3888-65a7-47c3-adb9-8953c19d7e0e","resolution":{"observed_at":"2026-08-12T19:08:28.653520Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:29.589474Z","title":"Osa-hcim: On-the-fly saliency-aware hybrid sram cim with dy- namic precision configuration,","venue":null,"work_id":"9a0ba9c0-54ef-4abe-b208-f4c51688ebce","year":2024},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.658744Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:547899bfd8970ec3dfba2ed83d1f3e304fe4e84fb93ae17c52ac002c56d69782","observation_id":"bd7a02c7-2cd3-4c4f-82a8-88ddd17c8300","resolution":{"observed_at":"2026-08-12T19:08:29.594065Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:29.574302Z","title":"Oversampling adc: A review of recent design trends,","venue":null,"work_id":"dcb7dbea-d0a4-482e-aa20-a4b29f3d695a","year":2024},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.663132Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:6f31429f1b5fc2301e5e400f519dc36b9215b4ecfa38feffe438f77d3df38a3c","observation_id":"7d059c1d-37fa-4e61-9acb-54192e3cf83c","resolution":{"observed_at":"2026-08-12T19:08:29.579618Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:29.359487Z","title":"A 28-nm 0.8m-weights/mm2 9.1-tops/mm2 sram-based all-analog compute-in-memory using fine-grained structured pruning with adaptive-ranging adc,","venue":null,"work_id":"3ba2f270-91fa-4622-9937-5dec5f00dddd","year":2024},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.695090Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:94d88c02cc387ebb5b44ea125f8124266d21f46e2e82f2bf9af9575362c477bc","observation_id":"cc7ca5c9-b90d-494c-a443-0f29d19c9e19","resolution":{"observed_at":"2026-08-12T19:08:29.461023Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:28.766055Z","title":"A switched-capacitor sram in-memory computing macro with high-precision, high-efficiency differential ar- chitecture,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.766055Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:e6ac51b9e492162d17e90b27678d56c419ae8ab6a655d1696630e8f433034d52","observation_id":"4396f354-c9c2-4741-af5f-0a70ed103d81","resolution":{"observed_at":"2026-08-12T19:08:28.766055Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:29.186111Z","title":"14.6 a 28nm 64kb bit- rotated hybrid-cim macro with an embedded sign-bit-processing array and a multi-bit-fusion dual-granularity cooperative quantizer,","venue":null,"work_id":"c12c131d-b0b8-4e8b-858e-d3464530089b","year":2025},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.845939Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:398e5ed08f89da794ce3f582e5b633e59eee5af6c48cd9b7d3983a0dda3bad9c","observation_id":"00603778-41eb-4dc7-aac6-b702dffe7a64","resolution":{"observed_at":"2026-08-12T19:08:29.278380Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:28.998269Z","title":"16.4 an 89tops/w and 16.3tops/mm2 all-digital sram-based full-precision compute-in memory macro in 22nm for machine-learning edge applications,","venue":null,"work_id":"65937f3b-5a5f-459e-859d-76c4fa6ee36f","year":2021},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.894129Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:c4455663ae733b105c209bec2b2c49414d762f2e5612aa77c224e45e0a7d156b","observation_id":"262b5849-7d1d-40d6-a784-187381cf9bb1","resolution":{"observed_at":"2026-08-12T19:08:29.066772Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T19:08:28.978750Z","title":"Dimc: 2219tops/w 2569f2/b digital in-memory computing macro in 28nm based on approximate arithmetic hardware,","venue":null,"work_id":"f2454f31-c00b-4ada-a2f0-a3a84a8e69c0","year":2022},"citing_paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits","version":4},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-08-12T19:08:28.898802Z"},"links":{"citing_paper":"/paper/2411.11022"},"observation_digest":"sha256:ea407f9bd529ac22c4f0253bf4037a118575ec4b09855bcaf1b8e0b4bf3a5394","observation_id":"afa2c1e2-9832-4d07-8a46-9c9299ce388b","resolution":{"observed_at":"2026-08-12T19:08:28.986135Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2411.11022","last_updated":"2025-09-02T13:29:12Z","latest_version":4,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-17T01:16:55.092781Z","submitted_at":"2024-11-17T09:58:37Z","title":"ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits"},"reference_resolution":{"displayed":44,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":15,"verified_exact":0,"verified_fuzzy":29},"total_outbound_references":44},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"thesis":"As of 22 August 2026, this Paper Citation Record lists 44 of 44 outbound references and 0 inbound Pith citation observations for arXiv:2411.11022."}