{"as_of":"2026-08-12T23:30:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:4c16027afd67477e08f8fd6a42f3c5eb0dc12fb2652a5935278899d3c151066d","coverage":[{"denominator":40,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":40,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-12T12:28:03.629933Z","state":"measured"},{"denominator":40,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":40,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-12T06:34:41.77262+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2411.17198/citation-record","integrity":"/paper/2411.17198/integrity","json":"/paper/2411.17198/citation-record.json","paper":"/paper/2411.17198"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:05.636105Z","title":"Dependable Multicore Architectures at Nanoscale: The View From Europe","venue":null,"work_id":"a2b865cb-5cd4-4800-96b4-389ac7ca5863","year":null},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.484584Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:1c2feae1e08be715e97f32d46fafca863f89431bb56e95cbd1bf308882e98ed0","observation_id":"22a7f360-0727-4af9-97cf-5c294939d156","resolution":{"observed_at":"2026-08-12T12:28:05.639728Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2003.81312","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:05.476621Z","title":"Basic mechanisms and modeling of single -event upset in digital microelectronics","venue":null,"work_id":"2477c18e-ec4f-480a-9056-d84b720e5f3b","year":2003},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.492405Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:0f7aebc8c1bec8f47790807134f8c2271ff9363e983f7d6be0ffd8a697628a87","observation_id":"3adf1088-f9cf-4018-8930-28b00a018d39","resolution":{"observed_at":"2026-08-12T12:28:05.483178Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1109/iolts.2006.35","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.742145Z","title":"Factors that impact the critical charge of memory elements,","venue":null,"work_id":"046e3a8f-a653-4103-b249-82503363b60b","year":2006},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.496270Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:a6c331873f214a77ce00df7742c619006448cc5f1237683efb769177f69eea44","observation_id":"3b7eb85e-009c-4e94-89df-49fcbec4bf6d","resolution":{"observed_at":"2026-08-12T12:28:03.745791Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2009.51733","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:05.410226Z","title":"Analysis of radiation -hardening techniques for 6 T SRAMs with structured layouts","venue":null,"work_id":"7545be71-e7b7-4341-a3af-37e42046607c","year":2009},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.499917Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:3f745f0329c5e80498c792f756ed1ad76887ac39376a4025ee7efb4e2b4ed0e6","observation_id":"478f455f-2e2e-4321-bca6-4c8936922524","resolution":{"observed_at":"2026-08-12T12:28:05.415730Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.503779Z","title":"Impact of Technology Scaling on SRAM Soft Error Rates,","venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.503779Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:02f874672adf8cf4c67bd5df8eb4299d051bc1353c34e4aa7c28f197cf43613b","observation_id":"ed920419-e7cb-471d-9d3d-5c8f57875b48","resolution":{"observed_at":"2026-08-12T12:28:03.503779Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2007.91750","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:05.230824Z","title":"An 8T -SRAM for Variability Tolerance and Low -Voltage Operation in High -Performance 16 Caches,","venue":null,"work_id":"35036106-8bf7-4557-80a1-a85de0f2476b","year":2008},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.507673Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:44cd1f710ce54c3a8b1f997fed6204706884a035e6bd31b9a2b505f5183f1e9e","observation_id":"6986ee11-3b50-47c4-a4c6-5d0714dc5234","resolution":{"observed_at":"2026-08-12T12:28:05.236261Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2014.23116","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:05.149050Z","title":"SRAM Alpha -SER Estimation From Word -Line Voltage Margin Measurements: Design Architecture and Exper imental Results","venue":null,"work_id":"34e4b462-adff-4fa0-8b21-ff6f66e52b31","year":2014},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.511609Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:eebcc8b7e6280097c7f7714c3442c5322757ba5ed7f07ababb88d03d8a954d75","observation_id":"db80dd9f-5816-4908-82fd-1ab430454e43","resolution":{"observed_at":"2026-08-12T12:28:05.154921Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:05.625431Z","title":"A Soft Error Tolerant 10T SRAM Bit -Cell With Differential Read Capability","venue":null,"work_id":"ec9392f2-3a72-459b-9d16-4741804c83c1","year":null},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.515788Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:bda4646ae12176a8a2ff4564f1a21c7fcb73a9de1fbe0c2e613756c1122c1a63","observation_id":"1c3ac8c6-9588-4896-bc4f-97179588b96a","resolution":{"observed_at":"2026-08-12T12:28:05.629195Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1016/j.microrel.2012.01.003","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.731218Z","title":"Variability aware low leakage reliable SRAM cell design technique","venue":null,"work_id":"1ae4ae6b-7880-4322-a851-378115e4c53b","year":2012},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.522762Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:dff285ea6b01659e92218e2aaad2e9dee89356a6565a70a0d92ccdead173aeaa","observation_id":"29453145-a76a-4d96-88bc-11c95bf7ae10","resolution":{"observed_at":"2026-08-12T12:28:03.735044Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1109/23.556880","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.720633Z","title":"Upset hardened memory design for submicron CMOS technology,","venue":null,"work_id":"63ae8d09-175b-4419-a90b-e19f7c7b1b2f","year":1996},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.526461Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:b5b33bb7860e75becf4d210e083f609c920f8a65477acd9381264643e81c11ed","observation_id":"0ab21281-0ec3-497e-af11-60d05fcca83e","resolution":{"observed_at":"2026-08-12T12:28:03.724207Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1016/j.sse.2015.05.036","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.709519Z","title":"Detailed 8-transistor SRAM cell analysis for improved alpha particle radiation hardening in nanometer technologies","venue":null,"work_id":"60b2e04c-8192-4313-b34c-86912c6c8514","year":2015},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.529945Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:cbb2aa5281b4082df5be51a8e2f43c73ced6ad4f7d9b2bb71389ededacbaa26a","observation_id":"ec900bdf-0599-4455-a736-64930d68e7d6","resolution":{"observed_at":"2026-08-12T12:28:03.713492Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:05.615235Z","title":"Autran, D","venue":null,"work_id":"aa8fb73e-1e9f-442a-bfdf-7d708ce15b07","year":2015},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.537290Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:8f03a4a76c1a4fce5579510f6fbb58a5aabb5e0712e25cb37dcd9ece4ab453d7","observation_id":"5180aed4-723e-4978-bd0f-95e809521b25","resolution":{"observed_at":"2026-08-12T12:28:05.618716Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1371/journal.pone.0144679","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.698484Z","title":"Analytical Model for Estimating Terrestrial Cosmic Ray Fluxes Nearly Anytime and Anywhere in the World: Extension of PARMA/EXPACS","venue":null,"work_id":"86355b58-767f-49f3-8ea0-9c04aaf14672","year":2015},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.540641Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:63299d6e08c421547aadd48743d8abd7701bedf10b2cb4620d5cc524f427ef32","observation_id":"7c691c17-5c77-4a3f-8abb-a938ee87c5b4","resolution":{"observed_at":"2026-08-12T12:28:03.702284Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2015.24912","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:04.928094Z","title":"Electron -Induced Single- Event Upsets in 45 -nm and 28 -nm Bulk CMOS SRAM -Based FPGAs Operating at Nominal Voltage,","venue":null,"work_id":"204c48b4-63eb-4823-ad1e-79d208305129","year":2015},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.544097Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:590a9a7f3507b15536b2b6fb2ab226ebc3d1fc3d53a5e1fbba892845882cff88","observation_id":"936f1512-27f7-4919-bf5e-a292856e028c","resolution":{"observed_at":"2026-08-12T12:28:04.933182Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2016.75746","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:04.858389Z","title":"Predicting the vulnerability of memories to muon -induced SEUs with low - energy proton tests informed by Monte Carlo simulations,","venue":null,"work_id":"cf2a17d6-5fdf-4f56-8467-dc520ac895e1","year":2016},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.547367Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:94a5af5ebf4bee1424b68f78a8ae975b670684d61cc5fb2b9a9a1a68ed97517e","observation_id":"91538460-bd4d-4aaf-9e71-b822f43afe07","resolution":{"observed_at":"2026-08-12T12:28:04.863595Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.550800Z","title":"Study of atmospheric muon interactions in Si nanoscale devices","venue":null,"work_id":null,"year":2017},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.550800Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:44ccf466672cb4c2b1047fefbf51056bd629631b5efba06b6ed6942db28a4337","observation_id":"6848a059-8577-4443-a04c-f6aefb51c5f2","resolution":{"observed_at":"2026-08-12T12:28:03.550800Z","resolver_source":null,"status":"malformed_identifier"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2016.26212","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:04.791019Z","title":"Monte Carlo Evaluation of Single Event Effects in a Deep - Submicron Bulk Technology: Comparison Between Atmospheric a nd Accelerator Environment,","venue":null,"work_id":"d739c36d-e749-4bf3-80d5-633ed09b19e6","year":2017},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.554440Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:d8adfa9e9c3d13f5f58e1730f432734f35f4b87fd6cacb153cfa0fc5dde52179","observation_id":"6cdfeaa1-0140-4649-a8f8-9a822d23a4d8","resolution":{"observed_at":"2026-08-12T12:28:04.796088Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.557823Z","title":"SEE Measurements and Simulations Using Mono -Energetic GeV -Energy Hadron Beams,","venue":null,"work_id":null,"year":2013},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.557823Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:13d8a9be4b780f357b352b248b7e791594fc27e40a0ae96f571808dad3d7e80b","observation_id":"8e57e191-ef56-413e-a965-cc85a47f756d","resolution":{"observed_at":"2026-08-12T12:28:03.557823Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2018.28317","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:04.646017Z","title":"Impact of Thermal and Intermediate Energy Neutrons on SRAM SEE Rates in the LHC Accelerator","venue":null,"work_id":"1568ecdb-06ad-490e-8e2d-db21044339fd","year":2018},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.561398Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:e705838302f6b3da82d0dbc5ebb22d4a4ecfc19e8848b15aaf52ecee38f2b9a1","observation_id":"944656da-1f2c-4734-b4a3-ea127c02b08f","resolution":{"observed_at":"2026-08-12T12:28:04.651387Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"epjn/2017031","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:04.558661Z","title":"Single Event Effe ct cross section calibration and application to quasi - monoenergetic and spallation facilities","venue":null,"work_id":"ff2649fd-40db-4cc9-bff7-cc8abdf64df8","year":2018},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.565117Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:c13411ecf36b0b2650eec8964cf8b51adf3f35ca835147453a2fe1e972f4b423","observation_id":"3d469698-c21c-4569-a437-d6f36872dff8","resolution":{"observed_at":"2026-08-12T12:28:04.564176Z","resolver_source":"raw_fallback","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.568556Z","title":"Method for measuring mixed field radiation levels relevant for SEEs at the LHC,","venue":null,"work_id":null,"year":2012},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.568556Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:40ea2e9d9e03ce4c2106fd95d96488ffab85e899ee319976025c84fcd195fa77","observation_id":"f0b1560f-7cd9-4938-8bba-edb5ef517be3","resolution":{"observed_at":"2026-08-12T12:28:03.568556Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1016/s0026-2714(00)00218-3","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.680122Z","title":"Neutron-induced 10B fission as a major source of soft errors in high density SRAMs","venue":null,"work_id":"2ea0a0e3-7c00-4af8-a44d-98b65af1c687","year":2001},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.572133Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:0a88ffc39e8b0cbc918b1ec0a039e9f8f45d7d828b2cb0874c9aee222e90f0ef","observation_id":"2570da0e-c4f1-4711-83ca-a29d16dabef0","resolution":{"observed_at":"2026-08-12T12:28:03.684476Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:05.605077Z","title":"Contribution of Ther mal Neutrons to Soft Error Rate","venue":null,"work_id":"bbdd5dd1-506b-4422-8151-c86f1b43b150","year":2018},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.575495Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:c96c4a64f9e01363d07b7acada55913b8880ffb54c12e8b15708237858ebb7ed","observation_id":"0fa50c54-ca6e-4c74-9dbd-b1bc87b7542f","resolution":{"observed_at":"2026-08-12T12:28:05.608531Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2016.76046","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:04.427827Z","title":"On -line write margin estimator to monitor performance degradation in SRAM cores","venue":null,"work_id":"c58c054b-9fff-4748-93d0-be568b846941","year":2016},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.579141Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:5e377da831d4e2721f7e4bfe1b085990e8d415c0b4375cf9c1f880a96c1cc523","observation_id":"807c27f1-f2e5-477a-ac41-d8f0a766205c","resolution":{"observed_at":"2026-08-12T12:28:04.435361Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.582557Z","title":"A 65-nm Reliable 6T CMOS SRAM Cel l with Minimum Size Transistors","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.582557Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:e9e5c5f23c3628954750fc753347e0090dfb7614ecec4de134ffe09f9b484b46","observation_id":"c813fdf0-9a2a-477e-b166-426e55adfb96","resolution":{"observed_at":"2026-08-12T12:28:03.582557Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:05.593662Z","title":"Impacts of test factors on heavy ion single event multiple -cell upsets in nanometer -scale SRAM","venue":null,"work_id":"d5627295-2ac3-49e9-bd3f-ef8ed9c420e0","year":2015},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.586280Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:b69df920da556524f03bb580d33bf5fe9b57f24b722de4e1a59ff8a5af0f2598","observation_id":"e89823f8-ec8d-4b8e-886e-5fda1b343301","resolution":{"observed_at":"2026-08-12T12:28:05.598081Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.589750Z","title":"CHARM: A Mixed Field Facility at CERN for Radiation Tests in Ground, Atmospheric, Space and Accelerator Representative Environments","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.589750Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:1cb3feaa32cf81babfe8cc37be5a9cfa2ff7bf73d8e2d01835172fedd5cff7b2","observation_id":"178edf29-5d64-4677-8156-188422323cd0","resolution":{"observed_at":"2026-08-12T12:28:03.589750Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2010.20976","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:04.216072Z","title":"FLUKA Simulations for SE E Studies of Critical LHC Underground Areas,","venue":null,"work_id":"9735dec9-bb07-4a3e-ab2f-8c33ead618ea","year":2011},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.593865Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:7bc259caaeee532a247cd0eaec9b9d528305c3e65c52c3ded2ca8a32a1130456","observation_id":"0f804d5b-3ef9-4443-bd4c-afddaffcf99f","resolution":{"observed_at":"2026-08-12T12:28:04.221642Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2005.84588","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:04.135354Z","title":"Failure map functions and accelerated mean time to failure tests: New approaches from improving. the reliability stimation in systems exposed to single event upsets,","venue":null,"work_id":"528a39ef-6ed3-4b91-9e68-66c0786483f7","year":2005},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.597365Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:5350b0554007941f3cad1d9641489aec20fee346c5872646df799d99daf34577","observation_id":"9fb5c1f5-b969-42fd-bdd5-bb1e173d2838","resolution":{"observed_at":"2026-08-12T12:28:04.144145Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:05.582777Z","title":"Bevington and D.K","venue":null,"work_id":"5f90bbc4-8795-4b8c-8be0-b75ed18c2a80","year":2003},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.600827Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:0d0eacb156cd52337b4abb3811ebd2d033c8aa11a60441f37d5aa5c0136becf6","observation_id":"eccca570-011b-44d5-8ab7-d02288490224","resolution":{"observed_at":"2026-08-12T12:28:05.586614Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.604425Z","title":"Quantifying the Effect of Guard Rings and Guard Drains in Mitigating Charge Collection and Charge Spread","venue":null,"work_id":null,"year":2008},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.604425Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:5b2aed0264d7f9c46d4f1f96a1b13ee8411f009a094619e019e3b2d533163784","observation_id":"f9f9c94f-a092-412c-a73f-971bbd5e4bba","resolution":{"observed_at":"2026-08-12T12:28:03.604425Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2014.23650","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:04.999968Z","title":"Qualification and Characterization of SRAM Memories 18 Used as Radiation Sensors in the LHC,","venue":null,"work_id":"8fa26635-b012-4b2c-ba64-9f8be188724f","year":2014},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.608032Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:9019b576064313e03f824fd8ad94bf2889585076dc33f47ab53305c4229a626c","observation_id":"cacea7a3-776b-4f5a-8f5b-afd82d89dab2","resolution":{"observed_at":"2026-08-12T12:28:05.005858Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1016/j.microrel.2017.07.093","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.669221Z","title":"Soft error rate comparison of 6T and 8T SRAM ICs using mono -energetic proton and neutron irradiation sources","venue":null,"work_id":"03bb02e5-59aa-4883-8472-597e884161b8","year":2017},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.611723Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:b84ea03d7c0fb82a6a91863873f95ceaf752e53c56a9afd0f6fab3466c06dc85","observation_id":"c7b5d953-1985-4a7c-9799-b3eb4f5da654","resolution":{"observed_at":"2026-08-12T12:28:03.673103Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:05.572310Z","title":"SRAM single event upset calculation and test using protons in the secondary beam in the BEPC","venue":null,"work_id":"4a226718-5283-42a5-9a4a-a8b2d507825e","year":2011},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.615399Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:27e33093d6a84e0ad9013bc323ed06de5dc7053b2b4babea555b86ec650d7c44","observation_id":"ee40b685-88e5-44b6-97a1-d644c4a50de0","resolution":{"observed_at":"2026-08-12T12:28:05.576152Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2009.59946","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.979724Z","title":"A commercial 65nm CMOS technology for space applications: Heavy ion, proton and gamma test results and modeling","venue":null,"work_id":"64fea3a1-d038-44c1-a30f-4bab8f0e0036","year":2009},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.618872Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:94f93dcf64ff5bd85b132003b04433a018b95a3f81896e7d1bad8b947f5281ea","observation_id":"bb621f61-77de-4e1a-9ae5-58479a747b75","resolution":{"observed_at":"2026-08-12T12:28:03.988154Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.622573Z","title":"Low Energy Proton Single - Event-Upset Test Results on 65 nm SOI SRAM","venue":null,"work_id":null,"year":2008},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.622573Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:0b2ca83041209212fc206445efad92eb3773a8e38d801f895a8c453630ddbebb","observation_id":"5d2da97e-7ea6-4e40-92f4-5f8031ea4f88","resolution":{"observed_at":"2026-08-12T12:28:03.622573Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1109/23.659039","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.655938Z","title":"Heavy ion and proton -induced single event multiple upset,","venue":null,"work_id":"7b0089f9-9b1e-4104-83ab-8b52b01e266c","year":1997},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.626356Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:d295d723aa2d3f37f32512d6539dc9e462a31438e75e8d1e0e484ec6ba5d136e","observation_id":"e4332a7d-40f2-46b6-9caa-261fdf249ba1","resolution":{"observed_at":"2026-08-12T12:28:03.661587Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2009.59945","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:03.809779Z","title":"Investigation of neutron and proton SEU cross-sections on SRAMs between a few MeV and 50 MeV","venue":null,"work_id":"21f4a6e6-b07d-40ff-9df1-7bb349b5c4dd","year":2009},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.629933Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:2ce53adf14ad9176044129b195578c89b8a3918f4af6a936b2d725abbee367d3","observation_id":"dd20c3ab-0a56-412d-b44e-8bd1f75e6d9c","resolution":{"observed_at":"2026-08-12T12:28:03.815361Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2009.20320","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:05.066699Z","title":null,"venue":null,"work_id":"75397d0b-7183-4a0e-b4a4-19233f7ba59b","year":2009},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":2009,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.519252Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:cdc7f325d33edd92a7a77bae3ade158e0aa7cade38ebf0a8214a0cbce248ab92","observation_id":"8c32bd39-4a77-4730-a7f5-88e8c837c047","resolution":{"observed_at":"2026-08-12T12:28:05.072096Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2014.23595","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T12:28:05.560185Z","title":null,"venue":null,"work_id":"3c181dc5-634f-4ef8-8539-a653317f3d5b","year":2014},"citing_paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment","version":1},"reference_index":2015,"source":"pdf_text","source_observed_at":"2026-08-12T12:28:03.488745Z"},"links":{"citing_paper":"/paper/2411.17198"},"observation_digest":"sha256:b2b724b29c722026ba6e0aa1209970b503daee360ff3b0efc4c1d33d23a5d029","observation_id":"babdc3b2-7a4a-4450-a7ba-e21d8011c669","resolution":{"observed_at":"2026-08-12T12:28:05.565413Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2411.17198","last_updated":"2024-11-26T08:11:39Z","latest_version":1,"primary_category":"physics.ins-det","snapshot_observed_at":"2026-08-12T12:21:41.367755Z","submitted_at":"2024-11-26T08:11:39Z","title":"Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment"},"reference_resolution":{"displayed":40,"state_counts":{"malformed_identifier":1,"metadata_mismatch":16,"parse_uncertain":0,"unresolved":7,"verified_exact":9,"verified_fuzzy":7},"total_outbound_references":40},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-12T06:34:41.77262+00:00","source":"crossref"},{"observed_at":"2026-08-12T06:34:36.333875+00:00","source":"retraction_watch"}],"thesis":"As of 12 August 2026, this Paper Citation Record lists 40 of 40 outbound references and 0 inbound Pith citation observations for arXiv:2411.17198."}