{"as_of":"2026-08-19T02:36:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:eec88922d2cc8f3e990dfec4d2703ce7c45c1a378149df64ce5fe07ba4107a61","coverage":[{"denominator":47,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":47,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-11T18:04:22.584055Z","state":"measured"},{"denominator":47,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":47,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-18T06:34:40.430872+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2412.08308/citation-record","integrity":"/paper/2412.08308/integrity","json":"/paper/2412.08308/citation-record.json","paper":"/paper/2412.08308"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2023.2219","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.036081Z","title":"Navaux, A","venue":null,"work_id":"f7255f5d-906c-4902-9cbb-4da2b2d8caa6","year":2023},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.350436Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:bf2806623746bccd7789ab813badb6d631a6aa000b41d8061eb2b4176d9de6b0","observation_id":"d287b00d-7b8f-4e0e-8248-ee9b71a49e46","resolution":{"observed_at":"2026-08-11T18:04:24.046434Z","resolver_source":"raw_fallback","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.311795Z","title":"Shilov, Discrete GPU sales increase as Intel’s share drops to 0, Tom’s Hardware (9 2024)","venue":null,"work_id":"99ccc906-c09e-4faa-bc18-85a64b7ca114","year":2024},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.355624Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:401a73f4bad94719f557a31bccccbec19f073dc9e8772f158fa346455b1d0313","observation_id":"42f74ae9-e0e9-4efb-a00e-431082c44d4d","resolution":{"observed_at":"2026-08-11T18:04:24.316640Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.295476Z","title":"Norem, Intel has reportedly lost all its discrete GPU market share, Ex- tremeTech (9 2024)","venue":null,"work_id":"35798bf1-0760-4852-acb7-f09019058925","year":2024},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.360715Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:934a44ea8b149afc91ed4e0b297de5452e9ab86a8289df95230948ba1c5b660a","observation_id":"3547df00-a55e-44bc-b0eb-fecbcb85a791","resolution":{"observed_at":"2026-08-11T18:04:24.300688Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.280469Z","title":"URL {https://registry.khronos.org/SYCL/specs/sycl-202 0/html/sycl-2020.html}","venue":null,"work_id":"492b9a0c-fbc1-4fe7-b6f4-ed2e65790601","year":2023},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.365544Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:08bc656960325783cbaffc3ed83e539a2f9c9fb7c96d9930b809f469fbd3a731","observation_id":"660b7525-b15e-435c-a567-fd3b53baf34c","resolution":{"observed_at":"2026-08-11T18:04:24.285265Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.371617Z","title":"Costanzo, E","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.371617Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:bd974b6774425fefbbae4c812b400392529c972eed388f7a4e3c9be90c319bb4","observation_id":"73392458-77ae-4d1c-a0a9-48d2c607e9cd","resolution":{"observed_at":"2026-08-11T18:04:22.371617Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"9825.2023","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:23.958340Z","title":"Costanzo, E","venue":null,"work_id":"72299be8-e278-4cf4-989b-205009b257bc","year":2023},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.376708Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:79655c272954f9a573d4d20c77435a44222602a82c221f336fee8c1889b217b2","observation_id":"b3491412-17d0-448d-a0f3-75aad2f8751c","resolution":{"observed_at":"2026-08-11T18:04:23.966217Z","resolver_source":"raw_fallback","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.264139Z","title":"Costanzo, E","venue":null,"work_id":"12a6be14-0767-4ea1-ba19-d5c2a5f1322f","year":2022},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.381975Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:da9037333d4b0dc606a7a700afd92fde52ab6289d4678461241639e02354fa52","observation_id":"8b76414a-a28f-41a8-aa98-0dc38c74ce0c","resolution":{"observed_at":"2026-08-11T18:04:24.270328Z","resolver_source":"raw_fallback","status":"malformed_identifier"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1109/ipdps.2017.42","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.827524Z","title":null,"venue":null,"work_id":"d6d17034-218d-4f1c-a7a3-9865b510bff7","year":2017},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.386572Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:7d965501ea5b32ffc92aa971ec8cc662f5de785413ad38ad8c13214a57409f44","observation_id":"0fb0bf95-e149-47c9-95e7-2bacf51eaba2","resolution":{"observed_at":"2026-08-11T18:04:22.833103Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1016/c2015-0-02431-5","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.809226Z","title":null,"venue":null,"work_id":"2bbb8bc5-cca1-4593-8ffa-24b80dcc182a","year":2010},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.391167Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:9c38a28476a6cb5a25c54ad4932c1619eeef0d67846977a52fe8462aebad609d","observation_id":"11854c9b-2906-450c-9103-d47b33d712cc","resolution":{"observed_at":"2026-08-11T18:04:22.815554Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.395606Z","title":null,"venue":null,"work_id":null,"year":2010},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.395606Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:543ac2147c5c481762a7f5857229ea3ad95cff50fb5410daf2334600f21d42a6","observation_id":"0814951d-b47e-4cd1-87ac-a08b20dab1c7","resolution":{"observed_at":"2026-08-11T18:04:22.395606Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.249461Z","title":null,"venue":null,"work_id":"c154c7b1-fc55-4d58-856a-f918f2c5b0e5","year":null},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.400470Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:d58df50d8f32f403dc5df272e4e07e320ac24887f54add90cfa10650702b1ff8","observation_id":"7223c03f-6b44-4bea-ac0d-a4d912abc581","resolution":{"observed_at":"2026-08-11T18:04:24.254126Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.234318Z","title":null,"venue":null,"work_id":"a96b4daf-d0bb-48a5-9633-697571b0b221","year":null},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.404964Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:601917827ca874870fa6160853393f5a6f6a7e4240dc5e2f7ef3f66d751d3e4b","observation_id":"f6367d3e-9aef-4ada-bfa7-6cb4b87c0fe2","resolution":{"observed_at":"2026-08-11T18:04:24.239236Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.220940Z","title":"Farber, Parallel Programming with OpenACC, 1st Edition, Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2016","venue":null,"work_id":"3c24ea0b-f0af-4487-916d-337d2d277066","year":2016},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.409484Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:b5aa398c0871bc06dd79e85d6c0f0c6a745d27aae93e28bc11d750804dabbcf3","observation_id":"ddb0825c-972f-4c2b-95c2-2ba030751062","resolution":{"observed_at":"2026-08-11T18:04:24.225196Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1145/2893488","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.774216Z","title":null,"venue":null,"work_id":"ea4790eb-5f1a-498d-b6d9-32cb0a113aac","year":2016},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.418206Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:590cde6f4f064f14d0b487d375d2a1d0b7e97180f451007502b1878ee23f05c9","observation_id":"b0100232-b64f-4baf-9e16-7fad33e74e3d","resolution":{"observed_at":"2026-08-11T18:04:22.779336Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.422669Z","title":null,"venue":null,"work_id":null,"year":1981},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.422669Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:e089342f5eea12cf3b98e518192221871670be67da28db2dbe95d9fd5e9972f7","observation_id":"f04cfa18-77ac-4e0b-8a29-6e88b940226b","resolution":{"observed_at":"2026-08-11T18:04:22.422669Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.427325Z","title":"Gotoh, An improved algorithm for matching biological sequences, in: Journal of Molecular Biology, V ol","venue":null,"work_id":null,"year":1981},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.427325Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:fa572e1ee6976b3e4c3a48c8ecb187553d0c5eef25ca9c543d6dd098d6a185cd","observation_id":"59c63eb0-f82e-4542-a2fe-2fc398852bb3","resolution":{"observed_at":"2026-08-11T18:04:22.427325Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.431671Z","title":"Rognes, Faster Smith-Waterman database searches with inter- sequence SIMD parallelization, BMC Bioinformatics 12:221 (2011)","venue":null,"work_id":null,"year":2011},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.431671Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:100cf399a1deeb0382f9c4c738986bb41dc994b9bdb3b06b069b815c730e7c73","observation_id":"c9d86584-7606-48f1-9b3c-54051afdafe6","resolution":{"observed_at":"2026-08-11T18:04:22.431671Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.436653Z","title":"Pennycook, J","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.436653Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:6c860e3e8adf1b064aceb08b36e8efb2d7cc1333b10fd171f8a899f058d61069","observation_id":"34b32ff0-73d7-4472-9b3f-a677821323a6","resolution":{"observed_at":"2026-08-11T18:04:22.436653Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1002/spe.3002","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-12T11:03:20.376878Z","title":"Marowka, Reformulation of the performance portability met- ric, Software: Practice and Experience 52 (1) (2022) 154–171","venue":"Software Practice and Experience","work_id":"28a1e8ea-fb3f-44e4-9850-d577b2b3a3f8","year":2022},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.441306Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:6c3889f5d4c811d89d5d7bc5491c93f5068964cab4bb4b04b3b94db1f9ab5136","observation_id":"5da9a214-375b-4d34-94fa-2ad29dda5100","resolution":{"observed_at":"2026-08-11T18:04:22.725071Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1093/bioinformatics/btt410","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.704111Z","title":"Korpar, M","venue":null,"work_id":"15e00dd1-01e8-457f-9f39-75ea0ba27feb","year":2013},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.445952Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:e37686a3b7f3c8b11dde42b02546a905556b9e0aa0ffd9fa1a25e910769dc6f3","observation_id":"1e1acf4c-f95f-4155-ac88-3f68785de986","resolution":{"observed_at":"2026-08-11T18:04:22.708786Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.450672Z","title":"Korpar, M","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.450672Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:252e0b33863860c2f804a8035e87d34b9bbb693bb83fe07fdec970a6f9f58c5b","observation_id":"9c8f05c7-f5ef-489b-8914-d551f6c4f664","resolution":{"observed_at":"2026-08-11T18:04:22.450672Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.207444Z","title":"Rucci, C","venue":null,"work_id":"01e32da0-897d-4804-ad29-93a2732c825b","year":2016},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.455320Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:7dcc39289632675f87e038afa0d2590dff393595c671754f91a36bfb2a272105","observation_id":"4a2745de-f922-4cf1-98d6-936b0465c023","resolution":{"observed_at":"2026-08-11T18:04:24.211989Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.193819Z","title":null,"venue":null,"work_id":"ec9d5088-4df3-401a-a862-b89ee336aed0","year":2023},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.464527Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:b8df1d3f0cf2d5fff6223d39f9a3be8e974e328f84083fb5e7eef93e4f383aa0","observation_id":"ef967be6-b013-4469-ae7f-f70f74a88d8e","resolution":{"observed_at":"2026-08-11T18:04:24.198218Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.179229Z","title":"URL {https://www.intel.la/content/www/xl/es/products/ \\\\platforms/details/alder-lake-s.html}","venue":null,"work_id":"55f61a78-83f4-41a5-9ed8-14aaf9c5632d","year":2023},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.469436Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:95339457c56c65a5eacbce2f70d5b5853ac982b85aaa8903dba2b936fd111ce0","observation_id":"e47fd1ba-e306-4827-a2a2-98c2fffe3289","resolution":{"observed_at":"2026-08-11T18:04:24.184219Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.475036Z","title":"Haseeb, N","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.475036Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:e9360f4b9701b77d40cb3f4f36ac9253f1f945e3648daea0f02bb0e525da0cfb","observation_id":"42c701ff-345a-4eb7-8dbd-1ac2a3b6035d","resolution":{"observed_at":"2026-08-11T18:04:22.475036Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.479525Z","title":"Vasileska, P","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.479525Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:b3259c0ff0b09216e31e0123e2bf942b3ee37047c55d5f0cf6670aa11afafe3e","observation_id":"25459a52-9477-4f70-b8b0-55685540a521","resolution":{"observed_at":"2026-08-11T18:04:22.479525Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"5508.35455","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:23.656983Z","title":null,"venue":null,"work_id":"d77ef74b-50bc-490b-99d2-3114df2601cb","year":2022},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.484021Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:faed25ce7193c91e3e246c8c8045af3d90273c3d53cb416ad0c46e3ef5a509a4","observation_id":"0a37fe84-7c82-4562-99a1-639fc046f399","resolution":{"observed_at":"2026-08-11T18:04:23.664077Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.164663Z","title":null,"venue":null,"work_id":"4d801bac-4617-4e53-acf5-d5d5507284d5","year":2022},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.488888Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:8d191217906fd2ac2d48f650988f93b83cd663481d3e55dd0294216eb87c8e87","observation_id":"4f01c38d-1f85-43e3-8837-ac8190772611","resolution":{"observed_at":"2026-08-11T18:04:24.169122Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.498290Z","title":"Solis-Vasquez, E","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.498290Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:ccbbbad303f64f6db4f21e7e75defa091407b49b89709351e98bf92b93c912ec","observation_id":"d2f891ed-7469-40a5-81b0-e9b6b5a73ae5","resolution":{"observed_at":"2026-08-11T18:04:22.498290Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.150384Z","title":"Casta ˜no, Y","venue":null,"work_id":"c682ef61-735b-4296-9bea-0dd0248bb049","year":2022},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.502558Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:84fb468328c2a871ed51d2f27650d351958328f60271234199ffd56a826d9f08","observation_id":"a2c1d4a6-67c1-4a0f-ae00-e2f60010bbdf","resolution":{"observed_at":"2026-08-11T18:04:24.154892Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:23.876098Z","title":"Homerding, J","venue":null,"work_id":"8233b5e4-c6fd-4ad9-909a-6e35f540dc27","year":2020},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.506838Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:712555ec33c188338343f1d02fbfe2f1f4c64fad874ce209526791aa511e6b7b","observation_id":"d918809e-8448-49ea-849e-8216b79cdb9a","resolution":{"observed_at":"2026-08-11T18:04:23.880742Z","resolver_source":"arxiv_id_nonexistent","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.135471Z","title":"Faqir-Rhazoui, C","venue":null,"work_id":"d9ce34ad-f8eb-4d1e-80a6-b3d2feb1e619","year":2023},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.511802Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:ec265ca782b70ea3edf7665c74770cdfd58f7f01bf52f7de773b86cd49d71d3a","observation_id":"51c7e633-1999-4da3-a0c3-79b1fd8c5d35","resolution":{"observed_at":"2026-08-11T18:04:24.140320Z","resolver_source":"raw_fallback","status":"malformed_identifier"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.516332Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.516332Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:b75e3d7cd3be8f1bb29e3d4d10e1ffbd3eddde80c5022291196fbbfa5c3984af","observation_id":"ac8dcff2-b287-4d21-af78-0118dd983983","resolution":{"observed_at":"2026-08-11T18:04:22.516332Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2406.10362","last_updated":"2024-06-14T18:23:36Z","snapshot_observed_at":"2026-08-18T13:39:51.103851Z","submitted_at":"2024-06-14T18:23:36Z","title":"A Comparison of the Performance of the Molecular Dynamics Simulation Package GROMACS Implemented in the SYCL and CUDA Programming Models","version":1},"cited_work":{"arxiv_id":"2406.10362","doi":"10.48550/arxiv.2406.10362","metadata_source":"pith","pith_arxiv_id":"2406.10362","snapshot_observed_at":"2026-08-11T18:16:15.004306Z","title":"A Comparison of the Performance of the Molecular Dynamics Simulation Package GROMACS Implemented in the SYCL and CUDA Programming Models","venue":"cs.DC","work_id":"465c4f46-e4f0-47b6-a92c-ce49f6648c83","year":2024},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.521149Z"},"links":{"cited_paper":"/paper/2406.10362","citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:5fb44a2929095c39ff08ccd08d32604af2deba424518e48ab36350056ba88cc5","observation_id":"a9106db9-c5f3-472e-937f-a5d707fe442a","resolution":{"observed_at":"2026-08-11T18:04:22.666247Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.120184Z","title":null,"venue":null,"work_id":"f4ed6f28-7bbf-44a6-83d0-ae4cabf20075","year":2024},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.526378Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:577566f39f3927d236e2520121c45e6b50fcb7a8b3a2efc8521d3a0e208b8f08","observation_id":"0f5c8229-87f6-4f51-9ab9-19f0c53024d6","resolution":{"observed_at":"2026-08-11T18:04:24.124730Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1007/s11227-024-05957-6","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.639518Z","title":"Faqir-Rhazoui, C","venue":null,"work_id":"718edceb-7211-47ce-905f-bf899f985ee7","year":2024},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.531214Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:e2c0c40ca6187348a380ceb3f8102543349d3334d29ebeb453c41df64a4017e5","observation_id":"35117583-f966-415a-ac74-25baac1a08f6","resolution":{"observed_at":"2026-08-11T18:04:22.644438Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.105310Z","title":"Schmidt, F","venue":null,"work_id":"b0cf6028-afaf-464c-99a2-cff063933b06","year":2024},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.535887Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:54889a3e123abad7e1498fb8086a2faeffe93d1bdbc3afc5b33a58af40192e5e","observation_id":"581c8119-c7fd-4e5a-a1ec-24c704d0afc9","resolution":{"observed_at":"2026-08-11T18:04:24.110596Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.089315Z","title":null,"venue":null,"work_id":"2b308eb1-3801-407f-bdff-54f490ad944f","year":2023},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.540789Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:53f9f9c6387dfed3baaa0536bfef90ac9aea35b3a59b1b90ee7a896849114770","observation_id":"234b41bd-223d-4d0b-96ef-f18f9cd49628","resolution":{"observed_at":"2026-08-11T18:04:24.094385Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.073908Z","title":"Franquinet, Performance portability analysis of sycl with a classical cg on cpu, gpu, and fpga, Master’s thesis (2023)","venue":null,"work_id":"3bf6f205-23a8-444c-b794-bf3dea493c60","year":2023},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.555159Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:a92dfe3937137f2e0e0d1cc0df5198e20aaaa22abf862054c07d81fbfedc2751","observation_id":"dcd5aea3-1816-4626-88db-f565fcfb6f68","resolution":{"observed_at":"2026-08-11T18:04:24.078982Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2409.03391","last_updated":"2024-09-05T09:52:04Z","snapshot_observed_at":"2026-08-18T02:08:02.961872Z","submitted_at":"2024-09-05T09:52:04Z","title":"Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL","version":1},"cited_work":{"arxiv_id":"2409.03391","doi":"10.48550/arxiv.2409.03391","metadata_source":"pith","pith_arxiv_id":"2409.03391","snapshot_observed_at":"2026-08-11T18:16:15.004306Z","title":"Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL","venue":"cs.DC","work_id":"ffad68d7-198a-47c0-97cf-7aaf36ee9921","year":2024},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.559687Z"},"links":{"cited_paper":"/paper/2409.03391","citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:267e278ce1792489cbcb400150aa8c212b8f84bf330d350cb2c6c9305c23141d","observation_id":"7aae863f-df0e-42cf-b245-17c1844db81c","resolution":{"observed_at":"2026-08-11T18:04:22.627770Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.564939Z","title":"Nguyen, P","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.564939Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:0ed5d08373e7316f232df220bd52159857fcae00fd012a8477d13d6497fd37c2","observation_id":"6803367d-fc91-44cf-a316-bf624910e588","resolution":{"observed_at":"2026-08-11T18:04:22.564939Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2310.06947","last_updated":"2023-10-10T19:07:52Z","snapshot_observed_at":"2026-08-16T14:53:19.036689Z","submitted_at":"2023-10-10T19:07:52Z","title":"Open SYCL on heterogeneous GPU systems: A case of study","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2310.06947","snapshot_observed_at":"2026-08-11T18:04:22.569354Z","title":"Carratal ´a-S´aez, Y","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.569354Z"},"links":{"cited_paper":"/paper/2310.06947","citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:6c9cce5b1ebb6bcc64c5079d2a4ac24f66245d8abc7b8ebd5cc692fdd76c621f","observation_id":"9c06d7c1-2261-437d-822b-998a08556cce","resolution":{"observed_at":"2026-08-11T18:04:22.569354Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:24.059276Z","title":null,"venue":null,"work_id":"f61804a0-f6f7-496b-b331-d05757212205","year":2023},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":45,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.574530Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:71e18361fbcf67d7892aa931c91b415f189f144eea998a940194ab232896b0a7","observation_id":"46b60b3a-2632-40c3-b2b8-a92ccd2d0f3a","resolution":{"observed_at":"2026-08-11T18:04:24.063738Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"4062.36245","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:23.097106Z","title":"Weckert, L","venue":null,"work_id":"3a963b0a-856f-4e5a-8265-27803ff3d328","year":2023},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":46,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.579421Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:dedb3948a07ae8f3ad4ed514a9554f89d6c53345d8e8b20f9f5d1243fdf5f891","observation_id":"d9617436-8488-47c4-be71-ff820b18c6a9","resolution":{"observed_at":"2026-08-11T18:04:23.105029Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"8115.36481","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:23.000692Z","title":null,"venue":null,"work_id":"5fb7d29d-04a6-4714-aa0d-0a940d6d8ecf","year":2024},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":47,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.584055Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:bbf6bda668101e21860a577aa68653c45edd0b81cc66edbb306d1d495dca3c4a","observation_id":"1fceb7f0-9f9c-4d18-97d6-d62c32eb9224","resolution":{"observed_at":"2026-08-11T18:04:23.008910Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1007/978-3-319-41279-5","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-13T11:03:48.094449Z","title":"URL https://doi.org/10.1007/978-3-319-41279-5\\_6","venue":null,"work_id":"1cab68a1-dbb0-44c4-b559-53a9faf40cda","year":null},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":223,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.459737Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:3afc00e85e249a2ea4e14c63f3cb125ebe97209d928e0277183d166f9dcac15f","observation_id":"6a7109e9-f4ef-406a-a317-1fdbece9f37e","resolution":{"observed_at":"2026-08-11T18:04:22.682425Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T18:04:22.493648Z","title":null,"venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment","version":3},"reference_index":2195,"source":"pdf_text","source_observed_at":"2026-08-11T18:04:22.493648Z"},"links":{"citing_paper":"/paper/2412.08308"},"observation_digest":"sha256:243c180dee64324e934589a4e9aca2ab5b80686049859c4108eddda85639663a","observation_id":"58053d4e-72f5-4493-add0-808857a6fdcb","resolution":{"observed_at":"2026-08-11T18:04:22.493648Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"paper":{"arxiv_id":"2412.08308","last_updated":"2025-04-14T13:53:03Z","latest_version":3,"primary_category":"cs.DC","snapshot_observed_at":"2026-08-18T20:13:14.367355Z","submitted_at":"2024-12-11T11:42:03Z","title":"Analyzing the Performance Portability of SYCL across CPUs, GPUs, and Hybrid Systems with SW Sequence Alignment"},"reference_resolution":{"displayed":47,"state_counts":{"malformed_identifier":2,"metadata_mismatch":3,"parse_uncertain":0,"unresolved":21,"verified_exact":12,"verified_fuzzy":9},"total_outbound_references":47},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"thesis":"As of 19 August 2026, this Paper Citation Record lists 47 of 47 outbound references and 0 inbound Pith citation observations for arXiv:2412.08308."}