{"as_of":"2026-08-19T15:41:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:133f0d5389ac1a1af5df844ce2c235e957c817b02bf946e2041e1a160deeae21","coverage":[{"denominator":35,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":35,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-10T19:33:37.691263Z","state":"measured"},{"denominator":36,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":36,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-19T06:32:44.657259+00:00","state":"measured"},{"denominator":1,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":1,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-05T20:33:59.260617Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"pith","source_observed_at":"2026-08-05T20:34:03.137214Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"cited_work":{"arxiv_id":"2501.09954","doi":null,"metadata_source":"pith","pith_arxiv_id":"2501.09954","snapshot_observed_at":"2026-08-05T20:34:03.137214Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","venue":"cs.LG","work_id":"e2749ae1-cfe2-40d7-be78-5a07d6a12445","year":2025},"citing_paper":{"arxiv_id":"2508.10303","last_updated":"2026-07-20T20:46:14Z","snapshot_observed_at":"2026-08-17T14:38:57.212628Z","submitted_at":"2025-08-14T03:19:34Z","title":"DiffAxE: Diffusion-driven Hardware Accelerator Generation and Design Space Exploration","version":2},"reference_index":20,"source":"arxiv_source","source_observed_at":"2026-08-05T20:33:59.260617Z"},"links":{"cited_paper":"/paper/2501.09954","citing_paper":"/paper/2508.10303"},"observation_digest":"sha256:d645b8d2f437d9adce1377706d118e0e1bcbc2ccfbeaf80d06d91a581ceebe5c","observation_id":"2c6f2bf1-d7f4-43e8-a0fe-91159a8cdef5","resolution":{"observed_at":"2026-08-05T20:34:03.184551Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/2501.09954/citation-record","integrity":"/paper/2501.09954/integrity","json":"/paper/2501.09954/citation-record.json","paper":"/paper/2501.09954"},"outbound":[{"citation":{"cited_paper":{"arxiv_id":"2403.05465","last_updated":"2024-03-26T18:43:35Z","snapshot_observed_at":"2026-08-19T09:06:40.369835Z","submitted_at":"2024-03-08T17:28:49Z","title":"Algorithm-Hardware Co-Design of Distribution-Aware Logarithmic-Posit Encodings for Efficient DNN Inference","version":2},"cited_work":{"arxiv_id":"2403.05465","doi":null,"metadata_source":"pith","pith_arxiv_id":"2403.05465","snapshot_observed_at":"2026-08-10T19:33:38.352009Z","title":"Algorithm-Hardware Co-Design of Distribution-Aware Logarithmic-Posit Encodings for Efficient DNN Inference","venue":"cs.AR","work_id":"7406db7e-a651-4f9e-8a88-502778f8d7d9","year":2024},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:36.850372Z"},"links":{"cited_paper":"/paper/2403.05465","citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:5436aeda4cf57d4da779df3835ade164b1632834da5c020569c5ff893d66abea","observation_id":"72e49753-fad8-4881-9ba9-aa2b594d0cc4","resolution":{"observed_at":"2026-08-10T19:33:38.382001Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:39.704161Z","title":"Maeri: Enabling flexible dataflow mapping over dnn accelerators via reconfigurable interconnects,","venue":null,"work_id":"13bc2b54-8aab-4c92-a47b-61c3f7fdb264","year":2018},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:36.860239Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:b61f225dfbe2be50094ecd930674bb2092740b1f01d6f802ce488ad401754224","observation_id":"958251d4-ffae-4ded-9882-60f38e26f37b","resolution":{"observed_at":"2026-08-10T19:33:39.712234Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2411.05282","last_updated":"2025-04-29T18:38:03Z","snapshot_observed_at":"2026-08-19T09:06:41.194869Z","submitted_at":"2024-11-08T02:25:45Z","title":"MicroScopiQ: Accelerating Foundational Models through Outlier-Aware Microscaling Quantization","version":4},"cited_work":{"arxiv_id":"2411.05282","doi":null,"metadata_source":"pith","pith_arxiv_id":"2411.05282","snapshot_observed_at":"2026-08-10T19:33:38.239807Z","title":"MicroScopiQ: Accelerating Foundational Models through Outlier-Aware Microscaling Quantization","venue":"cs.AR","work_id":"9c2f5e34-bc3c-41cc-978f-e241186dfaf7","year":2024},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:36.868151Z"},"links":{"cited_paper":"/paper/2411.05282","citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:d58f4abacbde7fd3143b0ca0b58526170826a0b35477a09ea1ad22e00b0d902f","observation_id":"306b0f65-2fc9-4a38-9c69-efae8dc54106","resolution":{"observed_at":"2026-08-10T19:33:38.278280Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:36.913605Z","title":"Dosa: Differentiable model-based one-loop search for dnn accelerators,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:36.913605Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:c90a90c18f443cebf92ca02cc187b46f01ece645eeb30653b1ff01ff0e9ad318","observation_id":"f382fe46-bccc-4bcb-a4d5-104ea4167f29","resolution":{"observed_at":"2026-08-10T19:33:36.913605Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2108.08295","last_updated":"2021-08-16T05:05:52Z","snapshot_observed_at":"2026-08-19T09:07:19.630638Z","submitted_at":"2021-08-16T05:05:52Z","title":"AIRCHITECT: Learning Custom Architecture Design and Mapping Space","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2108.08295","snapshot_observed_at":"2026-08-10T19:33:37.003716Z","title":"Airchitect: Learning custom architecture design and mapping space,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.003716Z"},"links":{"cited_paper":"/paper/2108.08295","citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:077d208a27a68978b35b83ed1a93d4015b1b77a05154681e7a5a98da66703dfa","observation_id":"ba5cd7df-3536-462d-95dd-70300ca752e0","resolution":{"observed_at":"2026-08-10T19:33:37.003716Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:39.673621Z","title":"Nvdla deep learning accelerator,","venue":null,"work_id":"86bdcd5c-b929-473e-9a9d-2ed5600b792e","year":2017},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.076495Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:17fe6377376fcb2466aac311aac9ab12843c9dbaf02701dcfff38bdda20e955e","observation_id":"6b90485d-0f0e-43a3-b7c0-26a60e7c5325","resolution":{"observed_at":"2026-08-10T19:33:39.681348Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:39.566459Z","title":"Eyeriss: An energy- efficient reconfigurable accelerator for deep convolutional neural net- works,","venue":null,"work_id":"06993c78-4c86-47df-940d-e19aa3f97e6e","year":2016},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.128112Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:b1e722be5c5de156b0163099f307b63f56a3648ad1e94e02e6622ddd75797e5f","observation_id":"f45bc254-18b1-4c77-bd50-f2480d55d9f8","resolution":{"observed_at":"2026-08-10T19:33:39.635297Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:39.483354Z","title":"Shidiannao: Shifting vision processing closer to the sensor,","venue":null,"work_id":"32da7170-9094-4402-9a79-777dd688eada","year":2015},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.152126Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:babfe017fa16b15349df0e8fae08b0c587fc964fb5b33457a11449225808d78e","observation_id":"29a83901-9d5f-46c4-aa3e-44ba4e7b1dc2","resolution":{"observed_at":"2026-08-10T19:33:39.522659Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:37.161185Z","title":"Imagenet: A large-scale hierarchical image database,","venue":null,"work_id":null,"year":2009},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.161185Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:86d14c1577486c2db7d91fa7a45b984b300564649f433ddc8f42166b9295bd5e","observation_id":"82e3e79e-91f3-4367-8038-eff366639ecf","resolution":{"observed_at":"2026-08-10T19:33:37.161185Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:37.170370Z","title":"Unified perceptual parsing for scene understanding,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.170370Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:806cd8186939640d3b4d9c828a384203b946e19c1418b365e252f1223d0f8775","observation_id":"dde3529d-1e1f-42db-8a1b-f1d292acb3ba","resolution":{"observed_at":"2026-08-10T19:33:37.170370Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:39.402837Z","title":"Learn- ing a continuous and reconstructible latent space for hardware accelerator design,","venue":null,"work_id":"68ea8162-5451-4e2a-9a0f-d4f659b089f9","year":2022},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.178028Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:8407a7934f1a114e3d079ba5cd4f95986b77213908b8ce292beddfa3682f0537","observation_id":"5ef4f350-b04c-4dea-a773-e1ccb0c4cf62","resolution":{"observed_at":"2026-08-10T19:33:39.414484Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:37.189512Z","title":"Confuciux: Autonomous hardware resource assignment for dnn accelerators using reinforcement learning,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.189512Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:e727297fbcc17567f23efbec4660de40ef782f13fbbf005e065b72ae8de6c60c","observation_id":"a64ac6fd-6da4-49f7-b386-1e3002c36a8d","resolution":{"observed_at":"2026-08-10T19:33:37.189512Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:39.329018Z","title":"Gamma: Automating the hw mapping of dnn models on accelerators via genetic algorithm,","venue":null,"work_id":"7d6dc669-4491-48c1-b862-a0bf8f11eb5d","year":2020},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.198241Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:b04f6f75811a812c0d40a83b2b057a8cd9c1b189b131ccb877b55578f693aa62","observation_id":"8baffe04-c066-4511-8c6d-6c1cd4ecd2d0","resolution":{"observed_at":"2026-08-10T19:33:39.339772Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:39.265281Z","title":"Digamma: Domain- aware genetic algorithm for hw-mapping co-optimization for dnn accel- erators,","venue":null,"work_id":"4e4e0176-62c4-4363-bfa1-9e7a2d8fde41","year":2022},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.214562Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:5b4033d4e88dce29791a3eb2a8e1cb51c8cec7942623fadf9325335d96e0b01e","observation_id":"7c9b2a5a-cae5-40bf-8b7b-560a2905c5a8","resolution":{"observed_at":"2026-08-10T19:33:39.304519Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:39.141494Z","title":"Hasco: Towards agile hardware and software co-design for tensor computation,","venue":null,"work_id":"8a2f2c9d-42ff-409c-93f1-2e097fa8e9b5","year":2021},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.302812Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:384c732015855eaebfa1ef3f8ff33d38f3b6b69a6f3c2fce8b904d9187f3fe25","observation_id":"c5411dfc-fe93-4a63-9f3e-7859c1f5581f","resolution":{"observed_at":"2026-08-10T19:33:39.197567Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:39.056520Z","title":"Gandse: Generative adversarial network-based design space exploration for neural network accelerator design,","venue":null,"work_id":"186aa047-b4fc-4225-8ba7-2ec7dcc653df","year":2023},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.330761Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:fec41349b5ddf6085e8ae1af50595cf7077a01c7b35859328b8edeb0b76071c9","observation_id":"35af7329-1338-4fd9-8275-9a0adfd87cbb","resolution":{"observed_at":"2026-08-10T19:33:39.099095Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:38.944004Z","title":"A systematic methodology for characterizing scalability of dnn accelerators using scale-sim,","venue":null,"work_id":"a16d8969-751e-408d-b93e-5359e30996d3","year":2020},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.374067Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:7d0c6441994d0b59df7fb3da4cbc0131d1a0e6b35087acc6e8e8bb16ff3ee767","observation_id":"131c0ede-3bf9-4aa3-8dc0-843ff388c331","resolution":{"observed_at":"2026-08-10T19:33:39.002582Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:38.916119Z","title":"Ntrans- net: A multi-scale neutrosophic-uncertainty guided transformer network for indoor depth completion,","venue":null,"work_id":"6fa831fa-9e47-47e9-a352-e04d497b918c","year":2023},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.408354Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:6931e29d7b45b4d65e0fc16fa18f029dca28e1a1f05d455408096a3882f8931e","observation_id":"a8fbe63b-3d97-45b4-af17-40f607414904","resolution":{"observed_at":"2026-08-10T19:33:38.924752Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:38.884306Z","title":"MAESTRO: A data-centric approach to understand reuse, performance, and hardware cost of DNN mappings,","venue":null,"work_id":"58378768-697a-4720-a300-e3bcb52c39c3","year":2020},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.449730Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:21322b1fac1bd9bd6a446ad65d4a793cd26d0d9730ad8c4d6df7c6631e529097","observation_id":"2958999a-79da-4fe8-a9ba-ec535a54bfd1","resolution":{"observed_at":"2026-08-10T19:33:38.893292Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:38.829479Z","title":"A systematic methodology for characterizing scalability of dnn accelerators using scale-sim,","venue":null,"work_id":"94e4a611-af17-4aa4-84cd-bc5932c7e669","year":2020},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.493222Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:bda1ff46727980913fef3afea274aa432b7625225550e9bbb10c204c9f1f5648","observation_id":"f342c4ba-af77-4214-aa0d-c3c0495256c0","resolution":{"observed_at":"2026-08-10T19:33:38.847946Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:38.782716Z","title":"Contrastive quant: quantization makes stronger contrastive learning,","venue":null,"work_id":"38ed6b66-63df-449d-8ee4-cfd20416bbd6","year":2022},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.519062Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:dd508be9ef5817f4c120dab0b72ae844df8b02c07b88ec2b25f5f836216a517d","observation_id":"29fa0b57-cb4f-414f-bebc-fd1738319230","resolution":{"observed_at":"2026-08-10T19:33:38.798195Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:38.737340Z","title":"Synergistic self- supervised and quantization learning,","venue":null,"work_id":"a1761940-b2a9-48a1-a405-b670f0fca712","year":2022},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.546272Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:f5563232943cc777724d7667d81ad09dc25ba3c4ea7fd434fc10ba739b80a246","observation_id":"ab94501e-bfda-476a-8057-1bd2cb190c02","resolution":{"observed_at":"2026-08-10T19:33:38.754552Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:38.713391Z","title":"Jumping through local minima: Quantization in the loss landscape of vision transformers,","venue":null,"work_id":"ec361b4f-2352-4531-9dbc-0fb7ce9dc665","year":2023},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.578976Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:8d52e39cbe2fe60b8bb5bc0a8753a90b98a44799ca26efe912d70a331e727788","observation_id":"5000218b-2e72-4b75-8bb3-ea0de7603fb2","resolution":{"observed_at":"2026-08-10T19:33:38.720048Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2407.05266","last_updated":"2024-09-09T00:08:36Z","snapshot_observed_at":"2026-08-16T13:36:29.174360Z","submitted_at":"2024-07-07T05:39:25Z","title":"CLAMP-ViT: Contrastive Data-Free Learning for Adaptive Post-Training Quantization of ViTs","version":2},"cited_work":{"arxiv_id":"2407.05266","doi":null,"metadata_source":"pith","pith_arxiv_id":"2407.05266","snapshot_observed_at":"2026-08-10T19:33:38.052186Z","title":"CLAMP-ViT: Contrastive Data-Free Learning for Adaptive Post-Training Quantization of ViTs","venue":"cs.CV","work_id":"11e0407c-eb97-4748-9472-4bdf1e34dd1a","year":2024},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.595420Z"},"links":{"cited_paper":"/paper/2407.05266","citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:9bd95169aaca2f3687c93d0e379de923662c4c4218c5785b30a08006aa6bdb6a","observation_id":"9840c8e9-7190-4a3e-be97-03f06b22f6a1","resolution":{"observed_at":"2026-08-10T19:33:38.062825Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:38.690425Z","title":"Positive–negative equal contrastive loss for semantic segmentation,","venue":null,"work_id":"23651618-2f6c-4920-8aed-46c81ccd16c2","year":2023},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.610600Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:8b797dd202eecdc6e2fbb53672a9f9ca9b5cb269aadfd72884f30e431ddbf452","observation_id":"6ea39518-7e3e-4c6b-92d8-4dc13536c97a","resolution":{"observed_at":"2026-08-10T19:33:38.697818Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:38.664416Z","title":"Targeted supervised contrastive learning for long-tailed recognition,","venue":null,"work_id":"be0b16ab-5baf-4338-a5ad-22db9da76d7d","year":2022},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.622150Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:82531ffc6d5938f62a2fd1cce8b8e3ec4151e42ce186c1ca9d60dc556509730b","observation_id":"9c20ead8-c65a-4308-a0a2-cdfb871dfe88","resolution":{"observed_at":"2026-08-10T19:33:38.674852Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:37.633401Z","title":"A meta-analysis of overfitting in machine learning,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.633401Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:3f7d291ab3750fa071b4ff28764313488876bb4754fb38e1ba006a951efb3979","observation_id":"b62c5b9e-5d9b-4448-8711-969368a13226","resolution":{"observed_at":"2026-08-10T19:33:37.633401Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:37.640838Z","title":"Attention is all you need,","venue":null,"work_id":null,"year":2017},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.640838Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:d823d596278ae5f7cf1cd7bcb13ae03b6528b2d036869f0b414ed220c54330f0","observation_id":"07da979e-5004-4e15-a378-18be019dfc21","resolution":{"observed_at":"2026-08-10T19:33:37.640838Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:38.608697Z","title":"Automatic chemical design using a data-driven continuous representation of molecules,","venue":null,"work_id":"42263773-ee7f-408c-b2ac-1828432fe812","year":2018},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.647283Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:be7f62226f92b0b95d5d854d7a56b1df910e39c3639df5e725c9c74d3c388678","observation_id":"6741481b-5b7e-40d6-aa0f-dcdc33d67495","resolution":{"observed_at":"2026-08-10T19:33:38.622011Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2302.13540","last_updated":"2023-02-27T06:35:03Z","snapshot_observed_at":"2026-08-16T15:52:32.847801Z","submitted_at":"2023-02-27T06:35:03Z","title":"OccDepth: A Depth-Aware Method for 3D Semantic Scene Completion","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2302.13540","snapshot_observed_at":"2026-08-10T19:33:37.653147Z","title":"Occdepth: A depth-aware method for 3d semantic scene completion,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.653147Z"},"links":{"cited_paper":"/paper/2302.13540","citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:dfa54dba5c2ea6280532bbe1a016f5ac9d0d57fcc6c46e68ba0a1f1abe772f22","observation_id":"7a67e5d9-5d80-4c3a-a05f-9487ee4ed26d","resolution":{"observed_at":"2026-08-10T19:33:37.653147Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:37.659508Z","title":"Generalized focal loss: Learning qualified and distributed bounding boxes for dense object detection,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.659508Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:8c5dd7279ed4d373bc92c307a9b542e3171ddccfdbfbfd961312f1a390486619","observation_id":"2c62f214-c846-49da-a80d-9d9cd91d7711","resolution":{"observed_at":"2026-08-10T19:33:37.659508Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:37.668651Z","title":"Deep residual learning for image recognition,","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.668651Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:cd00de1f27cebb65ebb733bb43e1a2deb32f3a7b4137c635c100c99cad0d7790","observation_id":"85ee32fe-07ca-45a1-8e89-302b7fd29881","resolution":{"observed_at":"2026-08-10T19:33:37.668651Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2307.09288","last_updated":"2023-07-19T17:08:59Z","snapshot_observed_at":"2026-08-07T12:56:43.323460Z","submitted_at":"2023-07-18T14:31:57Z","title":"Llama 2: Open Foundation and Fine-Tuned Chat Models","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2307.09288","snapshot_observed_at":"2026-08-10T19:33:37.675761Z","title":"Llama 2: Open foundation and fine-tuned chat models,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.675761Z"},"links":{"cited_paper":"/paper/2307.09288","citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:c0e9ea6c7e75cc4d0a843ec766bccf8bcb764ce0a75e8a9b82925c28fa39f0fa","observation_id":"1f684d8e-5dc3-46fb-b6fa-2b2c9018ef7f","resolution":{"observed_at":"2026-08-10T19:33:37.675761Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2407.21783","last_updated":"2024-11-23T23:27:33Z","snapshot_observed_at":"2026-08-13T17:20:44.002518Z","submitted_at":"2024-07-31T17:54:27Z","title":"The Llama 3 Herd of Models","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2407.21783","snapshot_observed_at":"2026-08-10T19:33:37.682431Z","title":"The llama 3 herd of models,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.682431Z"},"links":{"cited_paper":"/paper/2407.21783","citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:922c9655b058352588e4242ec492a3030fe54d7fe75e00ff444729981ee6a5a0","observation_id":"d92b25d0-4abc-40c9-ab70-64c0483b62bc","resolution":{"observed_at":"2026-08-10T19:33:37.682431Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:33:37.691263Z","title":"Mind mappings: Enabling efficient algorithm-accelerator mapping space search,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-10T19:33:37.691263Z"},"links":{"citing_paper":"/paper/2501.09954"},"observation_digest":"sha256:0dc0d35efcda719cdd1249e5c0571a6a0427b5071e7de94a99fd0ac865fe6879","observation_id":"7951d3ef-09e0-47b6-9313-91fe49119971","resolution":{"observed_at":"2026-08-10T19:33:37.691263Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"paper":{"arxiv_id":"2501.09954","last_updated":"2025-01-17T04:57:42Z","latest_version":1,"primary_category":"cs.LG","snapshot_observed_at":"2026-08-19T09:06:52.709971Z","submitted_at":"2025-01-17T04:57:42Z","title":"AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations"},"reference_resolution":{"displayed":35,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":13,"verified_exact":3,"verified_fuzzy":19},"total_outbound_references":35},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-19T06:32:44.657259+00:00","source":"crossref"},{"observed_at":"2026-08-19T06:32:39.956319+00:00","source":"retraction_watch"}],"thesis":"As of 19 August 2026, this Paper Citation Record lists 35 of 35 outbound references and 1 inbound Pith citation observation for arXiv:2501.09954."}