{"as_of":"2026-08-18T05:37:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:db66a0b4181ac6752a36c2a35c6eef5d022b9148b694b94d23c93b4fa422156f","coverage":[{"denominator":26,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":26,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-10T19:19:21.626523Z","state":"measured"},{"denominator":28,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":28,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-17T06:30:58.91139+00:00","state":"measured"},{"denominator":2,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":2,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-15T22:29:22.922361Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"pith","source_observed_at":"2026-08-05T23:30:35.522871Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2501.10301","snapshot_observed_at":"2026-08-15T22:29:22.922361Z","title":"AraXL: A physically scalable, ultra-wide RISC-V vector processor design for fast and efficient computation on long vectors,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2505.07112","last_updated":"2025-05-30T10:34:35Z","snapshot_observed_at":"2026-08-15T22:22:23.969173Z","submitted_at":"2025-05-11T20:45:03Z","title":"Efficient Implementation of RISC-V Vector Permutation Instructions","version":2},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-15T22:29:22.922361Z"},"links":{"cited_paper":"/paper/2501.10301","citing_paper":"/paper/2505.07112"},"observation_digest":"sha256:c6adc429a80e68c04bd60dbf7730594b0a01cd8da9036c4f32c8442e1b51318e","observation_id":"ba6a679b-efd9-4f70-83ea-c62e3053887f","resolution":{"observed_at":"2026-08-15T22:29:22.922361Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"cited_work":{"arxiv_id":"2501.10301","doi":null,"metadata_source":"pith","pith_arxiv_id":"2501.10301","snapshot_observed_at":"2026-08-05T23:30:35.522871Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","venue":"cs.AR","work_id":"bef8c658-1be9-4e83-8f8d-3ebf35b6b7ed","year":2025},"citing_paper":{"arxiv_id":"2508.07110","last_updated":"2025-08-09T21:42:44Z","snapshot_observed_at":"2026-08-13T15:02:04.489909Z","submitted_at":"2025-08-09T21:42:44Z","title":"Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes","version":1},"reference_index":4,"source":"arxiv_source","source_observed_at":"2026-08-05T23:30:35.423354Z"},"links":{"cited_paper":"/paper/2501.10301","citing_paper":"/paper/2508.07110"},"observation_digest":"sha256:2bcce504becab41125f6a2adb4097418f104486a7bbf0f6f732dc21b9aa32180","observation_id":"3c20c367-a2db-4783-abf9-a29e97a0c398","resolution":{"observed_at":"2026-08-05T23:30:35.526534Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/2501.10301/citation-record","integrity":"/paper/2501.10301/integrity","json":"/paper/2501.10301/citation-record.json","paper":"/paper/2501.10301"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.918985Z","title":"Scaling the power wall: A path to exascale,","venue":null,"work_id":"f0d8dafc-b310-4434-8ee6-c5221b12fb78","year":2014},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.525890Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:44392877b214c91ff07fae91f73d4c3bd3a4ea73c9b478b4781f9c884c352267","observation_id":"aa3c4e9a-7a82-496c-ac92-09312ee640fa","resolution":{"observed_at":"2026-08-10T19:19:21.921059Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.913142Z","title":"The environmental cost of high performance computing system simulation,","venue":null,"work_id":"4d7d5ce6-b3cf-4ec5-a8b7-d433d58d7b9d","year":2024},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.528998Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:dad09f8fc056f85b7b507d0a8666ad016dd8b90763f6ff3a3cf17a74b3b13cf9","observation_id":"02720f6a-024d-4c06-9781-0d3ded6bc6f8","resolution":{"observed_at":"2026-08-10T19:19:21.915289Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.907251Z","title":"The CRAY-1 computer system,","venue":null,"work_id":"72ef326d-5a07-4c69-ab31-1bb1e13c982b","year":1978},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.531778Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:aed2fefeb58aaa7aa0bba0968c709ced406b6c75673ee738ed4400aae63b1dfd","observation_id":"ef3f478e-9cd3-442b-930c-898cb895621e","resolution":{"observed_at":"2026-08-10T19:19:21.909443Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.900804Z","title":"A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures,","venue":null,"work_id":"6548e957-d3da-4930-9b67-620fb4bc86fc","year":2020},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.534699Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:94d5d394a85bbc626318caedf3c4f726fcbc1ee3f95be2a2d1658d34ce5c0816","observation_id":"dec5db89-35c0-4301-81be-696812812032","resolution":{"observed_at":"2026-08-10T19:19:21.903155Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.893751Z","title":"Challenges and oppor- tunities in the co-design of convolutions and RISC-V vector processors,","venue":null,"work_id":"abb9a86d-227a-47b7-bc09-48a5487638ac","year":2023},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.538350Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:9c3c73ad3cd01907a2c32d59a5ca1ca61016922613ee4018974a3cde9c6dabb2","observation_id":"82f88328-d0a3-46be-a789-0a4f74fa0418","resolution":{"observed_at":"2026-08-10T19:19:21.896800Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.887466Z","title":"Short Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-V,","venue":null,"work_id":"b204a531-ffdb-43a1-a3ab-d1ba467179ea","year":2023},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.541730Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:77dc6861ec590c225c0ee19ca997f3468e7f2566d81f5dc8983b3acd325b2d09","observation_id":"03cd282e-3d82-4fd3-82fc-d2bd7d511fa5","resolution":{"observed_at":"2026-08-10T19:19:21.889968Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.881239Z","title":"Efficiently running SpMV on long vector architectures,","venue":null,"work_id":"5ef97016-b76a-42e9-9591-dc57aa30af43","year":2021},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.548461Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:b9783a86a9c0a76b40966911cfbee87d736337c6701079c0d397958462ad2510","observation_id":"a7041f1c-9f7f-46a7-9eb0-e6821947c890","resolution":{"observed_at":"2026-08-10T19:19:21.883650Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.874030Z","title":"HPCG on long-vector architectures: Evaluation and optimiza- tion on NEC SX-Aurora and RISC-V,","venue":null,"work_id":"aa5fd870-d13a-4864-9439-debc01a81e38","year":2023},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.551264Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:db83ce0e059d201961dcfa3701bdfb0fbbe5f22d54bb2fc07eaa0b000d09a241","observation_id":"74d88d0f-3f93-4e73-9097-15f8a22dfe05","resolution":{"observed_at":"2026-08-10T19:19:21.877130Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.867147Z","title":"AWS Graviton - Getting started,","venue":null,"work_id":"edec388a-4c69-4e66-8020-8eae426b2fcb","year":2024},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.553856Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:b32c8acfd102841670d56e4b49bd8e5c6d52ff0a54c9d7007677d65fcea9787c","observation_id":"0db4ba3f-7836-4a79-9b70-70328fea2a2a","resolution":{"observed_at":"2026-08-10T19:19:21.869987Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.860635Z","title":"Supercomputer Fugaku CPU A64FX realizing high performance, high-density packaging, and low power consumption,","venue":null,"work_id":"ea992c6d-932e-40b4-ae1b-212aa2d7b402","year":2020},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.558825Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:9dde3e74154f321d400efe80a944d124982fd3f3d898dab506989f4876751d16","observation_id":"9816e850-fb36-4365-8340-01bc5d9cf504","resolution":{"observed_at":"2026-08-10T19:19:21.863231Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.853724Z","title":"Vicuna: A timing-predictable RISC-V vector coprocessor for scalable parallel computation,","venue":null,"work_id":"10bbe9fa-2c2f-40e3-945d-a4dbf8d8d649","year":2021},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.562580Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:da0f6f67e168d3ef33e57f626068eb81e93af4221ef22db33a660b4899308b20","observation_id":"c6a9d4a6-24ba-49c7-acf9-a21a665c0af7","resolution":{"observed_at":"2026-08-10T19:19:21.856521Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.847787Z","title":"Vitruvius+: An area-efficient RISC-V decoupled vector coprocessor for high performance computing applications,","venue":null,"work_id":"6f021519-1724-4a9e-b9fb-d39ecf8a5bce","year":2023},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.565124Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:eb508a65bae43097e5f1e4e89522c2ef8cf1b74a4cc3abd4a94d1fc9bbb58685","observation_id":"f8930914-dfd1-400f-99b9-c259edaff00b","resolution":{"observed_at":"2026-08-10T19:19:21.849995Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.841755Z","title":"Ara2: Exploring single- and multi-core vector process- ing with an efficient RVV 1.0 compliant open-source processor,","venue":null,"work_id":"35994459-7e30-4c69-bf04-dde22d2feed9","year":2024},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.567532Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:8a3d862cfddb17f7e90f4e253d3a98550dd7586f6cdd2842063e4ba9b4e560ac","observation_id":"1aef1815-dfcc-40c5-88c9-25aae38c4db5","resolution":{"observed_at":"2026-08-10T19:19:21.844102Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.835827Z","title":"[Online]","venue":null,"work_id":"d1934d5f-2715-43f9-acef-1db1ec500b04","year":2022},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.572901Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:35df4f559d50322033545dc14fe1a6d12fe806a74164e57c40f39c70e9a97965","observation_id":"45cb3535-bd56-41f3-948e-76a6bf485606","resolution":{"observed_at":"2026-08-10T19:19:21.837908Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.829615Z","title":"P870 high-performance RISC-V processor,","venue":null,"work_id":"b6b3ea61-7c3b-4ed1-8fa0-757ef42a6811","year":2023},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.576667Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:f42aba441fd58be400fab5a4b2d11377f45258c226b901ad508cd9c2cdfc0e3f","observation_id":"aaa98d45-5095-4c7f-82f8-84b4a4960004","resolution":{"observed_at":"2026-08-10T19:19:21.832088Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.823068Z","title":"AndesCore™ NX27V Processor,","venue":null,"work_id":"c47fc13d-7666-47c9-bd2b-bcc36e1fde1d","year":2024},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.586976Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:a20fe039a1993784fbbabd7194914f46500da771627a0b3715347f94505018b3","observation_id":"bcf6babe-22dc-43c5-bef8-3cc8b45b32c2","resolution":{"observed_at":"2026-08-10T19:19:21.825473Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.816550Z","title":"SiFive announces differentiated solutions for gen- erative AI and ML applications leading RISC-V into a new era of high-performance innovation,","venue":null,"work_id":"bb11768f-71ce-4378-8373-4cc71f8eee73","year":2024},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.605741Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:ba876a929db05887f5017a7e01b4d891f20fce58fd82d70ea2fc3ac7786c877f","observation_id":"f9267513-1035-4bee-a45d-0b46490ecf3d","resolution":{"observed_at":"2026-08-10T19:19:21.818963Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.810302Z","title":"[Online]","venue":null,"work_id":"c8977c2d-64d7-4a87-a406-1600bd6bf794","year":2022},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.608007Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:d55204872ea4cff5c6b4956af5eff068c3f7d7164bd4243818d210c9202b17d6","observation_id":"72392d89-f60d-44d6-ba35-093df027ea93","resolution":{"observed_at":"2026-08-10T19:19:21.812557Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.610229Z","title":"Spatz: Clustering compact RISC-V-based vector units to maximize computing efficiency,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.610229Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:cdc656cf79b31aad6757a1908b95426d67e5502c6927cb6b810ea35f71721757","observation_id":"a7254c76-3e83-425d-bc8b-613560c76a27","resolution":{"observed_at":"2026-08-10T19:19:21.610229Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.803064Z","title":"Arrow: A RISC-V vector accelerator for machine learning inference,","venue":null,"work_id":"da9670bc-4630-4bda-bded-dedd9c522691","year":2021},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.612378Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:b63e364b5a5e8a1944189de80163ceeef39db0b69561c4e5d04ee475918b6738","observation_id":"31d158c2-3268-480a-98e0-5a66835ad438","resolution":{"observed_at":"2026-08-10T19:19:21.805705Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.795897Z","title":"AndesCore™ AX45MPV,","venue":null,"work_id":"386ea60e-c22f-4366-824f-459fdb8f429b","year":2024},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.615480Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:4dc6eac8400b4b45fb43950d10f4be73171047ea257afee07e25b4e79484d52d","observation_id":"d6d2ed20-c582-4413-a424-d500b3c4db04","resolution":{"observed_at":"2026-08-10T19:19:21.798200Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.788998Z","title":"Semidynamics vector unit,","venue":null,"work_id":"8628ecf5-cac8-439b-b418-f89bf48ad2bc","year":null},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.617712Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:6a91ad3e309d167c0a7f7fba4a02c81db099017b38841942bf6596e9074ec03f","observation_id":"c50ca31a-da96-4195-b7e5-ea8e6785aeb5","resolution":{"observed_at":"2026-08-10T19:19:21.791183Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.775232Z","title":"NEC SX-Aurora TSUBASA architecture,","venue":null,"work_id":"dd1cbd2b-fdea-43fd-8714-bc9b294e413b","year":2024},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.622303Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:984d8ff7b34aab009e551ba12f9511ed0a2502ac9e4dee1f72f7ac45f84fd651","observation_id":"420f456f-5579-4cb1-97da-4b3ac9e611cb","resolution":{"observed_at":"2026-08-10T19:19:21.777477Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.768993Z","title":"The Llama 3 herd of models,","venue":null,"work_id":"32842015-a77b-4f90-8a91-f1184fd8a5a3","year":2025},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.624409Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:a206141b7760f7d038624f5825dd8d7e5347e21dd348fadc9ab66275161c7107","observation_id":"acf185be-32a6-4817-b960-b0bf4ab388df","resolution":{"observed_at":"2026-08-10T19:19:21.771043Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.759223Z","title":"The cost of application-class processing: Energy and performance analysis of a Linux-ready 1.7-GHz 64-Bit RISC-V core in 22-nm FDSOI technology,","venue":null,"work_id":"1e8e3909-6f46-455f-be8b-3b3c4c52d684","year":2019},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.626523Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:21a2f33c0131f753e17db6a9612ac656579881c4c54f0c113c424f009a1b05ec","observation_id":"2c4e9603-5566-478e-9a29-e7252ea07b30","resolution":{"observed_at":"2026-08-10T19:19:21.764176Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T19:19:21.781901Z","title":"Available: https://semidynamics.com/en/technology/ vector-unit","venue":null,"work_id":"2d4bdea4-fbc0-487e-b542-1e75b559d1f1","year":null},"citing_paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors","version":1},"reference_index":2024,"source":"pdf_text","source_observed_at":"2026-08-10T19:19:21.620014Z"},"links":{"citing_paper":"/paper/2501.10301"},"observation_digest":"sha256:32dd45671f31a569e002047ea075949fb9a64a0c6d8715570ec510aaa8f1515b","observation_id":"a6632c8f-ebf0-4ebf-864c-888945c271a0","resolution":{"observed_at":"2026-08-10T19:19:21.784588Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2501.10301","last_updated":"2025-01-17T16:56:00Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-10T19:12:30.838529Z","submitted_at":"2025-01-17T16:56:00Z","title":"AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors"},"reference_resolution":{"displayed":26,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":1,"verified_exact":0,"verified_fuzzy":25},"total_outbound_references":26},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"thesis":"As of 18 August 2026, this Paper Citation Record lists 26 of 26 outbound references and 2 inbound Pith citation observations for arXiv:2501.10301."}