{"as_of":"2026-08-08T19:17:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:3e5e191845751b336640f28f48f06562519d60ee2c16e2ad5287b3b6983439a9","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":3,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":3,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-08T06:32:00.761636+00:00","state":"measured"},{"denominator":3,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":3,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-07T23:14:10.222152Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"pith","source_observed_at":"2026-08-06T15:51:17.775716Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2502.01681","last_updated":"2025-05-20T08:17:48Z","snapshot_observed_at":"2026-07-06T20:30:31.588538Z","submitted_at":"2025-02-02T05:25:34Z","title":"DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2502.01681","snapshot_observed_at":"2026-08-07T23:14:10.222152Z","title":"Deepgate4: Efficient and effective representation learning for circuit design at scale","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2502.08949","last_updated":"2025-05-19T17:23:05Z","snapshot_observed_at":"2026-08-07T23:05:06.971916Z","submitted_at":"2025-02-13T04:15:20Z","title":"DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining","version":2},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-07T23:14:10.222152Z"},"links":{"cited_paper":"/paper/2502.01681","citing_paper":"/paper/2502.08949"},"observation_digest":"sha256:ac9aefb6cea5981dc7c6ef3e9746c386c684a53381a614a4ea498818120fba48","observation_id":"e282a060-3555-43dd-b6a8-56e261e3b454","resolution":{"observed_at":"2026-08-07T23:14:10.222152Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2502.01681","last_updated":"2025-05-20T08:17:48Z","snapshot_observed_at":"2026-07-06T20:30:31.588538Z","submitted_at":"2025-02-02T05:25:34Z","title":"DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale","version":3},"cited_work":{"arxiv_id":"2502.01681","doi":null,"metadata_source":"pith","pith_arxiv_id":"2502.01681","snapshot_observed_at":"2026-08-06T15:51:17.775716Z","title":"DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale","venue":"cs.LG","work_id":"28b73e5e-d173-4859-a00b-9b8bb7d91602","year":2025},"citing_paper":{"arxiv_id":"2507.19525","last_updated":"2025-07-20T05:46:32Z","snapshot_observed_at":"2026-08-07T01:10:18.257426Z","submitted_at":"2025-07-20T05:46:32Z","title":"MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-06T15:51:16.994747Z"},"links":{"cited_paper":"/paper/2502.01681","citing_paper":"/paper/2507.19525"},"observation_digest":"sha256:843ebe6b8140944bd6a866317bbede179998cf229238fa4f8b90bd4a0f2e1eb6","observation_id":"bf6167ff-96be-4d75-88cb-07bd972987c8","resolution":{"observed_at":"2026-08-06T15:51:17.782618Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2502.01681","last_updated":"2025-05-20T08:17:48Z","snapshot_observed_at":"2026-07-06T20:30:31.588538Z","submitted_at":"2025-02-02T05:25:34Z","title":"DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2502.01681","snapshot_observed_at":"2026-08-04T07:53:41.236789Z","title":"DeepGate4: Efficient and effective representation learning for circuit design at scale,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.23472","last_updated":"2026-07-18T05:51:55Z","snapshot_observed_at":"2026-08-05T12:31:43.308424Z","submitted_at":"2025-10-27T16:10:32Z","title":"BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement","version":2},"reference_index":90,"source":"pdf_text","source_observed_at":"2026-08-04T07:53:41.236789Z"},"links":{"cited_paper":"/paper/2502.01681","citing_paper":"/paper/2510.23472"},"observation_digest":"sha256:350a95448f606f289de8641168eeb7f0b53540d0a4a7e9def3bc810caa74e72d","observation_id":"c1c0cbbc-3ade-4db2-be4f-62cc71467bd2","resolution":{"observed_at":"2026-08-04T07:53:41.236789Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"links":{"evidence":"/evidence","html":"/paper/2502.01681/citation-record","integrity":"/paper/2502.01681/integrity","json":"/paper/2502.01681/citation-record.json","paper":"/paper/2502.01681"},"outbound":[],"paper":{"arxiv_id":"2502.01681","last_updated":"2025-05-20T08:17:48Z","latest_version":3,"primary_category":"cs.LG","snapshot_observed_at":"2026-07-06T20:30:31.588538Z","submitted_at":"2025-02-02T05:25:34Z","title":"DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"thesis":"As of 8 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 3 inbound Pith citation observations for arXiv:2502.01681."}