{"as_of":"2026-08-21T12:46:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:01497d52cefff8ec3da77efb2e53748f195a2f85950fe8930ce182111081f545","coverage":[{"denominator":88,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":88,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-08T23:48:51.824119Z","state":"measured"},{"denominator":88,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":88,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-21T06:32:19.484+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2502.04063/citation-record","integrity":"/paper/2502.04063/integrity","json":"/paper/2502.04063/citation-record.json","paper":"/paper/2502.04063"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.358767Z","title":"Cranelift Code Generator","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.358767Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:61e4f1883abdb88c13aee893b301274bb02f5ed56e89408b18cc98c161856682","observation_id":"1867321e-44fa-4c6a-bc03-0d3cc2974d9f","resolution":{"observed_at":"2026-08-08T23:48:51.358767Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.364469Z","title":"The European Processor Initiative Accelerator Processor Stream","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.364469Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:8d51461917f6504d219e5a66e6e22c13d6dd8540a3eca76ee1e1bbae814b20f5","observation_id":"a1f6a353-7011-4d68-910f-3c1352ba578a","resolution":{"observed_at":"2026-08-08T23:48:51.364469Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.369814Z","title":"GCC, the GNU Compiler Collection - GNU Project","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.369814Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:dcc0b13c428defde53593bf101b7e022f7f93877adef2e118f8c9e2d88ccc770","observation_id":"fa11a38d-8996-4053-b11d-ab133252820a","resolution":{"observed_at":"2026-08-08T23:48:51.369814Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.387226Z","title":"High performance RISC-V CPUs","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.387226Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:f4391b00ca3abaddfde2f8206b551dea3acba990d43cfb552edbcb55a7aa1a7c","observation_id":"15eade31-254d-4d0f-9048-823af244baf6","resolution":{"observed_at":"2026-08-08T23:48:51.387226Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.392287Z","title":"Intel oneDNN","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.392287Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:39779e67c187ebd418294be0132daf96b36ea03eef62c797aaa03376afc62228","observation_id":"5b4c310e-1a8b-4788-b14e-81b40797b691","resolution":{"observed_at":"2026-08-08T23:48:51.392287Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.397575Z","title":"LLVM for PULP Platform Projects, Snitch RISC-V ISA Exten- sion Support, PULP Project","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.397575Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:7e2c921ee6a14fe72d66fdf29c1879dececad1fd6872a9333c29eb9aa0b7e4ec","observation_id":"2925e37f-5eef-4f99-a2b4-ef5d2fe662b4","resolution":{"observed_at":"2026-08-08T23:48:51.397575Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.403365Z","title":"MLIR Documentation: linalg Dialect","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.403365Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:f2e841c32a71df3349c9bcb6e8cfb15a58900964251ca7053cf472369c511509","observation_id":"faefd990-b94c-408d-b335-f59c3060a1a7","resolution":{"observed_at":"2026-08-08T23:48:51.403365Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.408200Z","title":"NVIDIA cuDNN","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.408200Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:5ee60f3b928344efb3d2179866653010735448d6aa09ba35bdd1de231393f683","observation_id":"038b94dc-37d8-4926-8d93-c07121fb67bd","resolution":{"observed_at":"2026-08-08T23:48:51.408200Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.670700Z","title":"oneAPI Programming Model","venue":null,"work_id":"b3f4459b-6aca-431a-8b0c-7003eeb6d729","year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.414010Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:f4b8ea31b02b7fc0ec2ccf904bcc3f99eb109766cc7eceef9a076e0ab0cdce90","observation_id":"fad313ad-3bed-467d-b62e-94a062a18c52","resolution":{"observed_at":"2026-08-08T23:48:55.675733Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.653346Z","title":"RISC-V Packed SIMD Extension","venue":null,"work_id":"59fb1b53-3d56-4d3c-a2f2-426014475241","year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.419230Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:10e1c987b6be23f8e90961cd700b19c94faa430692cfbd1961474e9d556eac93","observation_id":"db18cb63-a17f-4769-86fd-1ebd599cb70a","resolution":{"observed_at":"2026-08-08T23:48:55.658613Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.637047Z","title":"Snitch Cluster, PULP Project","venue":null,"work_id":"821fde4b-c4f7-4d1a-b78c-6281e0f77f6d","year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.425997Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:5be958b277e87b66c418017bc366c4afac4016f0aa3036bd797b88b3b57c760d","observation_id":"9588172b-ce57-4bbe-9d27-c551857c324d","resolution":{"observed_at":"2026-08-08T23:48:55.641920Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.620294Z","title":"Torch-MLIR","venue":null,"work_id":"c4928bf2-e597-4deb-a00e-116690b64a89","year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.430751Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:a8c98e39bbbd883f6112f338062d7d4b513ad04dee90b448748ccc0529b91e3a","observation_id":"5f6d8b74-b953-4b57-9418-1a4702c33b70","resolution":{"observed_at":"2026-08-08T23:48:55.626156Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.605430Z","title":"Verilator","venue":null,"work_id":"7c9c4bee-fbb5-42b1-849a-99fce379d152","year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.435045Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:38ab2e6382c2486c0b2f9e5f7ca4953af59fb1e550e3826937784c7de6b79597","observation_id":"a1afb103-f3c5-49f5-9ca2-f25fff7ff94d","resolution":{"observed_at":"2026-08-08T23:48:55.610128Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.590285Z","title":"xDSL: A Python Compiler Design Toolkit","venue":null,"work_id":"ea4095bf-3109-463f-868c-9f858b58a5f2","year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.439481Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:1f9b60913c5c57e7925482bb7c633c89cdfcaaaeb25b87cc6b8f2bf0e3c48e81","observation_id":"d9e124b1-f209-4f31-8da9-b494f6618740","resolution":{"observed_at":"2026-08-08T23:48:55.595346Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.573089Z","title":"XuanTie RISC-V ISA Extensions Specification","venue":null,"work_id":"77bbfdba-9302-4c67-b40c-0afd82574fd3","year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.444012Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:3504afe85abff2ddf7d39b9039d0955ab4ae5b3b06f961bd63888c624e1a445a","observation_id":"e4acbdc9-8e85-4b7e-b97d-6f09577da8e2","resolution":{"observed_at":"2026-08-08T23:48:55.578107Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.449228Z","title":"Murray, Benoit Steiner, Paul Tucker, Vijay Va- sudevan, Pete Warden, Martin Wicke, Yuan Yu, and Xiaoqiang Zheng","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.449228Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:1f823495ded648c514a38c6aebb204daff7ca9be9f23961d78712dbcbc9d2e76","observation_id":"2f036976-c2e1-40ad-85cf-028fce0c91b3","resolution":{"observed_at":"2026-08-08T23:48:51.449228Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.531097Z","title":"2001.Optimizing Compilers for Modern Architectures: A Dependence-based Approach(1 ed.)","venue":null,"work_id":"2b21abb1-876a-4e96-835a-ade821c4441f","year":2001},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.460184Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:9354ee316733cdda09c1fda0861f3a57fdea47216de19978b3624b2196b3928c","observation_id":"a4ab2f54-a5eb-468b-a5c8-b71195baa3e4","resolution":{"observed_at":"2026-08-08T23:48:55.536174Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"4872.33148","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.199847Z","title":null,"venue":null,"work_id":"6252d18e-da33-4719-b99b-4188637b6e47","year":2019},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.465021Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:cd3cb78a5dd5a0db835299cbfb0fb7f7b2e153c8fa91aa200f2d06fa309cd14a","observation_id":"a4ee15a8-e58b-413b-8bd4-250ebeee4056","resolution":{"observed_at":"2026-08-08T23:48:55.208665Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.470222Z","title":null,"venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.470222Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:d9362bc5abc9123adc380c0dd9f08661352a6cf23a67252b3085ac13b07e2c8e","observation_id":"30eaac7a-80bc-4552-8551-8ea3edaa7e1d","resolution":{"observed_at":"2026-08-08T23:48:51.470222Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2003.00532","last_updated":"2020-03-01T17:44:08Z","snapshot_observed_at":"2026-08-21T08:58:31.368259Z","submitted_at":"2020-03-01T17:44:08Z","title":"High Performance Code Generation in MLIR: An Early Case Study with GEMM","version":1},"cited_work":{"arxiv_id":"2003.00532","doi":null,"metadata_source":"pith","pith_arxiv_id":"2003.00532","snapshot_observed_at":"2026-08-08T23:48:55.020626Z","title":"High Performance Code Generation in MLIR: An Early Case Study with GEMM","venue":"cs.PF","work_id":"744dac80-4009-44a2-b75e-1dcb9530bc72","year":2020},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.475131Z"},"links":{"cited_paper":"/paper/2003.00532","citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:7e8429d9d05edbe8995d06c782ee568028878dfe2f8ef4be49148127625eb757","observation_id":"2e04fe51-71a4-4045-9cd8-0734c96a96a2","resolution":{"observed_at":"2026-08-08T23:48:55.025660Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.516288Z","title":null,"venue":null,"work_id":"69b7d6d6-0175-4086-b69c-f814486cea7a","year":null},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.480190Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:8d65f4d3fe73396368694a0bfbc0a24babab31933b71999248215806bdebfbe1","observation_id":"332873dd-fb2c-4167-9a8c-9800e2e16181","resolution":{"observed_at":"2026-08-08T23:48:55.520939Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.485074Z","title":null,"venue":null,"work_id":"66077f74-1cc4-49e8-bbcd-178c83cdc30d","year":2023},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.490549Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:fc36e0367809df1b3fb188ef45f495225ce81564df4beeafe20b2e6733a5a513","observation_id":"e89f6615-f44c-4850-bdf0-3ab7e3085e53","resolution":{"observed_at":"2026-08-08T23:48:55.491086Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1007/978-3-030-60276-5_8","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T05:30:23.456663Z","title":null,"venue":"Lecture notes in computer science","work_id":"6e2e784c-f0b5-4664-ad48-29b573d7c548","year":2020},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.495803Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:bfcb139cd3fadd2c3f2345f5f2609d79c0c6e8bcdc9a50760ca0a550a7b239ec","observation_id":"e0456e2b-efd2-44c8-a091-e433d61a095f","resolution":{"observed_at":"2026-08-08T23:48:52.134207Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.501607Z","title":null,"venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.501607Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:457edc842a6a129f877e5e369685597640d8059a97dced8418e645cf6d9921f9","observation_id":"8d43fe16-ca69-4696-a83e-cbe71aff8656","resolution":{"observed_at":"2026-08-08T23:48:51.501607Z","resolver_source":null,"status":"malformed_identifier"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.468435Z","title":null,"venue":null,"work_id":"28ded5b3-3c9a-4b5e-b4d6-5c669d34f7fa","year":2018},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.506496Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:ad9b4fe00f9428628ba45a90300807ffd72bc3faf52a0ef8bb4c7c28300ca714","observation_id":"64a2d917-0863-409b-a8db-2882ad6349e5","resolution":{"observed_at":"2026-08-08T23:48:55.474310Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1805.08166","last_updated":"2019-01-08T23:35:15Z","snapshot_observed_at":"2026-08-14T19:12:53.135307Z","submitted_at":"2018-05-21T16:38:12Z","title":"Learning to Optimize Tensor Programs","version":4},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1805.08166","snapshot_observed_at":"2026-08-08T23:48:51.511314Z","title":null,"venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.511314Z"},"links":{"cited_paper":"/paper/1805.08166","citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:26b232ebdf5280a703c3756f3c904eb886cab319fdfd85d744ce41a6bba9907b","observation_id":"08525448-7935-4828-a2f5-a129a84fd542","resolution":{"observed_at":"2026-08-08T23:48:51.511314Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"1410.0759","last_updated":"2014-12-18T01:13:16Z","snapshot_observed_at":"2026-08-14T23:17:07.466378Z","submitted_at":"2014-10-03T06:16:43Z","title":"cuDNN: Efficient Primitives for Deep Learning","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1410.0759","snapshot_observed_at":"2026-08-08T23:48:51.516562Z","title":null,"venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.516562Z"},"links":{"cited_paper":"/paper/1410.0759","citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:96d2821f5a87f1353f59f233f360bb5a2b192b6586301a18eecf1f294c22269f","observation_id":"44e5a90a-4d7c-4f86-8e61-988b3b83c42d","resolution":{"observed_at":"2026-08-08T23:48:51.516562Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1016/c2014-0-01395-0","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T05:30:23.456663Z","title":null,"venue":"Elsevier eBooks","work_id":"36498038-6323-439a-8c78-06b6383881d2","year":2023},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.521735Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:8debba2fd879a9c8ba25b7d6a84e061c8f941e1b1d5530b6098c9afe6f981391","observation_id":"39680294-ac9c-4e23-9d82-73ec707d0c88","resolution":{"observed_at":"2026-08-08T23:48:52.101790Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.526559Z","title":null,"venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.526559Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:890853cb30931c7d46f6a5db2120875cb9b30819ceef76ccd33a1975f55e2fa4","observation_id":"ee67465d-19c5-419b-9c97-52aef3251e62","resolution":{"observed_at":"2026-08-08T23:48:51.526559Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"7626.79170","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:54.842311Z","title":null,"venue":null,"work_id":"bb9455ce-6032-45c8-8739-07b91fa98029","year":1990},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.531431Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:f987df88fc97c26c4c5b58344faef1d402bd7b00cbfb160c1465eed943407041","observation_id":"54c21b94-f3d2-4ebf-afa5-73c007531cb4","resolution":{"observed_at":"2026-08-08T23:48:54.849313Z","resolver_source":"raw_fallback","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.07422","last_updated":"2024-06-17T00:23:29Z","snapshot_observed_at":"2026-08-16T14:43:45.017105Z","submitted_at":"2023-11-13T15:57:45Z","title":"Sidekick compilation with xDSL","version":3},"cited_work":{"arxiv_id":"2311.07422","doi":"10.48550/arxiv.2311.07422","metadata_source":"pith","pith_arxiv_id":"2311.07422","snapshot_observed_at":"2026-08-10T05:30:23.456663Z","title":"Sidekick compilation with xDSL","venue":"cs.PL","work_id":"f3ab30f2-ca06-4550-a07d-13deb789b16f","year":2023},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.536326Z"},"links":{"cited_paper":"/paper/2311.07422","citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:f5f335dc35dcf0afa37a404161fd073b48dd46fb8c186f33dc803e240c183976","observation_id":"8e6bbdb3-99b8-411e-864f-aa00ee735ea6","resolution":{"observed_at":"2026-08-08T23:48:52.086597Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2019.89650","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:54.748770Z","title":null,"venue":null,"work_id":"8b2d8b06-03d5-4a2c-a18e-635b29b341bc","year":2019},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.541832Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:66c830ef11218238efb8597832b109167b0b80bf7c705defa50e751ead51c3f6","observation_id":"dfa86149-b05e-4fa8-8941-a25e01cfcc7e","resolution":{"observed_at":"2026-08-08T23:48:54.756002Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2017.26545","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:54.663925Z","title":"Gürkay- nak, and Luca Benini","venue":null,"work_id":"716f45fb-495a-4c7e-90e6-ad16630e4beb","year":2017},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.551482Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:38c3dd140557ea9c586828f5190bde9307ea02da7d940724faa73bf798c3b3fd","observation_id":"517ade6c-30ec-4245-853f-e2ee736da41e","resolution":{"observed_at":"2026-08-08T23:48:54.670973Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"9009.35696","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:54.572794Z","title":null,"venue":null,"work_id":"f98fc555-7fc8-4de1-8e0d-86e1948209d5","year":2023},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.556207Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:f1dd5346d7f9ea95878211b4936fa15508f97bbecec989d641b5be7364524627","observation_id":"0dc77438-9c55-4635-b274-49588a39db36","resolution":{"observed_at":"2026-08-08T23:48:54.580075Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.560887Z","title":"van de Geijn","venue":null,"work_id":null,"year":2008},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.560887Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:38130c48009300c3522cbc781d1d31e97fc6a8bcd195d4cfc86dccf315f6a830","observation_id":"ad735453-903b-46c1-a0f9-81514a185466","resolution":{"observed_at":"2026-08-08T23:48:51.560887Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1142/s0129626412500107","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T05:30:23.456663Z","title":null,"venue":"Parallel Processing Letters","work_id":"ba9aa9eb-6711-487c-a21f-d1eed4330639","year":2012},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.565515Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:7d14968a400ab8fc7b9aee8f6ded1803fa793df0fe44343f97b8b6ea30331a36","observation_id":"c68875e4-51fa-471a-8470-969448f715c1","resolution":{"observed_at":"2026-08-08T23:48:52.065276Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.453459Z","title":null,"venue":null,"work_id":"6e3c667e-88dd-4fca-9c22-1c2fcaa9a32e","year":2021},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.570414Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:3677c7c06f801425f0c363b18150ecbf0c460f6549ed104c27f1febc65ee5775","observation_id":"179be694-e131-4ba2-b930-77ebb5511741","resolution":{"observed_at":"2026-08-08T23:48:55.458104Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.437994Z","title":null,"venue":null,"work_id":"7b25198d-0829-47bf-b10c-3d53af1c82c3","year":2006},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.575265Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:be54cf909f19671fd7d4c03b30d2748256c1076d7b812d678ca2ce2c874df68f","observation_id":"b9bba826-214e-454b-892f-37d512f474fe","resolution":{"observed_at":"2026-08-08T23:48:55.443249Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.585018Z","title":null,"venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.585018Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:edccf915182d5f349d756749f32eaf842fa2c5545ed44c3e359f45805407ed56","observation_id":"f99b2d4f-c4d8-4cb9-a65b-492393e00f79","resolution":{"observed_at":"2026-08-08T23:48:51.585018Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1109/sc.2016.83","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T05:30:23.456663Z","title":null,"venue":null,"work_id":"7e8dcbdc-3ee8-48a8-a7cb-d173c14e31dc","year":2016},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.590420Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:7e904623b3ca4d012ce574ce27f71863a13f209c6cabe1065e4a3b73abc9a2d4","observation_id":"4ddb4b71-c43e-4829-aba4-0ab3b433222a","resolution":{"observed_at":"2026-08-08T23:48:52.040067Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.596530Z","title":"Hennessy and David A","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.596530Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:906b6899c75704bcabe1bd4dc2f3355aca7eee529d13c7db081d82f830428896","observation_id":"b3bfed56-a69c-4723-a22b-df53ec475662","resolution":{"observed_at":"2026-08-08T23:48:51.596530Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.601387Z","title":null,"venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.601387Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:c52792accfd8ee65fa090e1bd23407099fdca023b06af31c3ba3a917d653d3a4","observation_id":"be703460-8aaa-47e6-a541-00fef4613e1d","resolution":{"observed_at":"2026-08-08T23:48:51.601387Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"4137.25441","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:54.267309Z","title":null,"venue":null,"work_id":"ad31fbcc-219b-439a-b8cf-e96a66f9948f","year":2018},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.606038Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:4a52662613540b21eaff4c84d99e9dd7b1d1a544039cab2de7137ae88bf1fae2","observation_id":"dd863d3f-8e4d-4a9f-87ab-270815746052","resolution":{"observed_at":"2026-08-08T23:48:54.274488Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2008.08272","last_updated":"2020-10-01T01:15:28Z","snapshot_observed_at":"2026-08-10T22:39:45.878362Z","submitted_at":"2020-08-19T05:28:08Z","title":"Compiling ONNX Neural Network Models Using MLIR","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2008.08272","snapshot_observed_at":"2026-08-08T23:48:51.610577Z","title":"Le, Tong Chen, Gong Su, Haruki Imai, Yasushi Negishi, Anh Leu, Kevin O’Brien, Kiyokuni Kawachiya, and Alexandre E","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":45,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.610577Z"},"links":{"cited_paper":"/paper/2008.08272","citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:8bd0fe11ea0435e54e944aee2f08544858ef2ef6adc6ce615603832db6455938","observation_id":"457d0097-0b57-4cd8-93b1-bf73d0cad007","resolution":{"observed_at":"2026-08-08T23:48:51.610577Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.615733Z","title":null,"venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":46,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.615733Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:aa1088f6adb2a24390bc503fb01521da4840a9bb9c9f8be01dfa3dbf816f4330","observation_id":"3e3f12bd-598f-42cc-84f4-6f83586b8e08","resolution":{"observed_at":"2026-08-08T23:48:51.615733Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.620849Z","title":null,"venue":null,"work_id":null,"year":2017},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":47,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.620849Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:426eb8a2e60e7c64bdb29b613c064786867f5770e897898c9fdd9de444dfcf89","observation_id":"e01b0b37-4d0a-446f-9d43-e1f47a6e7a7a","resolution":{"observed_at":"2026-08-08T23:48:51.620849Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.625718Z","title":null,"venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":48,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.625718Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:7c0d00ac105145dd2b698ccb28319fc66d0b65d9e63dc6bbd89d10b1bae4884b","observation_id":"ce8128b3-e579-4eac-bd19-c240fd5e77c6","resolution":{"observed_at":"2026-08-08T23:48:51.625718Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.630252Z","title":null,"venue":null,"work_id":null,"year":2013},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":49,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.630252Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:1c4b9ef765faad067020666650ca9108e5d715b4d9ce6007b4e7d52b04863a16","observation_id":"0c4ff955-bc22-40cf-9afe-36b94a651048","resolution":{"observed_at":"2026-08-08T23:48:51.630252Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.634726Z","title":null,"venue":null,"work_id":null,"year":2017},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":50,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.634726Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:45933765556a95bb22e07013d4fb3a265a979ba37c4ff5aa468e05897ae6d63e","observation_id":"02acfec8-82dd-4e6d-92d5-dc6b8d7f698b","resolution":{"observed_at":"2026-08-08T23:48:51.634726Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1002/spe.3214","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T00:03:40.895421Z","title":null,"venue":"Software Practice and Experience","work_id":"4d96d11e-df92-46b7-bde7-3322966e50b0","year":2023},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":51,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.639296Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:5b86ff0ba8940ada5e7a5701b0806c5af2f58da37726375ca3d8a3962302adb1","observation_id":"79afe977-ddcc-4119-8348-13fcace20fd5","resolution":{"observed_at":"2026-08-08T23:48:51.977010Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.420654Z","title":null,"venue":null,"work_id":"296fd2ed-1797-42a0-89ba-c722a308ba3a","year":2004},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":52,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.643864Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:42e2e9ac33defcf086d40790ec04d15d9d9ba8d063ad364b76239b252c570a0f","observation_id":"88b19147-2ae1-4ae9-aad0-09b331a4a587","resolution":{"observed_at":"2026-08-08T23:48:55.426676Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.653661Z","title":null,"venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":53,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.653661Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:d3d5e6da0498a6937178cd8ccd6f53eab55f50bc7bb8acc4e674c59a6f3cc990","observation_id":"c034c6d3-6689-4540-ad11-67d31705ba9a","resolution":{"observed_at":"2026-08-08T23:48:51.653661Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.658844Z","title":"Sadayappan","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":54,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.658844Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:bc33bd328bd465eeaaa0dde92d8de50155eb679cc4d84d0df8bb7eac86a0352a","observation_id":"ab31b7c0-81d9-498e-af51-ad1f92d30686","resolution":{"observed_at":"2026-08-08T23:48:51.658844Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.663831Z","title":null,"venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":55,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.663831Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:f6fa5e9961747d1363582399381d4dcd81deac807a47bf340c62d0f4cbb89014","observation_id":"52f3dfac-a479-48ad-9b8a-e675fe331bf3","resolution":{"observed_at":"2026-08-08T23:48:51.663831Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.5281/zenodo.14052014","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T05:30:23.456663Z","title":"A Multi-Level Compiler Backend for Accelerated Micro-kernels Targetting RISC-V ISA Extensions","venue":"Edinburgh Research Explorer (University of Edinburgh)","work_id":"7f66123e-7ea8-414d-9493-b7d1f0030f01","year":2024},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":56,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.668460Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:7cc266e3c97351c7158095e5c90ad8d304424fcd26adecbc0fdf9292bcf1acba","observation_id":"d294a7ef-4223-41f1-bd9c-d3782bce54ef","resolution":{"observed_at":"2026-08-08T23:48:51.942428Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.673173Z","title":null,"venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":57,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.673173Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:68dd28dae20b551e67d15ae80844d080fb0883088d5dc1447e101bd289231947","observation_id":"1bfb1373-14b7-4d19-9054-ae297187cbf0","resolution":{"observed_at":"2026-08-08T23:48:51.673173Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.404162Z","title":null,"venue":null,"work_id":"b2f1c1cc-8cfb-412e-a198-89652e499d70","year":2023},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":58,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.677775Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:e3aa88ccb9211ed43e6673880ae2158e11129fae3673d6ed538da4b3f810aa37","observation_id":"2b8223a6-a781-4af9-b4ef-109cb28b363f","resolution":{"observed_at":"2026-08-08T23:48:55.409280Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.682498Z","title":null,"venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":59,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.682498Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:f4aa92542c25f17d2917388b8b2e2218337c067da529288faa07e5bfb859f5e7","observation_id":"3b2d5078-63f5-43df-928a-b194b49b4739","resolution":{"observed_at":"2026-08-08T23:48:51.682498Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.365089Z","title":null,"venue":null,"work_id":"f4619d0c-4750-4e42-91f6-08b08a6d4a73","year":2021},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":60,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.692348Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:9999d4b831f8bc2a94fb6bf81a2a6ce02f758bcbc2af1d30454526d256badc5e","observation_id":"536a74c9-7d63-4bc8-82a5-5bad0e286c82","resolution":{"observed_at":"2026-08-08T23:48:55.369748Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.697415Z","title":null,"venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":61,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.697415Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:d14c93f9f91ff3137209f03ca91bedba3621e14b5427ab9ff63386ae9d70917d","observation_id":"58efdb77-c94b-4005-b3c8-02896418d4df","resolution":{"observed_at":"2026-08-08T23:48:51.697415Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.351358Z","title":null,"venue":null,"work_id":"d3c90cb7-e650-48c5-a8a9-c8ce76dab55f","year":2007},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":62,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.702220Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:746c5e7cbaf7155f9d590a44962c8ebbecc88195b32eb65a05250a786f0be55f","observation_id":"1369012a-1f0f-4d8c-9f28-89eef3d239df","resolution":{"observed_at":"2026-08-08T23:48:55.355789Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2019.29123","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:53.631014Z","title":null,"venue":null,"work_id":"7f4ba2c2-35cc-42f2-847e-4eeebb0346b3","year":2019},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":63,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.706641Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:5c91377ea4a71bb6735f7af2b09378f8c5f701573eae7abba0ed5cc30b5884fe","observation_id":"f2329fb6-b4a7-467c-900a-085b58f94d6b","resolution":{"observed_at":"2026-08-08T23:48:53.638319Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.711279Z","title":null,"venue":null,"work_id":null,"year":2013},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":64,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.711279Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:bb99d3e67700a8d45ef1fc509bf9b16b630494932bd47f3ea4a076c91ccb9f26","observation_id":"1396ac95-6aff-4e14-812f-27c26c75ac29","resolution":{"observed_at":"2026-08-08T23:48:51.711279Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.337244Z","title":null,"venue":null,"work_id":"3b91d551-eb34-421a-989d-f3bc87e16a4b","year":null},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":65,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.715981Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:dfadf258b25185472ab6144f6980aed2fd5621d0d105e510375ed8d2d993c332","observation_id":"9fb0529a-174e-47e9-841e-5ae64e30d01f","resolution":{"observed_at":"2026-08-08T23:48:55.341744Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.726161Z","title":null,"venue":null,"work_id":null,"year":2017},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":66,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.726161Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:c6748d515cacd41f15e51536f5513b6ac311a773eadee46b83d9a473904f0eaf","observation_id":"6ed17099-f643-4851-ab27-01d6944d8d5e","resolution":{"observed_at":"2026-08-08T23:48:51.726161Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:53.280717Z","title":null,"venue":null,"work_id":"766fd9a1-af3b-4420-92f0-a1c7c299a0dd","year":2019},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":67,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.732137Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:7744d2b4f6f0403142025eb0f5b5725dadb080d2c63cb52c31d9ad74d510de01","observation_id":"8e4499c8-46e5-4ed0-adf9-723864f9df00","resolution":{"observed_at":"2026-08-08T23:48:53.285750Z","resolver_source":"arxiv_id_nonexistent","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.321264Z","title":null,"venue":null,"work_id":"743e1df5-6b1d-4b6b-8b18-0f88ebfe0a14","year":2023},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":68,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.737303Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:606ded13ee8a46f7d06e98f75502399fcd38a9b7b9207f463aa9aeff56da559c","observation_id":"65c58352-e228-4edf-aa4f-16368c992ead","resolution":{"observed_at":"2026-08-08T23:48:55.327349Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:53.017553Z","title":null,"venue":null,"work_id":"d3abcafc-122d-4252-aaf3-30420b045ddc","year":2019},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":69,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.742606Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:ede59e84f4c93eb009eebf241246a41361fccbb95483d6f9830af14416ffb330","observation_id":"d98ffdf2-16ce-4795-9fc9-ec42d97af2b4","resolution":{"observed_at":"2026-08-08T23:48:53.022343Z","resolver_source":"arxiv_id_nonexistent","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.305895Z","title":"Sadayappan, and Fabrice Rastello","venue":null,"work_id":"53c0bafa-bcaa-4ce3-a61c-70ab424f4943","year":null},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":70,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.747555Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:097d73a6f701269c66c213f363acf968ca5b140c85d56be588b45b25967418b6","observation_id":"72a52fec-4cdd-4358-a817-50a7959568e4","resolution":{"observed_at":"2026-08-08T23:48:55.311049Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1145/2755561","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T05:30:23.456663Z","title":"Van Zee, Tyler M","venue":"ACM Transactions on Mathematical Software","work_id":"1a8830d9-34d0-4071-b6ef-36830206bee4","year":2016},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":71,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.758343Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:442ee100453f17728ceca8f63b597bd33136065112a5b46ebf92242f19236aa4","observation_id":"a636035c-6dfa-4322-8730-97197461696d","resolution":{"observed_at":"2026-08-08T23:48:51.926148Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.272192Z","title":null,"venue":null,"work_id":"f1deee6e-bb50-4d27-aa52-097e8e983c41","year":2023},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":72,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.765239Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:bda25887b16f63866aaa2005923af1851cc4963a2e728e1b173c63cf81f28817","observation_id":"e6044230-6e77-4765-b459-4f99c69c8716","resolution":{"observed_at":"2026-08-08T23:48:55.277662Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2202.03293","last_updated":"2022-02-07T15:31:59Z","snapshot_observed_at":"2026-08-16T17:23:05.280366Z","submitted_at":"2022-02-07T15:31:59Z","title":"Composable and Modular Code Generation in MLIR: A Structured and Retargetable Approach to Tensor Compiler Construction","version":1},"cited_work":{"arxiv_id":"2202.03293","doi":"10.48550/arxiv.2202.03293","metadata_source":"pith","pith_arxiv_id":"2202.03293","snapshot_observed_at":"2026-08-09T00:16:22.132183Z","title":"Composable and Modular Code Generation in MLIR: A Structured and Retargetable Approach to Tensor Compiler Construction","venue":"cs.PL","work_id":"a913327c-794a-42b8-bf8a-480114a38dfa","year":2022},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":73,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.771076Z"},"links":{"cited_paper":"/paper/2202.03293","citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:564aeff816ac649247a777a36ec56fbdec9df51064a505ce93cc7816e977ea29","observation_id":"d3fb5086-52d9-4e37-82ad-484a0793c7ff","resolution":{"observed_at":"2026-08-08T23:48:51.909126Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1601.01722","last_updated":"2016-01-07T22:43:43Z","snapshot_observed_at":"2026-08-17T03:59:33.321880Z","submitted_at":"2016-01-07T22:43:43Z","title":"Profiling-Assisted Decoupled Access-Execute","version":1},"cited_work":{"arxiv_id":"1601.01722","doi":null,"metadata_source":"pith","pith_arxiv_id":"1601.01722","snapshot_observed_at":"2026-08-08T23:48:52.787221Z","title":"Profiling-Assisted Decoupled Access-Execute","venue":"cs.AR","work_id":"80cd716e-e6f0-457f-9b3a-52d127565aa6","year":2016},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":74,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.777015Z"},"links":{"cited_paper":"/paper/1601.01722","citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:965875af595e71580cb840d48276267e8c88a89bb729eda6f8b8ff91f0e437f6","observation_id":"f88cedfb-c3e5-41a6-ae2c-e66cf93d65df","resolution":{"observed_at":"2026-08-08T23:48:52.792965Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.256192Z","title":null,"venue":null,"work_id":"a59a3511-cf47-4d9b-ab6c-ab052caf725b","year":2019},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":75,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.783250Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:22c0163c154b0c4194b88174e44835bc721a044a76961fe57b6c8699c099546c","observation_id":"b7ad92b6-05f7-4943-85f7-538bbb766f68","resolution":{"observed_at":"2026-08-08T23:48:55.261981Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.237302Z","title":null,"venue":null,"work_id":"631bcb5e-ff9f-4468-831e-b6a7395163df","year":2010},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":76,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.789395Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:c513e4abf2a1dfe98950c6fb2e7184c67afe8134b03fb92355497bb07e52fe5f","observation_id":"e89fadd8-7758-421e-8e00-1730f5b4ea32","resolution":{"observed_at":"2026-08-08T23:48:55.243518Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1109/sccc.2012.29","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T05:30:23.456663Z","title":null,"venue":null,"work_id":"d57fcf9a-6dfe-4e99-ad4f-de003357851b","year":2012},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":77,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.800207Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:d77600056b873604b2ca69f826329f4e7b1973c127573141ae48efd1ca001a31","observation_id":"c5f30a27-2530-4496-bd88-76625002044d","resolution":{"observed_at":"2026-08-08T23:48:51.885399Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.221776Z","title":null,"venue":null,"work_id":"2fbddc8c-c796-4dbd-9562-d7b5ff787ecb","year":2023},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":78,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.807860Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:5cebf649c55d79dd7109429807aea90c87f3930639f69a6aacdb33b8e8c35673","observation_id":"9de91498-8deb-43e9-afa7-174c8458ae49","resolution":{"observed_at":"2026-08-08T23:48:55.226853Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:52.523529Z","title":null,"venue":null,"work_id":"f062f0cf-f4d2-4044-ab9f-38a738634d66","year":2021},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":79,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.813050Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:e430f6beb8c948e7c5773c9139a26c966014416d5cf6a6f9d4bb571fc6d360e0","observation_id":"92521b55-5236-41fc-8ea5-4997988b036c","resolution":{"observed_at":"2026-08-08T23:48:52.533688Z","resolver_source":"arxiv_id_nonexistent","status":"malformed_identifier"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:52.318006Z","title":null,"venue":null,"work_id":"4e1098e4-950e-4ce0-b0d2-2a2c3ef3ce62","year":2021},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":80,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.819220Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:9210724351ff7b278f77c3035205114bfe642d235b904e501ef806cefd55636c","observation_id":"b65872c9-ba3e-4645-8102-b455a5609669","resolution":{"observed_at":"2026-08-08T23:48:52.322706Z","resolver_source":"arxiv_id_nonexistent","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.824119Z","title":null,"venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":81,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.824119Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:50ecee31a0abafefbaad98d518681b80b4c0505b40b335fb04e0e0c73db6b898","observation_id":"f4eefe06-a5aa-4bc0-bf8b-508d66c92eff","resolution":{"observed_at":"2026-08-08T23:48:51.824119Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:52.765466Z","title":null,"venue":null,"work_id":"80072dca-0c46-4dbe-9307-ef439995097a","year":null},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":179,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.794443Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:ab5e1c60089d4d11587ac5c47cb59576e3821aa2019efd30aebe6ea065f4099b","observation_id":"8090f09b-72bc-4970-a97d-755a2ea74d2b","resolution":{"observed_at":"2026-08-08T23:48:52.770751Z","resolver_source":"arxiv_id_nonexistent","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.580233Z","title":null,"venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":262,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.580233Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:635efd8c3b6cdaff2b12839df69a0a1963b47cf1b6898c0de32a951ca9adfa60","observation_id":"9d8bf7f7-b6eb-4bc1-9c1b-b7a00cb53f0e","resolution":{"observed_at":"2026-08-08T23:48:51.580233Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2004.12816","last_updated":"2020-04-23T22:36:05Z","snapshot_observed_at":"2026-08-11T15:13:27.814382Z","submitted_at":"2020-04-23T22:36:05Z","title":"Zakharov-Ito equation and Generalized Heisenberg ferromagnet-type equation: equivalence and related geometric curve flows","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2004.12816","snapshot_observed_at":"2026-08-08T23:48:51.648670Z","title":"IEEE Computer Society, Washington, DC, USA, 75–","venue":null,"work_id":null,"year":2004},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":2004,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.648670Z"},"links":{"cited_paper":"/paper/2004.12816","citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:7c29ced8dd2dd212c42cb9aae9ba6e72a4eade2817e7f2d12006c5ad01093a1c","observation_id":"f47e13af-e8ea-4f08-964b-dbd721f1b47e","resolution":{"observed_at":"2026-08-08T23:48:51.648670Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.500965Z","title":"Research Report","venue":null,"work_id":"f1dd4dfe-1d1d-4a0b-9b36-389d7d5c05e3","year":null},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":2005,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.485066Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:24eb0c93632457c4e234f184faaa55a5ca6de73f74b618232187e52b75e54cc4","observation_id":"c28217c0-69ec-440f-9994-3ce9b29c0b65","resolution":{"observed_at":"2026-08-08T23:48:55.505786Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.547269Z","title":"In 12th USENIX Symposium on Operating Systems Design and Implemen- tation (OSDI 16)","venue":null,"work_id":"4b34ea15-b490-423c-8aca-38f5b0226896","year":null},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":2016,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.454408Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:9e052379bf9b640a3286d50fa94f5a7d0b7afb68418851291121dbcf6da3aff5","observation_id":"de636524-6002-4fe6-873d-7091ac23f52a","resolution":{"observed_at":"2026-08-08T23:48:55.552471Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.379314Z","title":"In Advances in Neural Information Processing Systems , Vol","venue":null,"work_id":"1d5d1efd-149f-485e-8da2-2962ae6177b5","year":2019},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":2019,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.687633Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:260da8da6e500349a1f6f3e9bbc5c42200ee9e425a52dc88ddbfb5b9282fb32b","observation_id":"f77e909a-8fd5-4165-a690-ed4b9855ddf1","resolution":{"observed_at":"2026-08-08T23:48:55.384531Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:51.720970Z","title":"IEEE Trans","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":2021,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.720970Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:511da93e4a05b4d9c1579eac2bb53658aa66b70e7e253f662a3d030c2a323fa8","observation_id":"13ff2ded-e344-4936-9063-dae6a2c09c07","resolution":{"observed_at":"2026-08-08T23:48:51.720970Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T23:48:55.288580Z","title":"ACM Trans","venue":null,"work_id":"bb4fa8cb-d384-4c5d-9452-a805d6eda313","year":2023},"citing_paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions","version":1},"reference_index":2023,"source":"pdf_text","source_observed_at":"2026-08-08T23:48:51.752762Z"},"links":{"citing_paper":"/paper/2502.04063"},"observation_digest":"sha256:f2fed3d9fe04ff14290083c0df16a9aaabe7299b5d8c748f06d25278c073ba7c","observation_id":"81950f3c-47fa-441e-bc54-80641807b127","resolution":{"observed_at":"2026-08-08T23:48:55.294566Z","resolver_source":"raw_fallback","status":"malformed_identifier"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2502.04063","last_updated":"2025-02-06T13:20:29Z","latest_version":1,"primary_category":"cs.PL","snapshot_observed_at":"2026-08-16T10:39:25.938365Z","submitted_at":"2025-02-06T13:20:29Z","title":"A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions"},"reference_resolution":{"displayed":88,"state_counts":{"malformed_identifier":3,"metadata_mismatch":6,"parse_uncertain":0,"unresolved":50,"verified_exact":17,"verified_fuzzy":12},"total_outbound_references":88},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"thesis":"As of 21 August 2026, this Paper Citation Record lists 88 of 88 outbound references and 0 inbound Pith citation observations for arXiv:2502.04063."}