{"as_of":"2026-08-08T05:52:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:1e88ae15f94c1b39356cb523077c05e9793e245f44714b738fa36c95918e41d6","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":1,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-07T06:34:17.273281+00:00","state":"measured"},{"denominator":1,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":1,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-05T00:46:51.709066Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"pith","source_observed_at":"2026-08-05T00:46:52.252538Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2503.14153","last_updated":"2025-03-18T11:21:53Z","snapshot_observed_at":"2026-08-07T16:55:10.109424Z","submitted_at":"2025-03-18T11:21:53Z","title":"Speculative Decoding for Verilog: Speed and Quality, All in One","version":1},"cited_work":{"arxiv_id":"2503.14153","doi":null,"metadata_source":"pith","pith_arxiv_id":"2503.14153","snapshot_observed_at":"2026-08-05T00:46:52.252538Z","title":"Speculative Decoding for Verilog: Speed and Quality, All in One","venue":"cs.LG","work_id":"d18c7c03-ca4f-49b8-b31b-83e78b1601ec","year":2025},"citing_paper":{"arxiv_id":"2608.00531","last_updated":"2026-08-01T08:43:34Z","snapshot_observed_at":"2026-08-08T01:16:09.375026Z","submitted_at":"2026-08-01T08:43:34Z","title":"CURE: Local Uncertainty Repair for Block-Parallel Speculative Decoding","version":1},"reference_index":77,"source":"arxiv_source","source_observed_at":"2026-08-05T00:46:51.709066Z"},"links":{"cited_paper":"/paper/2503.14153","citing_paper":"/paper/2608.00531"},"observation_digest":"sha256:e4954724aceba505db16fa6066c4ce845107d93a0444924ad2c784165403938c","observation_id":"3eb44d2d-ba47-453f-a056-06b66dfb40fd","resolution":{"observed_at":"2026-08-05T00:46:52.326530Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/2503.14153/citation-record","integrity":"/paper/2503.14153/integrity","json":"/paper/2503.14153/citation-record.json","paper":"/paper/2503.14153"},"outbound":[],"paper":{"arxiv_id":"2503.14153","last_updated":"2025-03-18T11:21:53Z","latest_version":1,"primary_category":"cs.LG","snapshot_observed_at":"2026-08-07T16:55:10.109424Z","submitted_at":"2025-03-18T11:21:53Z","title":"Speculative Decoding for Verilog: Speed and Quality, All in One"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"thesis":"As of 8 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 1 inbound Pith citation observation for arXiv:2503.14153."}