{"as_of":"2026-08-18T17:35:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:3751d3ba9d864f34b3a21c3552a4ff91f93b166f187fbcf650fc25b9cda7a105","coverage":[{"denominator":36,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":36,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-15T22:51:43.780308Z","state":"measured"},{"denominator":36,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":36,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-18T06:34:40.430872+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2505.06096/citation-record","integrity":"/paper/2505.06096/integrity","json":"/paper/2505.06096/citation-record.json","paper":"/paper/2505.06096"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.234920Z","title":"Attention Is All You Need,","venue":null,"work_id":"988bd7f3-4d13-4aa4-901d-0fbdec1d7481","year":2023},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.653484Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:286275f5017b587764f39fa5ce1bda74caeb5bf2d850f2500e9eb900aba2888a","observation_id":"fd090c29-eb09-4e92-8c31-6a0695de2660","resolution":{"observed_at":"2026-08-15T22:51:44.238480Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.224316Z","title":"Transformers: State- of-the-Art Natural Language Processing,","venue":null,"work_id":"bfc538ed-98e3-44d4-aff4-3cd764a9e0ae","year":2020},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.657516Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:e14c5983ac8af00dcc32e9dab871b8d4a9e3b64e1841a91135c9e93c40d7f168","observation_id":"32e4058d-2eb0-4c59-8607-bed85493d71f","resolution":{"observed_at":"2026-08-15T22:51:44.228021Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.214353Z","title":"12 Practical Large Language Model (LLM) Applications,","venue":null,"work_id":"90ed27f5-537a-4041-b953-1d8f35b3049a","year":2023},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.661724Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:94c169daf35ac9a6618830b591b851aab412b25a365f9d514ea41a76a4a24f04","observation_id":"a80cbb0d-5f36-4d50-bde5-9de5304b11ac","resolution":{"observed_at":"2026-08-15T22:51:44.217864Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2401.14196","last_updated":"2024-01-26T09:23:11Z","snapshot_observed_at":"2026-08-06T22:40:28.707813Z","submitted_at":"2024-01-25T14:17:53Z","title":"DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligence","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2401.14196","snapshot_observed_at":"2026-08-15T22:51:43.665298Z","title":"DeepSeek-Coder: When the Large Language Model Meets Programming–The Rise of Code Intelligence,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.665298Z"},"links":{"cited_paper":"/paper/2401.14196","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:583cfd9a77234fec4d3df306998fc080c3ecad55c1c2388d00f1ce2cac3ecab3","observation_id":"0ec0cb8d-d4c9-41d6-a5c0-2bbb786b0644","resolution":{"observed_at":"2026-08-15T22:51:43.665298Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2107.03374","last_updated":"2021-07-14T17:16:02Z","snapshot_observed_at":"2026-08-08T11:58:24.516369Z","submitted_at":"2021-07-07T17:41:24Z","title":"Evaluating Large Language Models Trained on Code","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2107.03374","snapshot_observed_at":"2026-08-15T22:51:43.669604Z","title":"Evaluating Large Language Models Trained on Code,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.669604Z"},"links":{"cited_paper":"/paper/2107.03374","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:acc9587580415b0ee3aff26a22fc23a46c9fc16f5366af806acaf99939871359","observation_id":"e155d444-e39c-477e-881b-6ff118465fc2","resolution":{"observed_at":"2026-08-15T22:51:43.669604Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2406.11931","last_updated":"2024-06-17T13:51:35Z","snapshot_observed_at":"2026-08-14T04:42:19.578053Z","submitted_at":"2024-06-17T13:51:35Z","title":"DeepSeek-Coder-V2: Breaking the Barrier of Closed-Source Models in Code Intelligence","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2406.11931","snapshot_observed_at":"2026-08-15T22:51:43.673419Z","title":"DeepSeek-Coder-V2: Breaking the Barrier of Closed- Source Models in Code Intelligence,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.673419Z"},"links":{"cited_paper":"/paper/2406.11931","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:c05a96d9e7aa3e12d729724e9acb773554423e10717b9220478027199c73aa69","observation_id":"65b6ae6f-6e06-4f47-a3e8-de82948dc3ae","resolution":{"observed_at":"2026-08-15T22:51:43.673419Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2211.15533","last_updated":"2022-11-20T18:15:30Z","snapshot_observed_at":"2026-08-16T16:14:44.169279Z","submitted_at":"2022-11-20T18:15:30Z","title":"The Stack: 3 TB of permissively licensed source code","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2211.15533","snapshot_observed_at":"2026-08-15T22:51:43.677253Z","title":"The Stack: 3 TB of permissively licensed source code,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.677253Z"},"links":{"cited_paper":"/paper/2211.15533","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:0c4eb6326cdfa37793385bbec439bb03ad55a33980ab586d380a6e887b1e01f8","observation_id":"418c6c8d-fa17-4194-bada-7272cbaa08ba","resolution":{"observed_at":"2026-08-15T22:51:43.677253Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.203887Z","title":"An Introduction to Microsoft Copilot,","venue":null,"work_id":"5ced7e19-39a7-48a0-bd26-c0aa6fb0ce46","year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.681786Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:61844213984485e1b16ff4832373bbdfc4e9884eed9183cccc2da95892bee241","observation_id":"960f7c70-d712-4862-80ff-5bc1b3ab6227","resolution":{"observed_at":"2026-08-15T22:51:44.207293Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2308.12950","last_updated":"2024-01-31T19:47:26Z","snapshot_observed_at":"2026-08-18T03:59:39.242039Z","submitted_at":"2023-08-24T17:39:13Z","title":"Code Llama: Open Foundation Models for Code","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2308.12950","snapshot_observed_at":"2026-08-15T22:51:43.685004Z","title":"Code Llama: Open Foundation Models for Code,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.685004Z"},"links":{"cited_paper":"/paper/2308.12950","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:d1b2bb3aa1fdcbf49798f65e48a5fd46f9b0a9692229a111323142ff7c3ef8d8","observation_id":"be0eb067-da92-430d-8aee-d71ace00702d","resolution":{"observed_at":"2026-08-15T22:51:43.685004Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2303.08774","last_updated":"2024-03-04T06:01:33Z","snapshot_observed_at":"2026-08-17T09:58:46.058102Z","submitted_at":"2023-03-15T17:15:04Z","title":"GPT-4 Technical Report","version":6},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2303.08774","snapshot_observed_at":"2026-08-15T22:51:43.688902Z","title":"GPT-4 Technical Report,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.688902Z"},"links":{"cited_paper":"/paper/2303.08774","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:efa0d18213573cab0ea4fe5e0764a3b77c73f6ddfc5b032e01dc5486203e071a","observation_id":"3922a23f-1159-47b9-aba3-f8b1b0f22f4e","resolution":{"observed_at":"2026-08-15T22:51:43.688902Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2401.12224","last_updated":"2023-12-28T15:09:14Z","snapshot_observed_at":"2026-08-17T19:51:18.038880Z","submitted_at":"2023-12-28T15:09:14Z","title":"LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2401.12224","snapshot_observed_at":"2026-08-15T22:51:43.692386Z","title":"LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.692386Z"},"links":{"cited_paper":"/paper/2401.12224","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:9649e315a501d02fc5f38a4b4881398f02b00be48f6db38537cff0a8711e86a5","observation_id":"43c4a1c1-4cdf-498d-98c2-c0a797877643","resolution":{"observed_at":"2026-08-15T22:51:43.692386Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.192508Z","title":"VeriGen: A Large Language Model for Cerilog Code Generation,","venue":null,"work_id":"caf426f8-fd7c-4b0a-820a-e9bc7c890605","year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.696039Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:e6c8a23bb4ba6e17af573d8b5e89e9fa063e5ec18e1f3f4931ccdb1e5f6ecaba","observation_id":"cd28e480-316f-4895-aa37-fd399e30b588","resolution":{"observed_at":"2026-08-15T22:51:44.196373Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.180985Z","title":"Chip-Chat: Chal- lenges and Opportunities in Conversational Hardware Design,","venue":null,"work_id":"7ad46736-8ea2-449b-ab16-b4ed074a2979","year":2023},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.699795Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:67fb3e336a201c906c6b1be092b6f3ac138e0a07d0d6518478a9e861e6c0aa46","observation_id":"b0fa4bf3-d8d0-4fed-b6be-c724899d14dd","resolution":{"observed_at":"2026-08-15T22:51:44.185680Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:43.703428Z","title":"ChipGPT: How far are we from natural language hardware design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.703428Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:33f3d73a2fd0bf27202e9f5af56c6c51b3db57acf9427d0f0e68f9c77e7a27b5","observation_id":"84c610c4-4da1-4eb5-9dcf-11d490ad49a9","resolution":{"observed_at":"2026-08-15T22:51:43.703428Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2407.10424","last_updated":"2025-05-11T07:35:24Z","snapshot_observed_at":"2026-08-16T13:34:17.701991Z","submitted_at":"2024-07-15T03:57:20Z","title":"CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2407.10424","snapshot_observed_at":"2026-08-15T22:51:43.706606Z","title":"CodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.706606Z"},"links":{"cited_paper":"/paper/2407.10424","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:8af266cd8f1c2888a285ecdc9ab9cd8bd667dd2b5ea057f5265da26ce7d670bb","observation_id":"11fccd4a-aa20-4d6e-8ca8-b79bc7e4474e","resolution":{"observed_at":"2026-08-15T22:51:43.706606Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.169236Z","title":"RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open- Source Dataset and Lightweight Solution,","venue":null,"work_id":"3d26fc68-5451-49ba-a0fb-2f79bfb25bc4","year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.710007Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:567888379b1cfc75cf33b072c70a4d411db6e3ad9ddd2b2da806d40a3ace219b","observation_id":"1d927ec2-41e9-4e18-8215-44defa485480","resolution":{"observed_at":"2026-08-15T22:51:44.173157Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2402.03375","last_updated":"2024-05-02T09:18:21Z","snapshot_observed_at":"2026-08-16T21:48:00.089413Z","submitted_at":"2024-02-03T08:00:12Z","title":"BetterV: Controlled Verilog Generation with Discriminative Guidance","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2402.03375","snapshot_observed_at":"2026-08-15T22:51:43.713325Z","title":"BetterV: Con- trolled Verilog Generation with Discriminative Guidance,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.713325Z"},"links":{"cited_paper":"/paper/2402.03375","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:76bd762c5d843258638877a0537a36ee276c291cc0a5be50093f49f30864567f","observation_id":"1fd0b58e-57a0-4f39-8278-e9d937cc789c","resolution":{"observed_at":"2026-08-15T22:51:43.713325Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2407.18271","last_updated":"2025-04-19T09:25:52Z","snapshot_observed_at":"2026-08-18T04:28:16.734865Z","submitted_at":"2024-07-21T11:25:21Z","title":"Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning","version":4},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2407.18271","snapshot_observed_at":"2026-08-15T22:51:43.716862Z","title":"Large Language Model for Verilog Generation with Golden Code Feedback,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.716862Z"},"links":{"cited_paper":"/paper/2407.18271","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:c046ec9f63baa3b5691ce50c97af4c3f37423aef709c34a0d970412e92c3dc34","observation_id":"e689daf8-3357-4ab3-8f78-b9e4b0775f40","resolution":{"observed_at":"2026-08-15T22:51:43.716862Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.04887","last_updated":"2024-06-04T19:12:48Z","snapshot_observed_at":"2026-08-16T21:50:25.774677Z","submitted_at":"2023-11-08T18:46:39Z","title":"AutoChip: Automating HDL Generation Using LLM Feedback","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.04887","snapshot_observed_at":"2026-08-15T22:51:43.720426Z","title":"AutoChip: Automating HDL Generation Using LLM Feedback,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.720426Z"},"links":{"cited_paper":"/paper/2311.04887","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:fe96002960fbeb3bd11425fcfc309f2d61c6e2f3101f955950d26b8ae1b44de7","observation_id":"d0021637-78e9-473e-8172-c6f5225591c5","resolution":{"observed_at":"2026-08-15T22:51:43.720426Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.158779Z","title":"RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Model,","venue":null,"work_id":"3bbe72ca-1f5b-4d4d-8efc-75a4140139fa","year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.723834Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:4081c7aaee222a5334fc1e4d7c49d8c9657d05fa3de6f46bd6bc5477e2066487","observation_id":"3316d6eb-05fc-418b-b462-6d9b0caeff19","resolution":{"observed_at":"2026-08-15T22:51:44.162507Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.147399Z","title":"OpenAI, Microsoft want court to toss lawsuit accusing them of abusing open-source code,","venue":null,"work_id":"dc21fcc1-6ff9-4c20-a261-c6fd1ed6268e","year":null},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.727302Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:78603e6a7c33c4c0bb903443a35dfff2aa55c6a0831cbd636d77c06880012c8a","observation_id":"b6529a4a-b049-4c0e-b13c-58b1405a2b39","resolution":{"observed_at":"2026-08-15T22:51:44.151317Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.125965Z","title":"RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation,","venue":null,"work_id":"148fcfda-73f4-49f5-a03e-d8bdaff6a081","year":2010},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.734169Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:103a24630ccbdd4e6bddc9863faf664030ba2a39336ad2cead78445d64dbcb43","observation_id":"90a73e50-359e-4396-8e09-d758f719abb1","resolution":{"observed_at":"2026-08-15T22:51:44.129864Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2402.09363","last_updated":"2024-06-04T21:07:11Z","snapshot_observed_at":"2026-08-16T21:51:44.331298Z","submitted_at":"2024-02-14T18:09:53Z","title":"Copyright Traps for Large Language Models","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2402.09363","snapshot_observed_at":"2026-08-15T22:51:43.737597Z","title":"Copyright Traps for Large Language Models,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.737597Z"},"links":{"cited_paper":"/paper/2402.09363","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:2425091defc7da8f55c7147a7fe518910405e55e86f619663c358ead62341e4a","observation_id":"1f2837d5-946d-44c9-b09b-752a7f27fb26","resolution":{"observed_at":"2026-08-15T22:51:43.737597Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.113355Z","title":"Beyond Fair Use: Legal Risk Evaluation for Training LLMs on Copyrighted Text,","venue":null,"work_id":"26384746-f95f-481f-92a5-7135e651d367","year":2023},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.741184Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:cf027011c0c13a34d0f84009379ed175409d2f7c408a0cbe458f62bc8ddb925f","observation_id":"e4cebff8-44d3-43bd-bc92-276f1f76ee86","resolution":{"observed_at":"2026-08-15T22:51:44.117315Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.101201Z","title":"Ongoing lawsuits could affect everyone who uses generative AI,","venue":null,"work_id":"a6785be6-93ea-460e-a1a0-5e4811c51300","year":2023},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.744390Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:d4e65a85d6c45ae13958b25129fb4db51bdf6d60d721ee197713e445ee916e69","observation_id":"fdc722ba-38e0-4edb-8f49-89719eb46b7d","resolution":{"observed_at":"2026-08-15T22:51:44.105083Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.089554Z","title":"Ex- ploring Memorization and Copyright Violation in Frontier LLMs: A Study of the New York Times v. OpenAI 2023 Lawsuit,","venue":null,"work_id":"5b507224-5b94-4e2f-b232-8d86dc727d25","year":2023},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.747741Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:400caaee6f9a80a2a9935f2faca7b15f78acd34657a38f2443e52393e39be41f","observation_id":"4fc04375-7e64-4d51-b3e1-57c668ba7cea","resolution":{"observed_at":"2026-08-15T22:51:44.093635Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2401.00676","last_updated":"2024-01-01T06:04:52Z","snapshot_observed_at":"2026-08-16T21:51:44.945526Z","submitted_at":"2024-01-01T06:04:52Z","title":"Digger: Detecting Copyright Content Mis-usage in Large Language Model Training","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2401.00676","snapshot_observed_at":"2026-08-15T22:51:43.751139Z","title":"Digger: Detecting copyright content mis-usage in large language model training,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.751139Z"},"links":{"cited_paper":"/paper/2401.00676","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:9b27c0ebe11a4d49cde86a9af4d6999350c67493028bf75e0030b0727d488c1b","observation_id":"f5f49f02-ffca-4675-8691-cc3007278d67","resolution":{"observed_at":"2026-08-15T22:51:43.751139Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2406.12975","last_updated":"2024-08-21T11:57:05Z","snapshot_observed_at":"2026-08-16T14:06:33.074285Z","submitted_at":"2024-06-18T18:00:03Z","title":"SHIELD: Evaluation and Defense Strategies for Copyright Compliance in LLM Text Generation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2406.12975","snapshot_observed_at":"2026-08-15T22:51:43.755089Z","title":"SHIELD: Evaluation and Defense Strategies for Copyright Compliance in LLM Text Generation,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.755089Z"},"links":{"cited_paper":"/paper/2406.12975","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:ef595f9ff7782e27c2789ff7d0e593024751611c2d2b74ce8b27aa1395fa28b4","observation_id":"a82ffeb2-6c12-4269-95e3-314ae6dc2ca2","resolution":{"observed_at":"2026-08-15T22:51:43.755089Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.078500Z","title":"RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model,","venue":null,"work_id":"3ab27986-a671-488e-b0d4-93971935a98b","year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.758917Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:4a79ac65372a5e9550657a838db4afa33ad5bd455aa351a9ca6d10a7e2247d73","observation_id":"fcf7d3ba-9508-4e30-952e-36c64297413a","resolution":{"observed_at":"2026-08-15T22:51:44.082192Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2306.14027","last_updated":"2024-07-09T21:08:06Z","snapshot_observed_at":"2026-08-16T15:21:26.056227Z","submitted_at":"2023-06-24T17:44:36Z","title":"(Security) Assertions by Large Language Models","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2306.14027","snapshot_observed_at":"2026-08-15T22:51:43.762513Z","title":"LLM-assisted Generation of Hardware Assertions,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.762513Z"},"links":{"cited_paper":"/paper/2306.14027","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:ff6d9c730f3360d6f3b7b0c0097126fa7ce41d4222304495a7ef254f5905bcab","observation_id":"e7c2f607-8075-41d9-8bef-abd5e200b38d","resolution":{"observed_at":"2026-08-15T22:51:43.762513Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.067392Z","title":"OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation,","venue":null,"work_id":"3136dfed-5b64-4be0-9453-58651919e597","year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.766105Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:30a1a5d1b4ade6918fff0847aa260a641308476e819d719e7372b787d5907d8f","observation_id":"2384d7af-efa1-4a07-8624-76b90a74115f","resolution":{"observed_at":"2026-08-15T22:51:44.071228Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2402.03289","last_updated":"2024-02-05T18:47:04Z","snapshot_observed_at":"2026-08-16T21:51:43.805261Z","submitted_at":"2024-02-05T18:47:04Z","title":"Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2402.03289","snapshot_observed_at":"2026-08-15T22:51:43.769340Z","title":"Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.769340Z"},"links":{"cited_paper":"/paper/2402.03289","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:43de9abdde94aec7063230a898bebed03270b903360fd55cc11485adb8295dee","observation_id":"2f8462ce-1e04-469e-b16c-869cb2530b21","resolution":{"observed_at":"2026-08-15T22:51:43.769340Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2409.12993","last_updated":"2025-02-06T21:39:27Z","snapshot_observed_at":"2026-08-16T21:47:36.142329Z","submitted_at":"2024-09-19T12:15:55Z","title":"CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2409.12993","snapshot_observed_at":"2026-08-15T22:51:43.773049Z","title":"CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by- Construction Non-Textual Representations and Targeted Code Repair,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.773049Z"},"links":{"cited_paper":"/paper/2409.12993","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:5d37fced64c67e00a4e3c2ffefe8db4ccd1f756336bc5dc48a90137ac998080b","observation_id":"7b72accb-96ea-4b8d-b311-cf5b0536a3c0","resolution":{"observed_at":"2026-08-15T22:51:43.773049Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2407.16237","last_updated":"2024-09-02T07:25:21Z","snapshot_observed_at":"2026-08-16T21:47:33.564940Z","submitted_at":"2024-07-23T07:22:25Z","title":"OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2407.16237","snapshot_observed_at":"2026-08-15T22:51:43.776823Z","title":"OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.776823Z"},"links":{"cited_paper":"/paper/2407.16237","citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:9f6678015ff74dfaf4311cd6b5dadd6e0a998648713a33a721d8864add054264","observation_id":"1ffe184e-cef1-4348-a5bc-ed7966828962","resolution":{"observed_at":"2026-08-15T22:51:43.776823Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.053784Z","title":"GNN4IP: Graph Neural Network for Hardware Intellectual Property Piracy Detec- tion,","venue":null,"work_id":"36ce9e26-fad6-4a97-afe1-8a9350134c7f","year":2021},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.780308Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:1141dbb7fb04900fa7dd8c48331fbe08f97599356779f61d35c3a111508111f6","observation_id":"1a22c5ef-95d6-4c4c-99ee-7e58fbf619ec","resolution":{"observed_at":"2026-08-15T22:51:44.059392Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-15T22:51:44.136878Z","title":"Available: https://www.reuters.com/legal/litigation/ openai-microsoft-want-court-toss-lawsuit-accusing-them-abusing-open-source-code-2023-01-27/","venue":null,"work_id":"3f0f39d2-c47a-4e47-9a5d-51055c5cdc55","year":2023},"citing_paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs","version":2},"reference_index":2023,"source":"pdf_text","source_observed_at":"2026-08-15T22:51:43.730840Z"},"links":{"citing_paper":"/paper/2505.06096"},"observation_digest":"sha256:2df2b007831dfa671738169fa8a3836056c77fee068a0f997ca937cdeeed158c","observation_id":"e0f3a494-29c1-4bf3-afe3-f1f9df99c72b","resolution":{"observed_at":"2026-08-15T22:51:44.140437Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2505.06096","last_updated":"2025-06-30T19:58:46Z","latest_version":2,"primary_category":"cs.AI","snapshot_observed_at":"2026-08-18T15:26:36.107626Z","submitted_at":"2025-05-09T14:44:07Z","title":"Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs"},"reference_resolution":{"displayed":36,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":19,"verified_exact":0,"verified_fuzzy":17},"total_outbound_references":36},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-18T06:34:40.430872+00:00","source":"crossref"},{"observed_at":"2026-08-18T06:34:34.496301+00:00","source":"retraction_watch"}],"thesis":"As of 18 August 2026, this Paper Citation Record lists 36 of 36 outbound references and 0 inbound Pith citation observations for arXiv:2505.06096."}