{"as_of":"2026-08-08T07:22:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:3207928ff625d4e7fd827d8f0b3fdd54a637a26e33e9688991116a645638a757","coverage":[{"denominator":36,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":36,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-07T05:54:31.736128Z","state":"measured"},{"denominator":36,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":36,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-08T06:32:00.761636+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2506.06817/citation-record","integrity":"/paper/2506.06817/integrity","json":"/paper/2506.06817/citation-record.json","paper":"/paper/2506.06817"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.330972Z","title":"Soft-core processors for embedded systems,","venue":null,"work_id":"a93a622e-dac1-4a47-904f-3f3b250b2071","year":2006},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.590893Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:37977cde2dfb53589d09c88a4e8a3e2b628441a3f30e2f9ea6872dd056b3ef12","observation_id":"025a6956-e960-4840-b430-65fbb46038c2","resolution":{"observed_at":"2026-08-07T05:54:32.335199Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:31.595955Z","title":"Dealing with categorical and integer-valued variables in Bayesian Optimization with Gaussian processes,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.595955Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:c9c48ff496f698f792be91ee47df19c3f7387c0270d6047321853cf7f5597f23","observation_id":"8fa1d02e-7604-49ac-b5c1-784b96e1b750","resolution":{"observed_at":"2026-08-07T05:54:31.595955Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:31.600318Z","title":"BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.600318Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:baa18fbcf4eee4e597ae76bb2edd4cb4377876adfe9d7ae3fa4f180f2ba98015","observation_id":"eeaee6f0-8bc8-493a-8bde-8070512db62b","resolution":{"observed_at":"2026-08-07T05:54:31.600318Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.317559Z","title":"Boomerang: Physical-Aware De- sign Space Exploration Framework on RISC-V SonicBOOM Microar- chitecture,","venue":null,"work_id":"eafe3704-0058-4125-a627-fe6bad7428d6","year":2023},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.605124Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:56070f1d2f166d3731255a7d3fc25193ff115ccfa6327b3a846cfb1864e84b55","observation_id":"4e723f3c-9903-4ed1-a453-f827d23c5e1c","resolution":{"observed_at":"2026-08-07T05:54:32.321924Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.304064Z","title":"Taking the human out of the loop: A review of Bayesian optimization,","venue":null,"work_id":"88dce73a-51ce-40f6-a729-c28b9a9e3cb7","year":2015},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.609320Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:ab8a2fbf4a6542343e0b0b1a704674fd03fe049e65f461be240b2fbfe1702d52","observation_id":"093a2fe3-5332-4e63-bc03-c70e60b048ca","resolution":{"observed_at":"2026-08-07T05:54:32.308449Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:31.613713Z","title":null,"venue":null,"work_id":null,"year":2006},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.613713Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:b950feedcc4519d83f4dc1e0b8ce371a9c56fe375188fce382056d190093d360","observation_id":"5e423064-4963-400c-857c-d1c144d88fae","resolution":{"observed_at":"2026-08-07T05:54:31.613713Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.282744Z","title":"FIST: A feature-importance sampling and tree-based method for automatic design flow parameter tuning,","venue":null,"work_id":"8a6ab0b5-e159-4e64-a408-78d00f902f46","year":2020},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.618348Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:0db6f89c0035a5c8a9054339b2b2b5931ded030efb0fb6d6e4f951f27db187f3","observation_id":"db419efa-ad8c-487b-af64-36f47f07c598","resolution":{"observed_at":"2026-08-07T05:54:32.287111Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.270383Z","title":"Exploring machine learning adoption in customisable processor design,","venue":null,"work_id":"7ffe2942-57d5-4834-8b76-3c8f481c61a9","year":2023},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.622415Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:fd8a2b8a151aaa270124f87e5820982b2468735ffde38c881f6969884051d120","observation_id":"2b8742db-05dc-4471-9bbb-b741b8da794f","resolution":{"observed_at":"2026-08-07T05:54:32.274484Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.257728Z","title":"Is Vanilla Bayesian Optimization Enough for High-Dimensional Architec- ture Design Optimization?","venue":null,"work_id":"f606accf-8f45-407e-9ac2-64fb0647098d","year":2024},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.626356Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:4ec26730afa3fec15ed678ce13c65ff5dcf788ecd9945e9327f68e234933140f","observation_id":"752c403b-1fc9-4fbc-97c0-bcf7aa91bede","resolution":{"observed_at":"2026-08-07T05:54:32.261975Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.244512Z","title":"Resource-Constraint Bayesian Optimiza- tion for Soft Processors on FPGAs,","venue":null,"work_id":"9e39e56c-fb21-4fad-8fe7-a7a96ce0fbb9","year":2024},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.630434Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:de8bfaddde1eca2ba0506a541f1b8b4e0085a0b421fe0c5e96eea2c0f5fa32ac","observation_id":"742571bc-2bae-4d75-95b9-06711f7e7fdb","resolution":{"observed_at":"2026-08-07T05:54:32.248612Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.231981Z","title":"AMG: Automated Efficient Ap- proximate Multiplier Generator for FPGAs via Bayesian Optimization,","venue":null,"work_id":"449c0588-7cfd-45c0-97a1-140119d52c81","year":2023},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.634317Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:f5a784c3d3c9fda2b91cb424bd161363690c3d122c00e45d00f77b4629364894","observation_id":"692a6419-a938-4f5a-a5d8-1a82dba2339a","resolution":{"observed_at":"2026-08-07T05:54:32.236126Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.219644Z","title":"Layer-Specific Optimization for Mixed Data Flow With Mixed Precision in FPGA Design for CNN- Based Object Detectors,","venue":null,"work_id":"cdc0c89e-48c4-41d5-8f15-50e0022e1164","year":2021},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.638522Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:3661d7064876fca924e2ce4725c14faaaea0dc62d1fca17657a8b5ab98b9d697","observation_id":"3b44525a-a080-454b-89ee-b42d89ecdf28","resolution":{"observed_at":"2026-08-07T05:54:32.223852Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.206221Z","title":"Graebo: Fpga general routing architecture exploration via Bayesian optimization,","venue":null,"work_id":"225485ca-d4c8-4bcb-b8d9-882ca428ff81","year":2022},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.642363Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:d61f91053585131a4e0e75ea0d64a56279d2d41b184eb2be49dd605ceeeb89a2","observation_id":"fc842d7a-42b0-443e-999c-2f017babee7a","resolution":{"observed_at":"2026-08-07T05:54:32.210673Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.193059Z","title":"Multi-objective design space exploration for high-level synthesis via Bayesian optimization,","venue":null,"work_id":"2b6eef15-d6cd-4ba5-a515-e6f3100eb2d9","year":2023},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.646224Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:588c5d24cc5c199ffa8cfdaf8f413173e9511be55875a6d9948b5f8f738fa0a7","observation_id":"04c2b63f-6778-481e-a6af-02d80a3e73c4","resolution":{"observed_at":"2026-08-07T05:54:32.197427Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.180094Z","title":"Hgbo-dse: Hierarchical gnn and Bayesian optimization based hls design space exploration,","venue":null,"work_id":"f48a83bd-2066-4d23-aa77-0d2cd78961ac","year":2023},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.650182Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:ed88ca33d701c792399f937bbdad3413b3ec9c10feac7131f15cb8f9e7e177ec","observation_id":"9eeb6ed5-e7bf-49ed-ae05-8dabb4f0cdf1","resolution":{"observed_at":"2026-08-07T05:54:32.184362Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1012.2599","last_updated":"2010-12-12T22:53:04Z","snapshot_observed_at":"2026-07-06T02:20:34.514024Z","submitted_at":"2010-12-12T22:53:04Z","title":"A Tutorial on Bayesian Optimization of Expensive Cost Functions, with Application to Active User Modeling and Hierarchical Reinforcement Learning","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1012.2599","snapshot_observed_at":"2026-08-07T05:54:31.654031Z","title":"A Tutorial on Bayesian Optimization of Expensive Cost Functions, with Application to Active User Modeling and Hierarchical Reinforcement Learning,","venue":null,"work_id":null,"year":2010},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.654031Z"},"links":{"cited_paper":"/paper/1012.2599","citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:1696da4a9196515c8a2845999c2b2f136b765ab4702a45320c0d1d71e06b1060","observation_id":"84ca6b91-d4ed-4d9c-91a5-10b250dfd4a7","resolution":{"observed_at":"2026-08-07T05:54:31.654031Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.167272Z","title":"A software package for sequential quadratic programming,","venue":null,"work_id":"c0a63087-9f78-4802-8abb-d240e259403e","year":1988},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.658411Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:1ed33f8eb75d6b27a929cae16e408219252e61826480135a5ab6ac1a26d13486","observation_id":"96fff061-c53f-43b2-b54a-a92f91f7909e","resolution":{"observed_at":"2026-08-07T05:54:32.171601Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.154222Z","title":"An Interior Point Algorithm for Large-Scale Nonlinear Programming,","venue":null,"work_id":"e7bccf64-250c-4639-acb5-5c32676233b1","year":1999},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.662375Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:b16f933df2afa3960521829ea1bf7e04a1c7c64bd53955897fbbd1aa81e222f7","observation_id":"c3fdcb4a-da2e-4c74-a2f8-28d93a60787f","resolution":{"observed_at":"2026-08-07T05:54:32.158577Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.141076Z","title":"Taking the Human Out of the Loop: A Review of Bayesian Optimiza- tion,","venue":null,"work_id":"8a5e8401-8a79-4a0f-b884-f48f13fd1b9c","year":2016},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.666306Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:6087b3c8c1384972e28bc17e599203e4acf4e624f7fd3401ec7dcdee56267527","observation_id":"6dbe5375-708d-4ffa-b86c-24e38c0379d5","resolution":{"observed_at":"2026-08-07T05:54:32.145415Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:31.670451Z","title":"Towards agile DNN accelerator design using incremental synthesis on fpgas,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.670451Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:0b3764eca60b013ef33120cba5ac2274f6211145316ff515be88301ad87deb06","observation_id":"888d0f8b-b9d5-4ff0-bd4a-18673a4a244e","resolution":{"observed_at":"2026-08-07T05:54:31.670451Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.128278Z","title":"Efficient design space exploration via statistical sampling and AdaBoost learning,","venue":null,"work_id":"6e78093d-4258-4113-be04-9c0ce9c42ed8","year":2016},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.674388Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:2c7f5167bd192fbc8fae6fe73a6676e6cf2eb95dbc1ebd3769a121c62b83d2b1","observation_id":"6428d566-ec63-48c5-a5d2-b992ff345f5f","resolution":{"observed_at":"2026-08-07T05:54:32.132506Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2003.10870","last_updated":"2020-03-22T14:51:04Z","snapshot_observed_at":"2026-07-06T09:06:58.966574Z","submitted_at":"2020-03-22T14:51:04Z","title":"Cost-aware Bayesian Optimization","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2003.10870","snapshot_observed_at":"2026-08-07T05:54:31.678306Z","title":"Cost-aware Bayesian optimization,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.678306Z"},"links":{"cited_paper":"/paper/2003.10870","citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:2e05e1cccae484669afd28b51b461e3ea2cb6a18ae0fa3add68dd286c62f690b","observation_id":"c85c2834-3268-4029-b0a2-a25fe6d63a9a","resolution":{"observed_at":"2026-08-07T05:54:31.678306Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.115287Z","title":"Exploring coremark a benchmark maximizing simplicity and efficacy,","venue":null,"work_id":"04899ec5-026e-412f-ba87-d212cb43d0e9","year":2012},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.682691Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:7c14796ee357da8010cf62d7a2252d55ce43133ecbcde45eca071339ba35f505","observation_id":"c2c21411-9417-4fb6-b7ee-7283c379ae4d","resolution":{"observed_at":"2026-08-07T05:54:32.119376Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"8274.35828","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:31.837748Z","title":"Dhrystone: a synthetic systems programming benchmark,","venue":null,"work_id":"297edb64-0173-49fc-b951-5446f35a01a4","year":1984},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.686749Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:2fcec51216d9df5af1afbfb149252019dec4206e5ccba355dfcca85a7178d32a","observation_id":"0f62c590-aa5b-4d73-97e3-1324dd4a1534","resolution":{"observed_at":"2026-08-07T05:54:31.846608Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.102001Z","title":"riscv-software-src/riscv-tests risc-v,","venue":null,"work_id":"d1b94ceb-25de-47f5-abd9-f921d4b32df4","year":2019},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.690781Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:0a11a07a45d8946f05593deeb0efd4cdbca84d68ac4aad07859613f1e9da8965","observation_id":"f518d967-e757-4ec5-b536-8f1a5b5b2930","resolution":{"observed_at":"2026-08-07T05:54:32.106284Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.089820Z","title":"The Rocket Chip Generator,","venue":null,"work_id":"ef7962e4-0d50-44b6-8937-4bfac80b6ce0","year":2016},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.695670Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:ab2b1070e7e58412f42fb1cd5f911cb32134302a5889da5534c1b97183d04f49","observation_id":"51b3a8fc-1566-4966-bbda-482b38d9d3d5","resolution":{"observed_at":"2026-08-07T05:54:32.093871Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.076849Z","title":"The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameter- ized RISC-V Processor,","venue":null,"work_id":"1ebaaabd-ded8-4ea1-aade-d2281b93fefc","year":2015},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.700096Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:776ce455dfdefd2218b48f2e5547ad35fc9580ed615184e8ba9fd2745bb8b0df","observation_id":"78889dda-8af3-4255-b5e9-6957799f94e2","resolution":{"observed_at":"2026-08-07T05:54:32.081346Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.063798Z","title":"Cores-VeeR-EL2: A RISC-V Core,","venue":null,"work_id":"93bfdbe3-666f-4ac8-86fb-fd11986ab507","year":2024},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.704414Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:76c448e91cfa3f9ff651cb2560634df5b345ae2cefe7c7ab18da4cd4f5d0e3ae","observation_id":"fd9e936c-0c34-4aea-b41b-f0e65dba5dd7","resolution":{"observed_at":"2026-08-07T05:54:32.068006Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.051182Z","title":"Ibex: An embedded 32-bit risc-v cpu core,","venue":null,"work_id":"657aa0fc-b2ca-4090-86c6-d94f851d92b8","year":2021},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.708138Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:99f9f068a9f3adef8968041d3e7b1f2d5830ee95334e53073b274421fff94581","observation_id":"5bf21236-dfbd-4ceb-af83-303164d0a827","resolution":{"observed_at":"2026-08-07T05:54:32.055372Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.037691Z","title":"The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology,","venue":null,"work_id":"14cff055-5671-4248-92f2-9ec46fdfb9bc","year":2019},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.712026Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:651f916264ed13dfd8441e0243f72f63d9a3593f5f0ccffb456c9134b1784b8d","observation_id":"7cb09ff5-0662-4313-a983-5ace9a703c32","resolution":{"observed_at":"2026-08-07T05:54:32.042107Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.023064Z","title":"Can hardware performance counters be trusted?","venue":null,"work_id":"879c7186-7cee-44f3-89fa-5bdee4f9c7b3","year":2008},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.716151Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:2fccd164cc0c6d4dbfcf177a2c765309b95259d5b1a2a7cf80853778e03e97d7","observation_id":"c2915e88-2d84-4645-ac6c-16fdb3c377e2","resolution":{"observed_at":"2026-08-07T05:54:32.027843Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:32.008638Z","title":"Automating Optimiza- tion of Reconfigurable Designs,","venue":null,"work_id":"4cd9f355-e896-4502-ab55-f7f608fec7d1","year":2014},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.720116Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:4d3d52aa3757a9c40dec350639424f44c8fc892c5b8a5540a27934aa0d1b7071","observation_id":"b2234b0d-cad4-4b0e-9238-a3a67afd389b","resolution":{"observed_at":"2026-08-07T05:54:32.012975Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:31.994210Z","title":"Gamma: Automating the HW mapping of DNN models on accelerators via genetic algorithm,","venue":null,"work_id":"e1d4d3ab-c1a3-45d3-a484-cd606cc7a7e8","year":2020},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.724181Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:2b2975b293f95badd8151fced37e7a863e72e4f684bab3950a8bc65559881927","observation_id":"510c32bb-5ca6-443a-8e65-56e6343163ad","resolution":{"observed_at":"2026-08-07T05:54:31.998440Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:31.981100Z","title":"Extended ant colony optimization algorithm for power electronic circuit design,","venue":null,"work_id":"8dc6920e-0268-4ebb-9892-97284044390d","year":2008},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.728093Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:a12a2b3bc4ff3aa05c1f6826eb49ce63772a9ac7c8d01972c943664910792f65","observation_id":"e950939f-83ee-4c74-91d0-06b519345ed6","resolution":{"observed_at":"2026-08-07T05:54:31.985324Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:31.967126Z","title":"Towards automated risc- v microarchitecture design with reinforcement learning,","venue":null,"work_id":"b00c791f-7c22-41ae-b0e5-f2373b1fe698","year":2024},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.731952Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:b86f103106c53761d8476a789172aa1376b70e6b7a2b3e9c646262321e75b87c","observation_id":"7a6ff4a2-1be9-4ad7-a746-f28ea3900610","resolution":{"observed_at":"2026-08-07T05:54:31.971847Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:54:31.953370Z","title":"Selection of the Register File Size and the Resource Allocation Policy on SMT Processors,","venue":null,"work_id":"47bb823e-159b-46b5-b8d7-2286997cf35d","year":2008},"citing_paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-07T05:54:31.736128Z"},"links":{"citing_paper":"/paper/2506.06817"},"observation_digest":"sha256:b90b0b40387aca4636f99fbeb89e2a78d4a9520525c123ea3fa79be69f90099f","observation_id":"ae206edd-0c52-46b2-911c-2b496d2f213a","resolution":{"observed_at":"2026-08-07T05:54:31.957779Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2506.06817","last_updated":"2025-06-07T14:46:40Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-07T05:46:28.272009Z","submitted_at":"2025-06-07T14:46:40Z","title":"ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors"},"reference_resolution":{"displayed":36,"state_counts":{"malformed_identifier":0,"metadata_mismatch":1,"parse_uncertain":0,"unresolved":6,"verified_exact":0,"verified_fuzzy":29},"total_outbound_references":36},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"thesis":"As of 8 August 2026, this Paper Citation Record lists 36 of 36 outbound references and 0 inbound Pith citation observations for arXiv:2506.06817."}