{"as_of":"2026-08-08T02:34:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:8ab3f29fead0cc9678f8d1dd88e87ac9df3cc3eb903d3ac59dfa76845a64900c","coverage":[{"denominator":42,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":42,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-07T05:07:11.578113Z","state":"measured"},{"denominator":42,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":42,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-07T06:34:17.273281+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2506.08842/citation-record","integrity":"/paper/2506.08842/integrity","json":"/paper/2506.08842/citation-record.json","paper":"/paper/2506.08842"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:12.009240Z","title":"Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip,","venue":null,"work_id":"61d8b608-ce90-4600-87bc-8b1dd900df50","year":2015},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:10.582458Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:850a6e94410a84baaa2797948fb7de3eb67312bc653c9e16287f076eb882cb09","observation_id":"afda0a83-7c9e-4389-bec4-e8024fd75538","resolution":{"observed_at":"2026-08-07T05:07:12.012704Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.999260Z","title":"Loihi: A neuromorphic manycore processor with on-chip learning,","venue":null,"work_id":"2b24f8d6-c94e-4580-b9aa-ede3ee0e22dd","year":2018},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:10.696874Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:8f032d85712eee0d14b90067780b2f8b1e2bc360ed53ff81b5537aee34741035","observation_id":"5256863a-ad8f-4b5b-8976-46825229f209","resolution":{"observed_at":"2026-08-07T05:07:12.002821Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.988406Z","title":"S2n2: A fpga accelerator for streaming spiking neural networks,","venue":null,"work_id":"4fa8e6bc-991e-4952-9162-8bb3a44a55dc","year":2021},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:10.821043Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:5d1e825987a4002bc6689d739bda978ee59db3643b553b7feac47a8e3a29454f","observation_id":"ba652d5b-8b58-44e2-8d9d-3417bbab1f2b","resolution":{"observed_at":"2026-08-07T05:07:11.992024Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.977550Z","title":"Neurogrid: A mixed-analog-digital multichip system for large-scale neural simulations,","venue":null,"work_id":"84346dfe-0a6a-407c-9c0a-1a1c233d19b7","year":2014},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:10.995461Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:8d280276110ae18a2bc885ae361e3a4e222929b42d695afc4b033ff078584ae4","observation_id":"2a193455-f0dc-4720-83c8-b6b31159ba42","resolution":{"observed_at":"2026-08-07T05:07:11.981044Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.012571Z","title":"Towards artificial general intelligence with hybrid tianjic chip architecture,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.012571Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:7907eb5410c9a7f4a77dee35c8182da093b46101134697df0b09e5202668eed9","observation_id":"f42adea2-5697-430b-a4b4-3711176c8df4","resolution":{"observed_at":"2026-08-07T05:07:11.012571Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.959767Z","title":"An energy-efficient spiking neural network accelerator based on spatio-temporal redundancy reduction,","venue":null,"work_id":"ab74e700-a33f-4d91-a07b-03d89f81aedf","year":2023},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.152534Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:2cd6e189d037113f5afb1aec7f690e2b19bff202655e3a542e1c1512f716368c","observation_id":"d9e4740d-d73f-4c9a-a9c7-9c842ebab6d7","resolution":{"observed_at":"2026-08-07T05:07:11.963095Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.950116Z","title":"Seenn: Towards temporal spiking early exit neural networks,","venue":null,"work_id":"0d4e6558-8159-4fe3-a2d3-c46d0422dfc0","year":2024},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.272076Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:213285ff980988addc177390b44d1df7fd4781e1f7e837b6829111e51d93ce75","observation_id":"1f191340-2d98-4796-a79f-63ece324cd2a","resolution":{"observed_at":"2026-08-07T05:07:11.953164Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.939939Z","title":"Unleashing the potential of spik- ing neural networks with dynamic confidence,","venue":null,"work_id":"56dca3a8-83a6-46b6-93a7-cef75d9f334c","year":2023},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.370624Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:11e131a5d8a831add6f5a49cb6474295b444a86ab3ad69158461a12d6440aabc","observation_id":"1ba9bab4-e933-4b60-b560-015dbd2c0854","resolution":{"observed_at":"2026-08-07T05:07:11.943693Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.927473Z","title":"Input-aware dynamic timestep spiking neural networks for efficient in-memory computing,","venue":null,"work_id":"5ca92dd9-3f21-4275-8f7e-97f07bf35113","year":2023},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.403316Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:22e7d856cec32ed8087a3ba2da3ec3bee30699eba46fe2c9d0dd3b4dac18872d","observation_id":"8e0ecea5-e1e1-461e-b62c-be21943473a7","resolution":{"observed_at":"2026-08-07T05:07:11.932769Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.916683Z","title":"Topspark: a timestep optimiza- tion methodology for energy-efficient spiking neural networks on au- tonomous mobile agents,","venue":null,"work_id":"685aedcf-0f36-4512-98ba-8761548edf92","year":2023},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.454790Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:e711a2adb8491427fd716d6c46e55dc62e1ce6c1079043a60bb99353d4a99d61","observation_id":"ab05781a-5f88-4121-97e9-4f52297c4f95","resolution":{"observed_at":"2026-08-07T05:07:11.920484Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.905199Z","title":"Diet-snn: A low-latency spiking neural network with direct input encoding and leakage and threshold optimization,","venue":null,"work_id":"e3837d28-9d97-4e71-9f7f-33952c6ea022","year":2021},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.458462Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:3114c3de306c1e0a5f096bb7c4e34979d1045a9a26b116a1949c8517b4c930db","observation_id":"1d68b551-4384-4c7e-8c8a-8603121777d2","resolution":{"observed_at":"2026-08-07T05:07:11.908805Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2110.05929","last_updated":"2021-10-01T22:54:59Z","snapshot_observed_at":"2026-08-06T01:56:44.132297Z","submitted_at":"2021-10-01T22:54:59Z","title":"One Timestep is All You Need: Training Spiking Neural Networks with Ultra Low Latency","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2110.05929","snapshot_observed_at":"2026-08-07T05:07:11.461775Z","title":"One timestep is all you need: Training spiking neural networks with ultra low latency,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.461775Z"},"links":{"cited_paper":"/paper/2110.05929","citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:01c42b53106e483a67d212009b70e024ec0bfc74a834badc4b72d99a95c4b91e","observation_id":"3544fbbc-aced-43a0-88aa-292bef54c0b1","resolution":{"observed_at":"2026-08-07T05:07:11.461775Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.893128Z","title":null,"venue":null,"work_id":"dab071aa-2b44-45d0-afcc-30d16d7ccede","year":2023},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.465467Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:dcc00e8795f101cd00381dd49bb92ca6c217fae63f4aaf51d059b6c45b74fcd9","observation_id":"92b09b23-cee9-4b44-8f5f-49373dd2b1b8","resolution":{"observed_at":"2026-08-07T05:07:11.897908Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.881447Z","title":"Spikeconverter: An efficient conversion framework zipping the gap between artificial neural networks and spiking neural networks,","venue":null,"work_id":"ea3cab72-b144-47e5-9f76-dedc0972544d","year":2022},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.469944Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:2ba472ef100a4ec42516c6f28f766729b9869af886e305661e6f83c6f53aa936","observation_id":"3c89cc0d-eded-4344-b2bf-c7e8aaeeee1b","resolution":{"observed_at":"2026-08-07T05:07:11.885317Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.869451Z","title":"Differen- tiable spike: Rethinking gradient-descent for training spiking neural networks,","venue":null,"work_id":"a1b16877-568e-470f-be2e-ca8df74c143f","year":2021},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.491729Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:95a5e4ccbd2095acbe675e1dbb29d4e3fd3b07116543f9c9d5f18a36ca8e595f","observation_id":"954337ea-ef75-4d44-b421-eb9181784cce","resolution":{"observed_at":"2026-08-07T05:07:11.873376Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.858116Z","title":"Rethinking the performance comparison between snns and anns,","venue":null,"work_id":"101c6e2b-3ddc-47a1-9ae9-aedeb7f0a657","year":2020},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.495042Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:35cd58ba4147d0b422edec22ecb0b61a9797bd89d1aad0203279c6aebf16754b","observation_id":"e7db562b-022c-45c0-8a39-1e5a2f5bf0cc","resolution":{"observed_at":"2026-08-07T05:07:11.861754Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.498432Z","title":"Towards spike-based machine intelligence with neuromorphic computing,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.498432Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:36d3d7fc916a9ab5443932aaa194bb3abf02859455901fb5dd033a05cefbf73d","observation_id":"fa20b879-1c73-4994-99fa-9130ea75f734","resolution":{"observed_at":"2026-08-07T05:07:11.498432Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.501312Z","title":"Parallel time batching: Systolic- array acceleration of sparse spiking neural computation,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.501312Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:59f7e2f135e8173e639f0b314fd07d6f071e7ff0d0ee8e043c012918bc5d4a3e","observation_id":"3d73fc6d-0fb5-4b2f-b87d-3b79b96023fc","resolution":{"observed_at":"2026-08-07T05:07:11.501312Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.833107Z","title":"Skydiver: A spiking neural network accelerator exploiting spatio-temporal workload balance,","venue":null,"work_id":"0355cd14-88b1-430c-a83e-886e9163dea5","year":2022},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.504286Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:87879b13b19f4ac2342287b63105ae015b134a5562a43eb033d9039a417771f4","observation_id":"af1a2db1-9d2c-4a77-9804-9959146caf1c","resolution":{"observed_at":"2026-08-07T05:07:11.836992Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.507323Z","title":"Sato: spiking neural network acceleration via temporal- oriented dataflow and architecture,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.507323Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:35cb3f23e94e83e1255072ec9aff5674ff9ce0e02f17cbf64a51ed931f7af409","observation_id":"c2c01892-3c81-4632-98f5-18e30f948b44","resolution":{"observed_at":"2026-08-07T05:07:11.507323Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.510646Z","title":"Spinalflow: An architecture and dataflow tailored for spiking neural networks,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.510646Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:66358cf66ca604f3f0acbd4d3d852a07cde2aeffa55efe17768727847300ac92","observation_id":"e9c986ec-c010-4894-aa80-cefd253b86a3","resolution":{"observed_at":"2026-08-07T05:07:11.510646Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.808942Z","title":"Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,","venue":null,"work_id":"56a49601-3859-479a-914b-28009fa3d934","year":2016},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.513655Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:d5e9f5e2306ea666b3835a7fd27855dc1b1324bf8e408f3eb1dde65a4403289e","observation_id":"bb30473e-d3d6-48af-a665-01370b9f1596","resolution":{"observed_at":"2026-08-07T05:07:11.812435Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2202.11946","last_updated":"2022-05-15T11:17:43Z","snapshot_observed_at":"2026-07-06T12:41:10.171070Z","submitted_at":"2022-02-24T08:02:37Z","title":"Temporal Efficient Training of Spiking Neural Network via Gradient Re-weighting","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2202.11946","snapshot_observed_at":"2026-08-07T05:07:11.516763Z","title":"Temporal efficient training of spiking neural network via gradient re-weighting,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.516763Z"},"links":{"cited_paper":"/paper/2202.11946","citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:4bad63590a2efacdf9de08be463deb86cdda9aea7ddb94f51d955d3b7161ae99","observation_id":"7fc47fd2-bc39-4f0a-88fe-3eb193813db4","resolution":{"observed_at":"2026-08-07T05:07:11.516763Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.798912Z","title":"Dayan and L","venue":null,"work_id":"84a6df23-6ee6-4141-8b81-c2c8a69d1225","year":2005},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.520154Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:454902ce9632e61869565aa9818d9672d1ea69af93f580a058bd2670aa0e4471","observation_id":"aed45caa-fd32-4cd5-be65-5b62c5178c50","resolution":{"observed_at":"2026-08-07T05:07:11.802451Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.523106Z","title":"Spatio-temporal backpropa- gation for training high-performance spiking neural networks,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.523106Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:60a966a82a7db223c9ece55a4746679e0812a0d1c82b731489fb85d7f0b4092d","observation_id":"eeaecaf9-9d8e-4d4b-8565-c83eb270721a","resolution":{"observed_at":"2026-08-07T05:07:11.523106Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.526068Z","title":"Training deep spiking neural networks using backpropagation,","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.526068Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:19c7f94a37fd28409dd5ab5e43d3d363a064efb3e6cca250110622366fa1cba6","observation_id":"071e52d9-b613-47fb-bb1d-7c3ad7153c79","resolution":{"observed_at":"2026-08-07T05:07:11.526068Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.774836Z","title":"Spikingjelly: An open-source machine learning infrastructure platform for spike-based intelligence,","venue":null,"work_id":"053fc27e-4955-4bf9-89e4-cb7914687d56","year":2023},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.528925Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:64a956078cbc14837e906f13366d4f410a99d1b60ad131ad452c52d8ce701f64","observation_id":"52ab12a5-1535-4c94-8118-c25442320695","resolution":{"observed_at":"2026-08-07T05:07:11.778713Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.532043Z","title":"Adaptive smoothing gradient learning for spiking neural networks,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.532043Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:2bb76a3c5a718a2f22345f4cfbbdba257e374f0619e0490e73a59abba0c596c7","observation_id":"fe629907-df55-49d5-aa81-d150e2446d91","resolution":{"observed_at":"2026-08-07T05:07:11.532043Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.535164Z","title":"Learning multiple layers of features from tiny images,","venue":null,"work_id":null,"year":2009},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.535164Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:27d4c30fe64971ce5ac518dce87779d30f9a3ca1b8b5f43538c76c646c8fe5e2","observation_id":"68f507c3-60b0-49b4-bb5e-6009a7f31524","resolution":{"observed_at":"2026-08-07T05:07:11.535164Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.538400Z","title":"Tiny imagenet visual recognition challenge,","venue":null,"work_id":null,"year":2015},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.538400Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:a8bc66fcd5fabead8f784c16503448ba241112e0614e98995d45acdd6a72fe47","observation_id":"b1d5a7eb-5577-4a6e-a5b7-d37d29e76031","resolution":{"observed_at":"2026-08-07T05:07:11.538400Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"1409.1556","last_updated":"2015-04-10T16:25:04Z","snapshot_observed_at":"2026-07-06T03:53:32.549552Z","submitted_at":"2014-09-04T19:48:04Z","title":"Very Deep Convolutional Networks for Large-Scale Image Recognition","version":6},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1409.1556","snapshot_observed_at":"2026-08-07T05:07:11.541521Z","title":"Very deep convolutional networks for large-scale image recognition,","venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.541521Z"},"links":{"cited_paper":"/paper/1409.1556","citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:f9951d99badead3cc7a1f07177594ad3e60740aec947f602d706a71130667711","observation_id":"2d8d55bb-9597-44b1-8f62-66fe44d0ab7f","resolution":{"observed_at":"2026-08-07T05:07:11.541521Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.544910Z","title":"Deep residual learning for image recognition,","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.544910Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:c3e3e7b77244a6d9301ff49c2be77cf02b8e694a8ce7e62b23110f058047b3c5","observation_id":"499c7f89-8ae2-4099-8f20-faf2fcd2f7b1","resolution":{"observed_at":"2026-08-07T05:07:11.544910Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.548028Z","title":"Going deeper with directly-trained larger spiking neural networks,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.548028Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:b4e8ff3c0088f3673614c18d7150642c0c95c8527a358b5f904bdc4ed11f5411","observation_id":"567ddd2d-f091-4ce5-a037-06abae58c4c0","resolution":{"observed_at":"2026-08-07T05:07:11.548028Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2303.04347","last_updated":"2023-03-08T03:04:53Z","snapshot_observed_at":"2026-08-01T03:12:55.845079Z","submitted_at":"2023-03-08T03:04:53Z","title":"Optimal ANN-SNN Conversion for High-accuracy and Ultra-low-latency Spiking Neural Networks","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2303.04347","snapshot_observed_at":"2026-08-07T05:07:11.551183Z","title":"Optimal ann- snn conversion for high-accuracy and ultra-low-latency spiking neural networks,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.551183Z"},"links":{"cited_paper":"/paper/2303.04347","citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:be078f3a88400cb0cd13520362cbe43e1ef56655f781c692f813674a128bdc25","observation_id":"af039db7-25a9-4ee3-975b-14f1b89780da","resolution":{"observed_at":"2026-08-07T05:07:11.551183Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.729872Z","title":"Spike-thrift: Towards energy-efficient deep spiking neural networks by limiting spiking activity via attention-guided compression,","venue":null,"work_id":"e70fdff5-b807-4693-b46f-5d4cc77e5d65","year":2021},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.554824Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:7fef3cd36b73493fd1fe637bbffe31bc34b8c3a27bde538a52f0bd3d6e163bf7","observation_id":"96b7a740-e0d8-4109-9942-1932d73fd712","resolution":{"observed_at":"2026-08-07T05:07:11.733437Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.558177Z","title":"Temporal effective batch normalization in spiking neural networks,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.558177Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:d6e71f1cc5bba0e0313a5ac9ebc7af7a57db8de76957940217e5d68e2f14ffb0","observation_id":"be6ca48c-1496-4833-b668-5e614d05c0db","resolution":{"observed_at":"2026-08-07T05:07:11.558177Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2206.09449","last_updated":"2022-06-19T16:52:56Z","snapshot_observed_at":"2026-08-04T17:33:57.642873Z","submitted_at":"2022-06-19T16:52:56Z","title":"SNN2ANN: A Fast and Memory-Efficient Training Framework for Spiking Neural Networks","version":1},"cited_work":{"arxiv_id":"2206.09449","doi":null,"metadata_source":"pith","pith_arxiv_id":"2206.09449","snapshot_observed_at":"2026-08-07T05:07:11.610939Z","title":"SNN2ANN: A Fast and Memory-Efficient Training Framework for Spiking Neural Networks","venue":"cs.NE","work_id":"1d2933a7-f13b-45bb-8568-862d7c82c288","year":2022},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.561635Z"},"links":{"cited_paper":"/paper/2206.09449","citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:6a214afbf215c7f68e6a30357d28e3cf31be81ea39ad899f28bc40ec66e36770","observation_id":"325cfbd8-f160-431d-b252-d41a325ce8c5","resolution":{"observed_at":"2026-08-07T05:07:11.616467Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.711411Z","title":"Encoding, model, and architecture: Systematic optimization for spiking neural network in fpgas,","venue":null,"work_id":"904ecc5f-cd7f-444b-b472-c023d2a83b06","year":2020},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.565137Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:33ff33acc96093c1abcc2afeb560526c80c150ebb644a58e5cd75f0dd3b9b1f6","observation_id":"626c470a-9047-41c5-84e0-6aea1b485278","resolution":{"observed_at":"2026-08-07T05:07:11.715229Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.700466Z","title":"The implementation and optimization of neuromorphic hardware for supporting spiking neural networks with mlp and cnn topologies,","venue":null,"work_id":"9ed438c5-f832-4910-9dd8-a3180fc28112","year":2022},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.568403Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:2bce1be6fa51918f3185ce846f5d5a90170db018d642ac247226b916ed1d6179","observation_id":"8f10a9f2-9d73-41bb-b536-43ef34b9c09d","resolution":{"observed_at":"2026-08-07T05:07:11.704404Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.571507Z","title":"An fpga implementation of deep spiking neural networks for low-power and fast classification,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.571507Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:dfd844755d97443292d1dc6105c2ba2e22032f638842a550ef69628208ab72b2","observation_id":"545038dd-5e02-4890-a7e6-b6c10618473f","resolution":{"observed_at":"2026-08-07T05:07:11.571507Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.676975Z","title":"Cerebron: A reconfigurable architecture for spatiotemporal sparse spiking neural networks,","venue":null,"work_id":"d5430da4-e9d9-4560-bcc8-1d177211ad13","year":2022},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.574746Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:d45105ca6e3a5de5635e86fafbedaac6c5a19cbdfa97c3f6d3056bacfd3f721c","observation_id":"6bc946a2-680a-40be-a42a-cab3173f781e","resolution":{"observed_at":"2026-08-07T05:07:11.685924Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:07:11.666658Z","title":"Firefly: A high- throughput hardware accelerator for spiking neural networks with effi- cient dsp and memory optimization,","venue":null,"work_id":"9709ae8f-cd11-49f2-b823-32170311742b","year":2023},"citing_paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design","version":1},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-08-07T05:07:11.578113Z"},"links":{"citing_paper":"/paper/2506.08842"},"observation_digest":"sha256:ed7b62eba68838f0543ecf2734c42f5e4861ae6ae98467d1a6865df9cd900e81","observation_id":"a9047b19-dfe1-4b67-bbde-b222fd7456ea","resolution":{"observed_at":"2026-08-07T05:07:11.670196Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2506.08842","last_updated":"2025-06-10T14:29:02Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-07T04:58:14.354073Z","submitted_at":"2025-06-10T14:29:02Z","title":"STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design"},"reference_resolution":{"displayed":42,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":19,"verified_exact":1,"verified_fuzzy":22},"total_outbound_references":42},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"thesis":"As of 8 August 2026, this Paper Citation Record lists 42 of 42 outbound references and 0 inbound Pith citation observations for arXiv:2506.08842."}