{"as_of":"2026-08-12T04:23:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:7ec5b921c4574255211915c0f54c6ada7d4969ee458f4b3d2ea83556ce906b82","coverage":[{"denominator":30,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":30,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-07T04:27:03.044289Z","state":"measured"},{"denominator":30,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":30,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-11T06:34:44.6726+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2506.10577/citation-record","integrity":"/paper/2506.10577/integrity","json":"/paper/2506.10577/citation-record.json","paper":"/paper/2506.10577"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.358790Z","title":"In: Proceedings of the 56th Annual Design Automation Conference 2019","venue":null,"work_id":"876b9ee7-816e-48a1-a328-daa339beff69","year":2019},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.935412Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:cd62e2d910d52f7121d2658da5307fe298f262a1c0b904e6ad3277832ce44e5a","observation_id":"aea714c1-3d60-4eaf-b543-8598dd3a1d43","resolution":{"observed_at":"2026-08-07T04:27:03.362154Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.349083Z","title":null,"venue":null,"work_id":"d2a0132f-7648-4b7a-8800-9e3b370d12c2","year":2022},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.940412Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:79de9d3017800dd0577d7873dcaec46928f7f90af874ac953db890f1df298ad7","observation_id":"611f7699-f67f-45ad-aab7-a868c5ec90cd","resolution":{"observed_at":"2026-08-07T04:27:03.352494Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.337464Z","title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41(5), 1209–1221 (2021)","venue":null,"work_id":"ed36e72c-cdfc-4f2e-95cb-ab951fb7d25c","year":2021},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.944491Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:d164b43e6d493c84d01c8f9f57aa18cde2efcc5fa6da61d464fffbef61499cb7","observation_id":"d86b4994-daec-4c5b-8c72-123d10e77180","resolution":{"observed_at":"2026-08-07T04:27:03.341837Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.327898Z","title":"Advances in Neural Information Processing Systems 34, 16508–16519 (2021)","venue":null,"work_id":"3f266554-8eb2-435c-abcd-df4b1771e22f","year":2021},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.948417Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:1d3ec1de812291263bf4e87d5b4f3aa0b65d29d56fadfbbf68f296303a98e70e","observation_id":"02371fdb-bbdf-485c-8897-6eb060fef888","resolution":{"observed_at":"2026-08-07T04:27:03.331192Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.318072Z","title":"International Conference on Learning Representations (2023)","venue":null,"work_id":"abedf4dd-1c14-450f-9a02-771db831f901","year":2023},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.952534Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:4699e28f095d728370b58ad943a465eaeb114daa4ffa82d6d9fe2b58a5b760a2","observation_id":"11cbdd93-b6c2-4a6b-bc30-6b89afed765e","resolution":{"observed_at":"2026-08-07T04:27:03.321485Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.307745Z","title":"Advances in Neural Information Processing Systems 30 (2017) 10 GNNs for Automatic Addition of Optimizing Components in PCB Schematics A PREPRINT","venue":null,"work_id":"865dd6d2-5dfb-46ac-aa33-0f5914f66923","year":2017},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.956325Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:d683d8f99a1fec91cdcb3228efbce47524deca4659d5b022b13058a62b07d130","observation_id":"608e60ce-8ec9-484d-bb7d-dd227c2b2897","resolution":{"observed_at":"2026-08-07T04:27:03.312071Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.298099Z","title":"In: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","venue":null,"work_id":"e1ab5dbc-c2d9-49ed-8ed4-e1138a49108f","year":2020},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.960674Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:b24bb8bdecdd8392f05756c17db72994ed55a38729d2aeeb4759c355e56ae110","observation_id":"31db7185-fa49-4e44-bf3e-d04be4f9d41c","resolution":{"observed_at":"2026-08-07T04:27:03.301348Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.288324Z","title":"International Conference on Learning Representations (2020)","venue":null,"work_id":"bd1a8432-9e85-4f98-b92c-c4b6e1ed6f20","year":2020},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.964269Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:55c884c284e039ac1cae353635b895502f65fb9896e2f5aa3d84b1626418e96d","observation_id":"3e79dbc6-5ffc-4247-b42a-cab1dbaf5c23","resolution":{"observed_at":"2026-08-07T04:27:03.291594Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.278906Z","title":"ACM Transactions on Design Automation of Electronic Systems (TODAES) 26(5), 1–46 (2021)","venue":null,"work_id":"7c3b16e6-cfa1-4f19-b659-84b46201fa7e","year":2021},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.967770Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:05ddeb72ce84d11d0abfa11e1c610dcc9e63ff17496ff7d7b20d05f7fde9bd53","observation_id":"c6d54702-37a5-4a57-8393-da5f70f1ae82","resolution":{"observed_at":"2026-08-07T04:27:03.282121Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1611.07308","last_updated":"2016-11-21T11:37:17Z","snapshot_observed_at":"2026-08-06T06:17:37.090691Z","submitted_at":"2016-11-21T11:37:17Z","title":"Variational Graph Auto-Encoders","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1611.07308","snapshot_observed_at":"2026-08-07T04:27:02.971903Z","title":"arXiv preprint arXiv:1611.07308 (2016)","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.971903Z"},"links":{"cited_paper":"/paper/1611.07308","citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:7eab989f7fc12416a22f8f9318d1a6d12062b65c074e1188221324fed9337200","observation_id":"c8d39eb8-e518-4b2e-9f07-271533da75da","resolution":{"observed_at":"2026-08-07T04:27:02.971903Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.269264Z","title":"International Confer- ence on Learning Representations (2017)","venue":null,"work_id":"f46dcae0-19e8-4351-a9d9-0180396f9bd6","year":2017},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.975877Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:7b34a57b26e3bcf63945de41feb23be9728014d72ffa457a8ee2f3b3c1897d50","observation_id":"426df976-36d0-4996-91a3-31bfe49789ad","resolution":{"observed_at":"2026-08-07T04:27:03.272638Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.259811Z","title":"In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","venue":null,"work_id":"518dbbcb-30df-48be-aaac-c19037f4bc6c","year":2020},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.979354Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:ff3170ae8a6b8e126e9442a0b35ae6fd7e15b8478c700de9dcbbcd10fe5cbe83","observation_id":"6241442e-8d48-43b0-9210-7b295ca79300","resolution":{"observed_at":"2026-08-07T04:27:03.262972Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.250260Z","title":"International Conference on Learning Represen- tations (2019)","venue":null,"work_id":"26998942-9f93-4323-b9eb-71fd7126afc6","year":2019},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.982942Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:69635aff34338451da1aacf1b8dbef4ba544001b32c6900ec879da16cafcd0b8","observation_id":"dcec0c9b-5f26-42a1-8bbb-1ddca7571b85","resolution":{"observed_at":"2026-08-07T04:27:03.253611Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.240510Z","title":"Electronics 11(3), 435 (2022)","venue":null,"work_id":"ecc3ff14-861a-443b-aeac-c02d783d1f16","year":2022},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.986804Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:e94578782438c95e635bff342185c180d97524770cabda865096206116eef57f","observation_id":"d305ad01-52e5-4c9c-91e8-a7e0a0a4100b","resolution":{"observed_at":"2026-08-07T04:27:03.243569Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2004.10746","last_updated":"2020-04-22T17:56:07Z","snapshot_observed_at":"2026-08-10T07:39:19.641872Z","submitted_at":"2020-04-22T17:56:07Z","title":"Chip Placement with Deep Reinforcement Learning","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2004.10746","snapshot_observed_at":"2026-08-07T04:27:02.990203Z","title":"arXiv preprint arXiv:2004.10746 (2020)","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.990203Z"},"links":{"cited_paper":"/paper/2004.10746","citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:060a6854e34ba1dd9c5a05dfaf806d53b0c2cc0eda350d174d7a52d73f66317f","observation_id":"f171e03b-9ea3-47ad-a5fa-3f900e14159d","resolution":{"observed_at":"2026-08-07T04:27:02.990203Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.231158Z","title":"Nature 594(7862), 207–212 (2021)","venue":null,"work_id":"90b6f969-3a9a-4e8f-adbd-0126e18b13d5","year":2021},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.994225Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:31a7cb7bbb9ff2ba9c45dc69de38e8f343f2562aedac69d0ad7d7f8cca4cbb32","observation_id":"cc1e1b83-d25f-4e12-8e41-f25fc841c29d","resolution":{"observed_at":"2026-08-07T04:27:03.234575Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1908.10084","last_updated":"2019-08-27T08:50:17Z","snapshot_observed_at":"2026-07-06T08:17:05.681370Z","submitted_at":"2019-08-27T08:50:17Z","title":"Sentence-BERT: Sentence Embeddings using Siamese BERT-Networks","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1908.10084","snapshot_observed_at":"2026-08-07T04:27:02.997726Z","title":"arXiv preprint arXiv:1908.10084 (2019)","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:02.997726Z"},"links":{"cited_paper":"/paper/1908.10084","citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:a7bfd0075812da7e5f14d4b902156522146237763393a26ee8eab7bf50c6e9b2","observation_id":"95ac3b77-87c3-41a0-bb43-cf8ed9ca528c","resolution":{"observed_at":"2026-08-07T04:27:02.997726Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.221976Z","title":"In: 2020 57th ACM/IEEE Design Automation Conference (DAC)","venue":null,"work_id":"f94b4fc8-a904-4541-8b5d-beea969138be","year":2020},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:03.001515Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:9ce6999ac09cfea504ab0d6ace1b7f9a73f9117bc7f0b278bd61a292b6e6079d","observation_id":"64c990cc-f5e9-4e32-8074-e2521c3d3469","resolution":{"observed_at":"2026-08-07T04:27:03.225218Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.212726Z","title":"Neural Computing and Applications 35(16), 12145–12157 (2023)","venue":null,"work_id":"d032e248-7fd8-4f5c-97d9-27a8b95f1d02","year":2023},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:03.004961Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:3c97707b5aceb6779cc98f2bb1e4412895a73734ec0f3b77df84a52a8652e044","observation_id":"ef8fd78f-14fc-49e7-b261-4e1c3ec503a8","resolution":{"observed_at":"2026-08-07T04:27:03.216045Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.202342Z","title":"ACM Transactions on Design Automation of Electronic Systems 28(2), 1–27 (2023)","venue":null,"work_id":"8c045752-6857-4928-b18f-5f1cea206130","year":2023},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:03.008416Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:9ccd3bd2dffe3fa5ec7ab59dee0aa38192f99c6a1e395c806017f23548748e3f","observation_id":"4fe8796f-0317-4d1b-8ba1-11153f5d9c3d","resolution":{"observed_at":"2026-08-07T04:27:03.205835Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.191954Z","title":"In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","venue":null,"work_id":"eacd1b29-2bd4-4764-a8a0-c3e2b6181a42","year":2020},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:03.012521Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:fbf52ce333d458cf4a02f343b8093ef17967303d491c5950b0260604fda3aea2","observation_id":"adade457-3642-412c-b118-f718d686d19e","resolution":{"observed_at":"2026-08-07T04:27:03.195409Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.182423Z","title":"In: Proceedings of the Thirtieth International Joint Conference on Artificial Intelligence (2021)","venue":null,"work_id":"7329deeb-5669-4d56-ace3-aa5f7122db0c","year":2021},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:03.016313Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:8945cbdafdc887f1d0b1fdffb060248e2dbb3b446b880ed70020be101cbde0fc","observation_id":"a98d438b-cbf9-4826-bfa3-cd58d107df10","resolution":{"observed_at":"2026-08-07T04:27:03.185780Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.172217Z","title":"In: 2024 25th International Symposium on Quality Electronic Design (ISQED)","venue":null,"work_id":"2d695d9f-9bc9-4a52-b291-12f01bd65ddd","year":2024},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:03.019739Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:3fd115553f5f179039b491c984e77c26056bf08fd80ce451533b6e07dc2f8adf","observation_id":"eafd59e2-8e9d-49a6-b0a3-b4a9eec76a27","resolution":{"observed_at":"2026-08-07T04:27:03.175767Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.162534Z","title":"International Conference on Learning Representations (2018)","venue":null,"work_id":"a62cd61f-021c-478a-9c57-ade1c533932c","year":2018},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:03.023179Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:6026104f3c7bf8c15ed3b3645e8a17e67b4189aa3d6406f73188fb4290d0e053","observation_id":"b03a2f90-23a4-48a4-9a60-bed09ed82f60","resolution":{"observed_at":"2026-08-07T04:27:03.166170Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.152323Z","title":"In: 2020 57th ACM/IEEE Design Automation Conference (DAC)","venue":null,"work_id":"296ba277-88e6-4e9a-979a-a786682e5c41","year":2020},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:03.026583Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:8b0e0d0430ae42b12271635b0af48978611fe8a7ad1e46536a100fda7be89307","observation_id":"6536d509-b6ed-4a5a-835d-280489e95b92","resolution":{"observed_at":"2026-08-07T04:27:03.156071Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.141571Z","title":"Advances in Neural Information Processing Systems 33, 5776–5788 (2020)","venue":null,"work_id":"a13a34ff-6e1d-4359-ba85-82a98a9e837c","year":2020},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:03.030123Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:8188d44fff71a64b138ea12bffe5b90119acf6b959aa0ac73b101f7e6ad41803","observation_id":"b89cd0d3-2358-4e48-a521-dbba71fa4e4e","resolution":{"observed_at":"2026-08-07T04:27:03.145488Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.131899Z","title":"In: 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","venue":null,"work_id":"c65f61f3-f28d-443c-baab-a947157d0af9","year":2018},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:03.033500Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:95abfd9dfcf16c259cec97e72b81d8b2c9094ed18dba0c44000db564b70e0490","observation_id":"6144a27f-bb19-4e98-b4b7-7566c444395e","resolution":{"observed_at":"2026-08-07T04:27:03.135241Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.121743Z","title":null,"venue":null,"work_id":"74c86297-5c44-4001-850c-5347da187eab","year":2019},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:03.037083Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:e5a4901920ca5932a33825d92b9e5d099bdae8a83cfe5bb1dfe4a014800e4f87","observation_id":"0d64ca83-3d71-468b-93f1-1ae51ef448fb","resolution":{"observed_at":"2026-08-07T04:27:03.125258Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.111577Z","title":"In: Proceedings of the 55th Annual Design Automation Conference","venue":null,"work_id":"1d961108-7c52-4d19-a8fc-8cf3703fbec8","year":2018},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:03.040747Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:9a1f820ece7be2ccfb6e623c46fb2604b4d87e434107bec5074685467270e50a","observation_id":"fb794eda-ef48-489d-927c-ca42058763ce","resolution":{"observed_at":"2026-08-07T04:27:03.115250Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:27:03.099505Z","title":null,"venue":null,"work_id":"d6a5e753-b03c-4974-8d66-c6cd663bfc13","year":2018},"citing_paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-07T04:27:03.044289Z"},"links":{"citing_paper":"/paper/2506.10577"},"observation_digest":"sha256:11277b1d75e6dd4fb2a334057578a84bc43e07db8fd29785671575381e413f3a","observation_id":"72541f48-81de-4853-8173-ab3ba140c814","resolution":{"observed_at":"2026-08-07T04:27:03.104111Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2506.10577","last_updated":"2025-06-12T11:12:18Z","latest_version":1,"primary_category":"cs.LG","snapshot_observed_at":"2026-08-10T08:45:28.908739Z","submitted_at":"2025-06-12T11:12:18Z","title":"Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics"},"reference_resolution":{"displayed":30,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":6,"verified_exact":0,"verified_fuzzy":24},"total_outbound_references":30},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"thesis":"As of 12 August 2026, this Paper Citation Record lists 30 of 30 outbound references and 0 inbound Pith citation observations for arXiv:2506.10577."}