{"as_of":"2026-08-24T03:07:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:7a713e2beaeb970896f90db7baccde53ab2c6c1d4ca532e78cb206d35ab40488","coverage":[{"denominator":74,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":74,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-06T21:02:23.592553Z","state":"measured"},{"denominator":74,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":74,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-23T06:30:58.430688+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2507.01429/citation-record","integrity":"/paper/2507.01429/integrity","json":"/paper/2507.01429/citation-record.json","paper":"/paper/2507.01429"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:26.635321Z","title":"Nullhop: A flexible convolutional neural network accelerator based on sparse representations of feature maps","venue":null,"work_id":"2245e036-1fc2-4093-88b1-c95b9e5c212e","year":2018},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.193942Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:945d7a19c53532d06ef72885737bef87bdc9ca66fb8d13bc4133a1bf26e49bcb","observation_id":"4d5dd491-53ef-468a-9e6f-4c84d8e74023","resolution":{"observed_at":"2026-08-06T21:02:26.712225Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:26.477502Z","title":"A signed binary multiplication technique","venue":null,"work_id":"97dae5e8-4740-4f58-901f-5c1d0ef407d4","year":1951},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.199727Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:03e9e3d2ea05778dafd017ee17baff2738e48af3122925093165c910dad1669f","observation_id":"dd707539-9237-4d7f-9410-1616f3ee1a37","resolution":{"observed_at":"2026-08-06T21:02:26.562737Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:26.350608Z","title":"Skyrmion logic system for large- scale reversible computation","venue":null,"work_id":"85c237a9-8722-42eb-9f3e-dbfccd585b1b","year":2019},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.211162Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:a4223d47669653279dc61c6d3c8f13b9417abbd2b432ef15171276fd5a564de5","observation_id":"b800793b-d039-43e2-92a3-76801a1d31b1","resolution":{"observed_at":"2026-08-06T21:02:26.402353Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:26.185347Z","title":"Flinkcl: An opencl- based in-memory computing architecture on heterogeneous cpu-gpu clusters for big data","venue":null,"work_id":"abc09d88-7666-4fd7-9bc9-38d2d5035501","year":null},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.216620Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:0156bc3f4a7c5bb174c03d86c0b208806dd0b409ccfc048d56e2916f5ab14a39","observation_id":"9356bba0-7b4d-4421-ad40-af895b6c1037","resolution":{"observed_at":"2026-08-06T21:02:26.271551Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.995174Z","title":"IEEE Transactions on Systems, Man, and Cybernetics: Systems 47, 2740–2753","venue":null,"work_id":"5a83cdc5-1cb7-4404-b312-0b6be5b053de","year":null},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.221914Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:a0b28bf3b008c662673667a2e87200eeeeabd24ba98474e959346d022093eac0","observation_id":"d9e25348-bff7-4a55-8486-3758092ad92b","resolution":{"observed_at":"2026-08-06T21:02:26.080771Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.936042Z","title":"Gflink: An in- memory computing architecture on heterogeneous cpu-gpu clusters Choong et","venue":null,"work_id":"38ccc10a-28a4-487f-bb73-be6e07e2d594","year":null},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.227144Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:4418013fac1c7cd542872fec10192945d7948f8311dd4d7ac2a525c387bd3393","observation_id":"3bd61873-1149-4391-9b5f-8ff7c85941f4","resolution":{"observed_at":"2026-08-06T21:02:25.948129Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:23.232753Z","title":"Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.232753Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:c29e51ff5c9011950069fb02cd2becaa5d35c92384217a6c94393c77abf1d29a","observation_id":"7141863d-97c1-4d4d-b5ba-6ae48f7ec1af","resolution":{"observed_at":"2026-08-06T21:02:23.232753Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1145/3358199","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T05:30:23.456663Z","title":"Dwmacc: Accelerating shift-based cnns with domain wall memories","venue":"ACM Transactions on Embedded Computing Systems","work_id":"f9caacf2-7462-45e1-9303-95a89987a209","year":2019},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.237785Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:e63a0956b154efe378221a5cc4ff96819726bc163f86bb4e8afbd184b760e45f","observation_id":"03c84080-5f72-4f19-9143-9b0d5e40f3b7","resolution":{"observed_at":"2026-08-06T21:02:23.747862Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.908574Z","title":"The mnist database of handwritten digit images for machine learning research","venue":null,"work_id":"03d58df0-0baf-4911-b58d-193ba480b971","year":2012},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.243079Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:ca4ca4a8a861893789184025d5f273ec1fd4f5ae2cea6f5576e4223724608cf7","observation_id":"bb3b3e2f-b285-4220-bc04-e11a229abe32","resolution":{"observed_at":"2026-08-06T21:02:25.920285Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2018.82972","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.144700Z","title":"Quantized deep neural networks for energy efficient hardware-based inference, in:201823rdAsiaandSouthPacificDesignAutomationConference (ASP-DAC), pp","venue":null,"work_id":"f5a455f1-c729-4cd3-8717-7b23734f83ba","year":2018},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.248984Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:8440328d075a962c3863ed3c03e3aa765c877d444b8460d2313c7590f439c2ee","observation_id":"55e7c71c-dceb-4521-a9b8-0a9b6f498540","resolution":{"observed_at":"2026-08-06T21:02:25.153335Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2012.21859","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.052786Z","title":"Nvsim: A circuit- level performance, energy, and area model for emerging nonvolatile memory.IEEETransactionsonComputer-AidedDesignofIntegrated Circuits and Systems 31, 994–1007","venue":null,"work_id":"6e2911df-7ad2-4bd0-a655-25eb5ad47ce0","year":2012},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.254302Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:63b79990faa721f8ec52f9cdccaf1f623a259167084384a1158ce28b4c4ee884","observation_id":"ac0657fe-68b3-471c-a183-7455fe0d8467","resolution":{"observed_at":"2026-08-06T21:02:25.062117Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:23.259319Z","title":"Neural cache: Bit-serial in-cache acceleration of deep neural networks, in: 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), pp","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.259319Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:c9ed31acf37d635b05f4dfdac36a6d75cd3a2d77004c91e0c40f4fe614146411","observation_id":"169f9bc8-1c33-427a-99f7-b3b0e8a5c912","resolution":{"observed_at":"2026-08-06T21:02:23.259319Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"1510.00149","last_updated":"2016-02-15T06:25:40Z","snapshot_observed_at":"2026-08-04T16:59:47.843960Z","submitted_at":"2015-10-01T09:03:44Z","title":"Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1510.00149","snapshot_observed_at":"2026-08-06T21:02:23.264761Z","title":"Deepcompression:Compressing deepneuralnetworkswithpruning,trainedquantizationandhuffman coding","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.264761Z"},"links":{"cited_paper":"/paper/1510.00149","citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:34625e862e0d1a1ccecb2fe319a184d90108455c5b94b2ec3fbb74b31d8894a8","observation_id":"17e0a047-7db1-4263-8387-4967db8ce1bf","resolution":{"observed_at":"2026-08-06T21:02:23.264761Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:23.270231Z","title":"Deep residual learning for image recognition, in: 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), pp","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.270231Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:86d7d64b11db400b4cad4d038594e576972a3ef7a0a04c112dfd562d47dbd5b4","observation_id":"bb3a3f19-1e8c-434a-914f-abde25f01035","resolution":{"observed_at":"2026-08-06T21:02:23.270231Z","resolver_source":null,"status":"malformed_identifier"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.880635Z","title":null,"venue":null,"work_id":"802d7de8-7201-4b66-b1d6-8163272da0a3","year":null},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.276314Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:e4bf0d5744c5d131d5fece94967dfa55182ca862c8aa30f773819c2423e5ee8b","observation_id":"c5be0bdf-8e5c-4fad-9f0d-78ec995df8b4","resolution":{"observed_at":"2026-08-06T21:02:25.891145Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1704.04861","last_updated":"2017-04-17T03:57:34Z","snapshot_observed_at":"2026-08-20T09:32:02.065929Z","submitted_at":"2017-04-17T03:57:34Z","title":"MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1704.04861","snapshot_observed_at":"2026-08-06T21:02:23.287394Z","title":"Mobilenets: Effi- cient convolutional neural networks for mobile vision applications","venue":null,"work_id":null,"year":2017},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.287394Z"},"links":{"cited_paper":"/paper/1704.04861","citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:43739768a1cd54ee26493b8019314600fecd2860ea2f933367c405a6ca8f7c62","observation_id":"e9264eb7-fdfa-4655-85bb-5860a408f42d","resolution":{"observed_at":"2026-08-06T21:02:23.287394Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1016/j.sysarc.2020","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:23.714485Z","title":"Essa: An energy-aware bit-serial streaming deep convolutional neu- ral network accelerator","venue":null,"work_id":"fd24bdf9-c86a-4370-9f08-f354a17fc234","year":2020},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.294227Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:52859b43f25e8bd6052cd0512c14466c64001a6eab63568255c8a21d9c379299","observation_id":"546fef08-e1d9-4d3d-bad5-bf753e28d4b1","resolution":{"observed_at":"2026-08-06T21:02:23.719517Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2961.29029","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:24.757395Z","title":"Exploring main memory designbasedonracetrackmemorytechnology,in:2016International Great Lakes Symposium on VLSI (GLSVLSI), pp","venue":null,"work_id":"3abb4f90-eb61-470f-ad42-49e2b397c95f","year":2016},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.300067Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:56a71f90be5b66bd609b8bd6f25105a4d402dc328aede5b714460ddfd5998db3","observation_id":"f024902e-be04-4010-8c3c-d67b00ce5b98","resolution":{"observed_at":"2026-08-06T21:02:24.768353Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1502.03167","last_updated":"2015-03-02T20:44:12Z","snapshot_observed_at":"2026-08-12T21:01:12.961874Z","submitted_at":"2015-02-11T01:44:18Z","title":"Batch Normalization: Accelerating Deep Network Training by Reducing Internal Covariate Shift","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1502.03167","snapshot_observed_at":"2026-08-06T21:02:23.306235Z","title":"Batch normalization: Accelerat- ing deep network training by reducing internal covariate shift","venue":null,"work_id":null,"year":2015},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.306235Z"},"links":{"cited_paper":"/paper/1502.03167","citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:911d0e5e9757459e011be98edb16e0b38ece9f4a4b679421fdc53942cddfce17","observation_id":"c7319b4f-1c25-4760-b9d0-dbb760d625ab","resolution":{"observed_at":"2026-08-06T21:02:23.306235Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:23.312116Z","title":"Quantizationandtrainingofneu- ral networks for efficient integer-arithmetic-only inference, in: 2018 IEEE/CVFConferenceonComputerVisionandPatternRecognition, pp","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.312116Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:2510a0d0d38deda6ec65622b0290022a0b05ddafb5a0c787e9828bf0777d57a9","observation_id":"7630285e-48bc-4b7b-8629-4f9e3d8052b4","resolution":{"observed_at":"2026-08-06T21:02:23.312116Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2019.29116","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:24.563609Z","title":"Accelerator-awarepruningforconvolutionalneural networks","venue":null,"work_id":"06721f55-8f46-4f3d-9147-d824d8187e1b","year":2020},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.317425Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:3b3809ad61db86aadfcbd6cf470124d1e0347bc3ff64956c28c790a7e06f41ea","observation_id":"035096a1-49e1-4546-9150-79bcd6556a54","resolution":{"observed_at":"2026-08-06T21:02:24.572288Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.855952Z","title":"skyrmion, in: 2018 IEEE 7th Non-Volatile Memory Systems and Applications Symposium (NVMSA), IEEE","venue":null,"work_id":"d1f68a89-9ce2-45f7-85bf-393395334d09","year":2018},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.322849Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:92594aab4d18a8b37ec9c817741c6e29e6cd0ffca37c93b911ae4ffde48f41fc","observation_id":"25837cd5-897f-4b59-89f3-22322bcd84b5","resolution":{"observed_at":"2026-08-06T21:02:25.866110Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.830063Z","title":"Compact modeling and evaluation of magnetic skyrmion- basedracetrackmemory","venue":null,"work_id":"260fbd99-e114-4877-b8d2-52816509481d","year":2017},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.328633Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:e5660989c7d7714f015b64d2675c92f0c999df750c12872ac5fa2b8910978097","observation_id":"9a82e51a-0a28-49ac-b337-095074c88c6f","resolution":{"observed_at":"2026-08-06T21:02:25.840515Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.813934Z","title":"Exploiting retraining-basedmixed-precisionquantizationforlow-costdnnaccel- erator design","venue":null,"work_id":"5fa688aa-0113-4c04-bcc0-dcacede180be","year":2020},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.334338Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:1bb960f89bfb97eda521f754c3c9362ab2e5e308363509a1e46c4967f16d1e15","observation_id":"2b0842ca-6d81-4c8f-b601-40426b303b16","resolution":{"observed_at":"2026-08-06T21:02:25.819712Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.799625Z","title":"Heterogeneous dataflow accelerators for multi-dnn work- loads,in:2021IEEEInternationalSymposiumonHigh-Performance Computer Architecture (HPCA), IEEE","venue":null,"work_id":"f2f3ac28-d884-46d2-87f7-2992179a8faf","year":2021},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.339516Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:27609261a96d7eb8acc5652f9e3f2dd195a37b0985464dfd6578cc10bbdf2883","observation_id":"ba7e98cd-fc05-40c0-842c-e582aaef4c98","resolution":{"observed_at":"2026-08-06T21:02:25.803955Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:23.344419Z","title":"Gradient-based learning applied to document recognition","venue":null,"work_id":null,"year":1998},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.344419Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:30acd5cf8f6b2acca39d542fc457b3a6f5cc7ce859242dd9b3c5a5921cb42d0b","observation_id":"4d51e971-8a80-40d8-bdca-4c54a59645b0","resolution":{"observed_at":"2026-08-06T21:02:23.344419Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2017.79532","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:24.474109Z","title":"Lognet:Energy-efficientneuralnetworksusinglogarithmiccomputa- tion, in: 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp","venue":null,"work_id":"db337745-81d3-49b6-bac5-259aec5df943","year":2017},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.349255Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:c7cd7d1d35c0adb0cd676d7017e92b38fbcc11a498d3ed3a8a131138091bfda9","observation_id":"d2221562-5bf0-4d34-afcd-43967cf65678","resolution":{"observed_at":"2026-08-06T21:02:24.482616Z","resolver_source":"raw_fallback","status":"malformed_identifier"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2009.54243","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:24.380762Z","title":"45nm low power cmos logic compatible embedded stt mram utilizing a reverse-connection 1t/1mtj cell, in: 2009 IEEE International Electron Devices Meeting (IEDM), pp","venue":null,"work_id":"092ce5f3-15d5-4798-869f-d4a0ebe494a4","year":2009},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.355954Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:7ac3931939d1aaea65bf52f5005a28f7e3176e30aa4054439b1953b6c15bf1a4","observation_id":"6c1c24e0-f6d0-461a-9884-b071a3d712e9","resolution":{"observed_at":"2026-08-06T21:02:24.389311Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.784977Z","title":null,"venue":null,"work_id":"2a401172-a6ea-4192-b3f9-aa3bcc214d6a","year":null},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.360774Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:19213e42380660924f99f4b7c2d9c3d40b7162e2bc7db7d7b0e8fe1b6b33b3da","observation_id":"e253ea87-9409-42cd-b24c-c8036e37249b","resolution":{"observed_at":"2026-08-06T21:02:25.789714Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.770610Z","title":"Skyrmion devices for memory and logic applications","venue":null,"work_id":"8595315a-2860-4f5c-bad6-dfb0a4116783","year":2021},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.371771Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:1c046ee8c1a357cd8281a830d2388da2791fb592110804a06d4bb984646c0bb3","observation_id":"a029ac4f-76b6-471a-913d-c6e6ac030a2d","resolution":{"observed_at":"2026-08-06T21:02:25.775049Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.754718Z","title":"A novel two- stage modular multiplier based on racetrack memory for asymmet- ric cryptography, in: 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), IEEE","venue":null,"work_id":"d9c74b44-f41b-40e5-aac0-022180199a68","year":2017},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.376931Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:8e27475ffed1964d0947e10e10c277a9d64ede80964c1fe39ffe8e606ad182bc","observation_id":"a11dfb94-7458-43da-8385-2bd533c4fc93","resolution":{"observed_at":"2026-08-06T21:02:25.759436Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.737878Z","title":"An fpga-based hardware emulator for neuromorphic chip with rram","venue":null,"work_id":"f0e77d18-60c9-4e6b-a963-f7b0aab2ff11","year":2018},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.382276Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:1c268c8ff53006a41519389cee2ee0f446aee817370ac8ec98b3c359b5d60f6d","observation_id":"9471dead-e800-4949-b915-6d153664471e","resolution":{"observed_at":"2026-08-06T21:02:25.743553Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.720326Z","title":"Energy efficient in-memory integer multiplication based on racetrack mem- ory, in: 2020 IEEE 40th International Conference on Distributed Computing Systems (ICDCS), IEEE","venue":null,"work_id":"dc04983d-6276-451f-b22e-3cc887b26140","year":2020},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.387685Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:b7834a92246d0cd98aff09770a2481b07d2b1be11b75a6d2ae708c1e0b19a8d6","observation_id":"8d50418c-c5bd-4a9c-9804-05c3165c47cb","resolution":{"observed_at":"2026-08-06T21:02:25.727259Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.704148Z","title":"A racetrack memory based in-memory booth multiplier for cryptography application, in: 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE","venue":null,"work_id":"c0d85ada-3993-4e57-b96b-75bf349fb1bd","year":2016},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.392496Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:37f53a8223079c5d6c5c89bb4e1c2f4b83c82008e7a1076d2b394045abc4ce1b","observation_id":"a7fb11ec-c84b-4f78-8ead-70771e40e399","resolution":{"observed_at":"2026-08-06T21:02:25.710086Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2012.62370","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:24.222262Z","title":"Towards energy-proportional datacenter memory with mobile dram, in: 2012 39th Annual International Sym- posium on Computer Architecture (ISCA), pp","venue":null,"work_id":"f575e8d2-406f-4081-a63f-17a2eea1f9d7","year":2012},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.397213Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:c48c8cd8882c93fa0c9e681b3e0cf19af6b16d6a5957711092e8b0fe82a90c79","observation_id":"d4f0848b-dd52-4eb1-a522-fdf68950ca60","resolution":{"observed_at":"2026-08-06T21:02:24.234838Z","resolver_source":"raw_fallback","status":"malformed_identifier"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.688240Z","title":"Exploration of gpgpu register file architecture using domain-wall-shift-write based racetrack memory, in: Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE, pp","venue":null,"work_id":"889231ba-62ca-4f00-b3de-9c7e5cb4c8ac","year":2014},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.401999Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:eed6a617a1dde519a0cfc5376545c33d1c2a928a8bb8a485b1737d1e73bca63a","observation_id":"d13926e3-0ccd-4216-90c2-2702aa3c6c4b","resolution":{"observed_at":"2026-08-06T21:02:25.693943Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.671137Z","title":"An energy- efficient gpgpu register file architecture using racetrack memory","venue":null,"work_id":"aea9f603-0699-43e3-aad7-45d09f9ab796","year":2017},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.406673Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:1455ef437e9a8966323e09e499a1a5761d5afcc659ac47a373d5fd825d470ea6","observation_id":"9f9f6a39-4d5e-4c7e-b5ea-27f3766b3eb9","resolution":{"observed_at":"2026-08-06T21:02:25.676900Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.654068Z","title":"Applied Physics Express 1, 091301","venue":null,"work_id":"e7e42a07-85c4-4361-98b1-2eab7afffdb5","year":2008},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.411477Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:d5cb83b8b0b6476319e6207ca3a577b7e282da21ac7b7c4fca0fe449d3d6dfa0","observation_id":"d7340a19-b320-48f7-9cc7-3809aca2db51","resolution":{"observed_at":"2026-08-06T21:02:25.659046Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.637281Z","title":"Zigzag: Enlarging joint architecture-mapping design space explo- ration for dnn accelerators","venue":null,"work_id":"0887ccac-f99d-45fd-a1c7-578f0061c09e","year":2021},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.417052Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:6f0776d079306d9cda1849fd52677084940cc4a4bede611d31a0b94b269963da","observation_id":"b6acf619-4a46-49ef-863c-515e29cb4fde","resolution":{"observed_at":"2026-08-06T21:02:25.642699Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.622138Z","title":"A spintronics full adder for magnetic cpu","venue":null,"work_id":"7ed845c0-d600-4bb9-978b-382d43c1d011","year":2005},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.422374Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:1aee75f3aefa92a2ced7626ba7e7503bf9d7b2c63e966550939c2046ce7d7ca6","observation_id":"9750e082-c255-453f-bf49-a1fd9493a0db","resolution":{"observed_at":"2026-08-06T21:02:25.626851Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.604715Z","title":"Anenergy-efficientprecision-scalable convnetprocessorin40-nmcmos.IEEEJournalofsolid-stateCircuits 52, 903–914","venue":null,"work_id":"d521a03d-1cc7-4f38-8bd3-8aab6281bf5d","year":2016},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.428215Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:cfe58a1de23b25a9793a6bb9194bd3815b88fca14b28fd30f7d53c7424a26260","observation_id":"999d3ed9-21d1-426a-ac0e-0255a1e96c17","resolution":{"observed_at":"2026-08-06T21:02:25.610021Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:23.432953Z","title":"Magneticdomain-wall racetrack memory","venue":null,"work_id":null,"year":2008},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.432953Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:675e9f3eb07da571a5253edcdda2db2793e6b311bfa8e517adde0b725ba53d96","observation_id":"b86a601b-88e9-4172-8d2b-e99f292ec56f","resolution":{"observed_at":"2026-08-06T21:02:23.432953Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.588362Z","title":"Pytorch: An imper- ative style, high-performance deep learning library, in: Advances in Neural Information Processing Systems 32","venue":null,"work_id":"4245d7bc-f566-47f8-9f62-da3f98ad9b1c","year":2019},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.437825Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:685f1f0f2e0cf8b0b456fb2ecf6d3922a19f05dfc997ef853e9039be65d5b8f8","observation_id":"c2df5e6a-8c5d-400b-a87f-eb8e024ba4a4","resolution":{"observed_at":"2026-08-06T21:02:25.593860Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.572384Z","title":"Parallelcom- putation in the racetrack memory","venue":null,"work_id":"a9e4065e-53d1-4aa9-9667-38bc9248e82a","year":2021},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.442592Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:2dfb040a953af03055be690e1ca34fac0f70f5a28858aa40483ff29ce957fefb","observation_id":"85fa95c3-0627-4cb8-b8b9-57134022cfa1","resolution":{"observed_at":"2026-08-06T21:02:25.577437Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:23.447290Z","title":"ImageNet Large Scale Visual Recognition Challenge","venue":null,"work_id":null,"year":2015},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":45,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.447290Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:59e5b88ec0d1e65cf5f5309df75e4de8c0ea0e3feebc37907f3de49eac8dae14","observation_id":"cbe88c31-ec94-48d0-825e-2865c47166e6","resolution":{"observed_at":"2026-08-06T21:02:23.447290Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.556176Z","title":null,"venue":null,"work_id":"2873512f-9996-46ba-8812-903930a57543","year":2018},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":46,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.452225Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:4cb0f3468b91414cd40f85196221c5333969450b507398fabf12006a09c37cdc","observation_id":"13fba473-2544-421e-b75d-6440f1e460b8","resolution":{"observed_at":"2026-08-06T21:02:25.561407Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.539119Z","title":"45nm freepdk library URL: https://si2.org/open-cell-library/","venue":null,"work_id":"2793da29-f116-47d7-8d38-decafc4a7ecb","year":2016},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":47,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.457034Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:b9443998dfbb1ae39692e578a43190bcade087f9673588caf2baf8470acafa7e","observation_id":"6c148211-7cd9-46b5-af2f-55418749c4da","resolution":{"observed_at":"2026-08-06T21:02:25.544587Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1409.1556","last_updated":"2015-04-10T16:25:04Z","snapshot_observed_at":"2026-08-17T19:17:06.411141Z","submitted_at":"2014-09-04T19:48:04Z","title":"Very Deep Convolutional Networks for Large-Scale Image Recognition","version":6},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1409.1556","snapshot_observed_at":"2026-08-06T21:02:23.462478Z","title":"Very deep convolutional net- works for large-scale image recognition, in: Bengio, Y., LeCun, Y","venue":null,"work_id":null,"year":2015},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":48,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.462478Z"},"links":{"cited_paper":"/paper/1409.1556","citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:0accb66a62b8a31484fbfd146cb37dfc9a502f282c6c651f2d0c3ffdd153d9cd","observation_id":"31f020c5-71cf-4fa5-9917-80aace26d7fe","resolution":{"observed_at":"2026-08-06T21:02:23.462478Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.523589Z","title":"Stt-ram buffer design for precision-tunable general-purpose neural network accelerator","venue":null,"work_id":"b45c2d06-a556-4b1c-9105-7b44af29d7c8","year":2017},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":49,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.468500Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:3046593bac1c93a51b2bf8730ed0f3e47773e34499fcf440535866c22a484a7b","observation_id":"d4c77d8d-7a53-4289-bcac-f5791df9edc3","resolution":{"observed_at":"2026-08-06T21:02:25.528704Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.507573Z","title":"Cross-layer racetrack memory design for ultra high density and low power consumption, in: Design AutomationConference(DAC),201350thACM/EDAC/IEEE,pp.1– 6","venue":null,"work_id":"365f2996-4769-414c-a952-5a1c43fe64bf","year":2013},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":50,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.473533Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:9bf857a4639c91bff0aa550492df7a8a9530f2239d981f56d35604afb6fc9d07","observation_id":"b220154b-6d2c-45af-81f8-3f24865e7723","resolution":{"observed_at":"2026-08-06T21:02:25.513719Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.491917Z","title":"Magnetic adder based on racetrack memory","venue":null,"work_id":"c4947585-17e6-4b12-b2fb-3217f45bad64","year":2013},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":51,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.478425Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:bdb6081e356f91cf29adeea994a0d7abd7a15589d89c79c1aa232f550ff1644b","observation_id":"30c35044-882a-400c-8493-0fcd2496895b","resolution":{"observed_at":"2026-08-06T21:02:25.497068Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.474878Z","title":"Stag: Spintronic-tape architecture for gpgpu cache hierarchies, in: Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on, pp","venue":null,"work_id":"4f90ec7b-d3ca-4bf0-a709-d2d093f245ff","year":2014},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":52,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.488517Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:a5c8bd92bfd087345ba688db5d8638797f4ff5dda40661ca94043ca80a254d13","observation_id":"3210ed56-23c6-4a35-bb35-c0ce5e9e8a45","resolution":{"observed_at":"2026-08-06T21:02:25.480334Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.457091Z","title":"Dwm- tapestri-an energy efficient all-spin cache using domain wall shift based writes, in: Proceedings of the Conference on Design, Automa- tion and Test in Europe, EDA Consortium","venue":null,"work_id":"fd1f23d2-222a-477c-92a1-4faab94294dd","year":2013},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":53,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.493979Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:fa461ef80e6b773a44be79455359628a7d565897ad7ddbf2803610c3f7b22ee4","observation_id":"ca63c2d5-8b3a-4e31-ba5c-eeed2a6d63b4","resolution":{"observed_at":"2026-08-06T21:02:25.463771Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.440583Z","title":"Ultra-dense ring-shaped racetrack memory cache design","venue":null,"work_id":"9d496178-c194-48a6-92f6-cbd248864ab2","year":2018},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":54,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.499587Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:cceea23ea7bc68990cd53d042d2f6c02aacd9cca28e1454a5a145a6ea99fd20b","observation_id":"e7a198a6-19c7-454c-9442-eba02b7c8b22","resolution":{"observed_at":"2026-08-06T21:02:25.446496Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.424796Z","title":"An automatic- addressingarchitecturewithfullyserializedaccessinracetrackmem- ory for energy-efficient cnns","venue":null,"work_id":"3679294c-dcd2-49cf-8eb6-9f57a6fc4c07","year":2020},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":55,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.505239Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:e846c4ec3e06a5c9c373783a8697b3c91fbb96f909e4627a5d55031f92720fd6","observation_id":"a9f2c575-1316-444d-a3ab-558ce8b06f8c","resolution":{"observed_at":"2026-08-06T21:02:25.429917Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.407686Z","title":"Dw-aes: A domain- wall nanowire-based aes for high throughput and energy-efficient data encryption in non-volatile memory","venue":null,"work_id":"f35ee033-2c77-44c1-a4f8-85e9bddcae7a","year":2016},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":56,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.511012Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:9ade587fdaef32e7089db169cfa4f5091b72174c5aae2d026e2c93585151a6be","observation_id":"99147cc2-e130-4c3c-bdc7-2fd4a39b180c","resolution":{"observed_at":"2026-08-06T21:02:25.412753Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.390408Z","title":"Energy efficient in- memory aes encryption based on nonvolatile domain-wall nanowire, in:Design,AutomationandTestinEuropeConferenceandExhibition (DATE), 2014, IEEE","venue":null,"work_id":"938e4961-42cf-4a7e-a0bb-3b3c2124efa2","year":2014},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":57,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.516690Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:73b7527fc0d80cbb031bef4751f5c9fe6ba7175b00f6ccc91e0aa98639bae9bf","observation_id":"b6d29d07-08f3-475f-8785-5e07f993dac6","resolution":{"observed_at":"2026-08-06T21:02:25.396959Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.373845Z","title":"Multilane racetrack caches: Improving efficiency through compression and independent shifting, in: Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific, IEEE","venue":null,"work_id":"e95a9e31-57a9-486f-9334-40215e289228","year":2015},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":58,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.521893Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:86966d5348e83e626c3bafedb82f56d7f78d6ae9ff606a75fa4bbc5feef9790a","observation_id":"8869f74e-05df-4a37-b0b8-a6b8e4f3a0e6","resolution":{"observed_at":"2026-08-06T21:02:25.379381Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1109/cvpr.2017.643","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T05:30:23.456663Z","title":"Designing energy-efficient convolutional neural networks using energy-aware pruning, in: 2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), pp","venue":null,"work_id":"0ab376fb-0df3-4b44-a5c1-7e6e93ed7063","year":2017},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":59,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.527045Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:06141c9e8e250fd9b420736aeea537cee7c221a305889288dbb2d29827cea014","observation_id":"cb963cd8-5bae-4a10-9ef0-7d2693aca709","resolution":{"observed_at":"2026-08-06T21:02:23.666851Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.357896Z","title":null,"venue":null,"work_id":"b8fbb027-3009-4578-9494-407cae87683f","year":null},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":60,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.534701Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:d0b8ce18b7889c0eda232100e7d3c25e85b218e08b2de0059769d5bb606054e6","observation_id":"3a45556b-fe70-467b-93c3-76aa48fc9e84","resolution":{"observed_at":"2026-08-06T21:02:25.362877Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.341756Z","title":"Energy-efficient nonvolatile reconfigurable logic using spin hall effect-based lookup tables","venue":null,"work_id":"608474a2-29e5-454d-8ac4-916dac0b17c8","year":2017},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":61,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.546260Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:1eaff2ba83b213879e8df2db2474d3f535919ae1dd3918b4a69b641629fcda57","observation_id":"dc403beb-c65d-4501-a60b-dd69571ea792","resolution":{"observed_at":"2026-08-06T21:02:25.346822Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1109/aspdac.2015","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:23.635077Z","title":"Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power, in: The 20th Asia and South Pacific Design Automation Conference, pp","venue":null,"work_id":"f67578be-8045-4f92-91ce-60a6146da3d9","year":null},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":62,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.552538Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:ea587797079d79aee21fff574e69b962bc592bc3db1f83fba44864bf53838405","observation_id":"5ebbc993-c421-4cb3-bd04-456f0abdc5aa","resolution":{"observed_at":"2026-08-06T21:02:23.642823Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:23.558712Z","title":"In-memory computation of a machine-learning classifier in a standard 6t sram array","venue":null,"work_id":null,"year":2017},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":63,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.558712Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:1f00e8e3c1b2d4b0aa9fc87d0531f627b73128f8b53411aee671e5e5f8814338","observation_id":"6adb23a0-2be9-4ebf-a9f6-6adddf6ce6b7","resolution":{"observed_at":"2026-08-06T21:02:23.558712Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.324204Z","title":"Magnetic skyrmion logic gates: conversion, duplication and merging of skyrmions","venue":null,"work_id":"ef480edf-0c7e-42ee-8c3f-ff7981021b5b","year":null},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":64,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.564855Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:506d914c669d29089684af959163230c26d0fe4896200dde302f2e6127efb6b1","observation_id":"f4aa87ee-7c6b-4409-8fea-674706e3b2c1","resolution":{"observed_at":"2026-08-06T21:02:25.329870Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.306043Z","title":"Perpendicular-magnetic-anisotropy cofeb racetrack mem- ory","venue":null,"work_id":"5a7cbc2b-c7b4-4d2c-be2c-5ac65195df01","year":2012},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":65,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.570369Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:b378b3b10ccd1feed973e462cb767b1e75af9092aa19e6317d0f3212d8ed1d5c","observation_id":"d4d3deb6-2e7b-4902-b5e7-0f26a3e1ad61","resolution":{"observed_at":"2026-08-06T21:02:25.312039Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.288978Z","title":null,"venue":null,"work_id":"a31bb45f-03ea-466a-9ece-6edff47e9c51","year":null},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":66,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.575905Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:11283aaba6bb47c1956ba782db232fd55a666ef576ce0aa31fbb8ac8b47c2874","observation_id":"d973c1d1-a73e-477c-af4c-633985f159c1","resolution":{"observed_at":"2026-08-06T21:02:25.294212Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1702.03044","last_updated":"2017-08-25T13:21:18Z","snapshot_observed_at":"2026-08-20T07:34:09.180609Z","submitted_at":"2017-02-10T02:30:22Z","title":"Incremental Network Quantization: Towards Lossless CNNs with Low-Precision Weights","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1702.03044","snapshot_observed_at":"2026-08-06T21:02:23.586520Z","title":"Incremen- tal network quantization: Towards lossless cnns with low-precision weights","venue":null,"work_id":null,"year":2017},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":67,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.586520Z"},"links":{"cited_paper":"/paper/1702.03044","citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:acc0a3e42e11e2f209d998c993a152ea0d89f19badcae9bb052724f95867fe8c","observation_id":"07b68028-6b05-4d77-984e-c9024c23bdd2","resolution":{"observed_at":"2026-08-06T21:02:23.586520Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.255392Z","title":"An efficient hardware accelerator for structured sparse convolutional neural networks on fpgas","venue":null,"work_id":"c91fff54-432c-4b0b-86a3-1a514220e53c","year":2020},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":68,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.592553Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:8e65adce22f84ac1f3104dbc2d680e157b62a7dcc6ae9e4b0707a014be85ef74","observation_id":"e19465bb-adb0-4592-b9c9-ad55c477110a","resolution":{"observed_at":"2026-08-06T21:02:25.260674Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1093/qjmam/4.2.236","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-10T05:30:23.456663Z","title":null,"venue":"The Quarterly Journal of Mechanics and Applied Mathematics","work_id":"44ca170f-aefb-4bfd-9153-acd0233b7319","year":null},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":240,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.205712Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:e4b576c93c5817de6b3ec85a0b7ef77c0d3ea310278d817a90cf29dd157c82c2","observation_id":"7a0b2cc2-d6ea-47c5-9882-bf437c88bdaa","resolution":{"observed_at":"2026-08-06T21:02:23.764836Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2012.22205","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:24.098702Z","title":null,"venue":null,"work_id":"41922b65-fe36-4143-8941-9bf1ab5df802","year":2012},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":1477,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.483502Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:7aa31e13e906f4546f83ef538724338269afecc6bf68f9a79a27d9bac458e06e","observation_id":"8a577fe4-9db1-4b28-a4c6-174d2704e398","resolution":{"observed_at":"2026-08-06T21:02:24.107735Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:25.272049Z","title":null,"venue":null,"work_id":"4df69c0c-d94a-4d08-8e09-3fe104586ee4","year":2013},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":2013,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.580731Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:1cb2d082d6cca6d8508dc290175d66a2fa42382d1df9d245442c5f9e7a7b72f3","observation_id":"dda02881-3381-42d8-9aca-65db0f5658ad","resolution":{"observed_at":"2026-08-06T21:02:25.277052Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2014.67428","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:23.991857Z","title":null,"venue":null,"work_id":"6880758c-3a25-41e8-99e4-aa46fe705e3a","year":2014},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":2014,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.540339Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:575ddb3c5ab18af76ce21a62753cbafc9eb09e3bb6357cdbf7a12545b5a3adc7","observation_id":"8aaf2473-e3b4-43a0-980a-a3da37336fad","resolution":{"observed_at":"2026-08-06T21:02:24.002239Z","resolver_source":"raw_fallback","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:23.367018Z","title":null,"venue":null,"work_id":null,"year":2017},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":2017,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.367018Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:2d228f8650101e0e151b39a10f0446e1538f6041f1f4cf82e1ea8e17ebca03a6","observation_id":"ad26b7a0-48ea-4710-a3cc-f8153d9b27df","resolution":{"observed_at":"2026-08-06T21:02:23.367018Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T21:02:23.281854Z","title":null,"venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems","version":1},"reference_index":2018,"source":"pdf_text","source_observed_at":"2026-08-06T21:02:23.281854Z"},"links":{"citing_paper":"/paper/2507.01429"},"observation_digest":"sha256:f810b9d75f10716143e61cabddf5a66e315bb09faf8b5472a57d83b987e482de","observation_id":"3eb766d5-5308-4790-9a1f-79c3242d8ce0","resolution":{"observed_at":"2026-08-06T21:02:23.281854Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"paper":{"arxiv_id":"2507.01429","last_updated":"2025-07-02T07:29:53Z","latest_version":1,"primary_category":"cs.ET","snapshot_observed_at":"2026-08-15T12:47:10.113434Z","submitted_at":"2025-07-02T07:29:53Z","title":"Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems"},"reference_resolution":{"displayed":74,"state_counts":{"malformed_identifier":3,"metadata_mismatch":7,"parse_uncertain":0,"unresolved":20,"verified_exact":5,"verified_fuzzy":39},"total_outbound_references":74},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"thesis":"As of 24 August 2026, this Paper Citation Record lists 74 of 74 outbound references and 0 inbound Pith citation observations for arXiv:2507.01429."}